US 6,784,019 B2Grant
Intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same
Issue Date:2004-08-31
•11 Claims
•8 Drawing Sheets
Abstract
A stacked dual-chip semiconductor packaging technology is proposed for the packaging of two semiconductor chips in one single package unit. The proposed dual-chip semiconductor package is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. By the proposed packaging technology, a first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip. Compared to the prior art, the proposed technology allows the packaging process to be implemented in a less complex and more cost-effective manner. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the semiconductor package.
Metadata
Assignee
- Siliconware Precision Industries Co., Ltd.
Inventor
- Chien-Ping Huang
Application Information
Application Number:US 10/219,245
Filing Date:2002-08-15
Priority Date:2001-04-03
Art Unit:7
Classifications
IPC:
H01L 2144H01L 2148H01L 2150
Field of Search:
438106438107438109438110438121438280438617438619257678257684257685257686257692257723257731257776257777257784
Patent Drawings (8 sheets)
Description
[0002] This is a Divisional of Ser. No. 09/865,760 filed on May 25, 2001, now U.S. application Ser. No. 6,462,422
Background of the Invention
[0003] 1. Field of the Invention:
[0004] This invention relates to semiconductor packaging technology, and more particularly, to an intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same, which is designed specifically for the packaging of two semiconductor chips in one single package unit.
[0005] 2. Description of Related Art:
[0006] Multi-chip packaging technology is used to pack two or more semiconductor chips in one single package unit, so that one single package unit is capable of offering a manifold level of functionality or data storage capacity. Memory chips, such as flash memory chips, are typically packaged in this way so as to allow one single memory module to offer an increased data storage capacity.
[0007] Related patents, include, for example, the U.S. Pat. No. 5,721,452 entitled “ANGULARLY OFFSET STACKED DIE MULTICHIP DEVICE AND METHOD OF MANUFACTURE”. This patent discloses an inventive semiconductor packaging technology that is designed for the packaging of two semiconductor chips in an offset die stacking arrangement to provide a dual-chip package.
[0008] The utilization of the foregoing patent, however, has several drawbacks. First, it requires the use of pillars to support the wire-bonding areas of the overlying chip, which would make the overall packaging process quite complex and thus costly to implement. Second, since the overlying chip is not coupled to die pad, it would make the finished semiconductor package poor in heat-dissipation efficiency. Third, since the stacked chips are adhered to each other by means of an adhesive layer, they would be easily subjected to delamination, resulting in reliability problem to the finished semiconductor package.
Summary of the Invention
[0009] It is therefore an objective of this invention to provide a new dual-chip semiconductor packaging technology, which can be fabricated without having to use pillars to support the wire-bonding areas of the packaged semiconductor chips.
[0010] It is another objective of this invention to provide a new dual-chip semiconductor packaging technology, which allows the packaging process to be implemented in a less complex and more cost-effective manner.
[0011] It is still another objective of this invention to provide a new dual-chip semiconductor packaging technology, which allows the packaged semiconductor chips to have an increased heat-dissipation efficiency.
[0012] It is yet another objective of this invention to provide a new dual-chip semiconductor packaging technology, which can be implemented without having to adhere the packaged semiconductor chips to each other so as to prevent delamination problem.
[0013] In accordance with the foregoing and other objectives, the invention proposes an intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same.
[0014] The semiconductor packaging technology according to the invention is characterized by an intercrossedly-stacked dual-chip arrangement which is constructed on a specially-designed leadframe having a supporting frame; a die pad supported on the supporting frame and having a peripherally-located upper portion and a centrally-located downset portion; and a set of leads linked to the supporting frame and arranged around the die pad. A first semiconductor chip is mounted within the downset portion of the die pad, while a second semiconductor chip is mounted on the upper portion of the die pad in an intercrossedly-stacked manner in relation to the first semiconductor chip.
[0015] Since the invention requires no pillars in the dual-chip structure, it allows the packaging process to be implemented in a less complex and more cost-effective manner than the prior art. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the package. In addition, since the invention can be implemented without having to adhere the two chips to each other, it can help prevent delamination problem. The invention is therefore more advantageous to use than the prior art.
Brief Description of Drawings
[0016] The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
[0017] FIG. 1A is a schematic diagram showing the top view of a specially-designed leadframe utilized by the first preferred embodiment of the invention;
[0018] FIG. 1B shows a sectional view of the leadframe of FIG. 1A cutting through the line A-A′;
[0019] FIG. 2A shows a top view of the mounting of a first semiconductor chip on the leadframe of FIGS. 1A-1B;
[0020] FIG. 2B shows a sectional view of the package construction of FIG. 2A;
[0021] FIG. 3A shows a top view of the mounting of a second semiconductor chip on the leadframe of FIGS. 1A-1B;
[0022] FIG. 3B shows a sectional view of the package construction of FIG. 3A;
[0023] FIG. 4A shows a top view of the wire bonding on the leadframe of FIGS. 1A-1B;
[0024] FIG. 4B shows a sectional view of the package construction of FIG. 4A;
[0025] FIG. 5A is a schematic diagram showing the top view of a specially-designed lead-frame with a semiconductor chip and bonding wires mounted thereon utilized by the second preferred embodiment of the invention;
[0026] FIG. 5B shows a sectional view of the preferred embodiment of FIG. 5A cutting through the line 5B—5B;
[0027] FIG. 6 is a schematic diagram showing the top view of a specially-designed lead-frame with a semiconductor chip and bonding wires mounted thereon utilized by the theird preferred embodiment of the invention;
[0028] FIG. 7A is a schematic diagram showing the top view of a speciall-designed lead-frame utilized by the fourth preferred embodiment of the invention;
[0029] FIG. 7B shows a sectional view of the leadframe of FIG. 7A.
[0030] FIG. 8 is a schematic diagram showing the top view of the leadframe in the fifth preferred emgodiment of the invention; and
[0031] FIG. 9 is a schematic diagram showing the top view of the leadframe in the sixth preferred embodiment of the invention.
Detailed Description of Preferred Embodiments
[0032] The intercrossedly-stacked dual-chip semiconductor package according to the invention is disclosed in full details by way of preferred embodiments in the following with reference to the accompanying drawings. Note that these drawings are simplified schematic diagrams showing only a small number of components related to the invention for demonstrative purpose and which are not drawn to actual sizes and scales in practical applications; the practical layout on the semiconductor package may be much more complex.
[0033] Referring to FIG. 1A and FIG. 1B, the intercrossedly-stacked dual-chip semiconductor package according to the invention is constructed on a specially-designed leadframe 10, which includes: (i) a supporting frame 11; (ii) a substantially rectangularly-shaped die pad 12 having a peripherally-located upper portion 12aand a centrally-located downset portion 12b, with the upper portion 12abeing linked via tie bars 13 to the supporting frame 11, and (iii) a set of leads 14 linked to the supporting frame 11 and arranged around the die pad 12, including a first subset of leads 14aand a second subset of leads 14b, wherein the first subset of leads 14aare oppositely arranged on the longer sides of the rectangularly-shaped die pad 12, while the second subset of leads 14bare oppositely arranged on the shorter sides of the same.
[0034] Alternatively, as illustrated in FIGS. 7A-7B, the downset portion 12bof the die pad 12 can be further formed with at least one opening 15 to help prevent delamination of a semiconductor chip (shown later in FIGS. 2A-2B with the reference numeral 20). Additionally, the opening formed on the downset portion 12bmay also be either a slot 15′ as shown in FIG. 8, or a slot group 15″ consisting of a plurality of slots as shown in FIG. 9, so as to achieve the same effect of preventing delamination.
[0035] Referring further to FIG. 2A and FIG. 2B, in the next step, a first die-attachment process is performed to mount a first semiconductor chip 20 (which has an active surface 20aand an inactive surface 20b) within the downset portion 12bof the die pad 12 by adhering its inactive surface 20bwith an adhesive layer 21, such as silver epoxy, thereto.
[0036] And, the total height of the first semiconductor chip 20 plus the adhesive layer 21 shouldn't exceed the upper portion 12aof the die pad 12 (i.e., the active surface 20aof the first semiconductor chip 20 should be lower than the upper portion 12aof the die pad 12).
[0037] Then a first wire-bonding is performed to bond a dirst set of bonding wires 41 for electically connecting respective I/O pads 22 of the first semiconductor chip 20 to the first subset of leads 14aof theset of leads 14.
[0038] Referring further to FIG. 3A and FIG. 3B, in the next step, a second die-attachment process is performed to mount a second semiconductor chip 30 having a size approximately same as the first semiconductor chip 20 (which has an active surface 30aand an inactive surface 30b) on the upper portion 12aof the die pad 12 by adhering its inactive surface 30bwith an adhesive layer 31, such as silver epoxy, thereto and arranged in an intercrossed manner in relation to the first semiconductor chip 20. As illustrated in FIG. 3A, this die attachment results in an intercrossedly-stacked dual-chip arrangement for the two chips 20, 30 on the die pad 12.
[0039] In the aforementioned second die-attachment process, the second semiconductor chip 30 substantially rectangularly-shaped and has its the shorter sides shorter in length than the longer sides of the first semiconductor chip 20. However, another embodiment with a second semiconductor chip 30′ in a size larger than a first semiconductor chip 20′ is shown in FIG. 5A and FIG. 5B, wherein the first semiconductor chip 20′ is mounted on the downset portion of the die pad 12. Further, the first semiconductor chip 20′ has an active surface and an inactive surface, wherein the active surface is substantially in a rectangular shape with a plurality of I/O pads 22 formed on the longer sides thereof.
[0040] Referring further to FIG. 4A and FIG. 4B, in the next step, a second wire-bonding process is performed to bond a second subset of bonding wires 42 for electrically connecting respectivethe I/O pads 32 of the second semiconductor chip 30 to the second subset of leads 14b. It can be seen from the illustration of FIG. 4A that, since the I/O pads 22, 32 are arranged on the shorter sides of the respective chips 20, 30, it allows both the first subset of bonding wires 41 and the second subset of bonding wires 42 to be conveniently routed to the nearby first subset of leads 14aand the second subset of leads 14b.
[0041] Referring further to FIG. 5A and FIG. 5B, when the first semiconductor chip 20′ has a smaller size than the second semiconductor chip 30′, the dual chips can be arranged in such a manner that a spacing there between is only required to be sufficient for bonding the first set of bonding wires 41; whereas the dual-chip arrangement can be in the case as shown in FIG. 6 when a first semiconductor chip 20″ is larger than a second semiconductor chip 30″.
[0042] Subsequent steps to finish the semiconductor package include an encapsulation step to encapsulate the two semiconductor chips 20, 30, and a singulation step to cut away the supporting frame 11 to singulate each individual package unit. These steps are all conventional processes, so description thereof will not be further detailed.
[0043] Additionally, besides the square—square, rectangle—rectangle or square-rectangle combination proposed in the aforementioned embodiments, the dual chips mounted on the lead frame 10 of the invention can also be in other combination's of shapes dependent on the integrated circuit design, the singulation technique or other technical requirements. Moreover, besides the intercrossedly-stacked arrangements shown in the aforementioned embodiments, the dual chips can also be in arrangement with one of the chips being rotated by an angle with respect to the other, so as to achieve the same effect of intercrossedly stacking the chips.
[0044] Compared to the prior art, since the invention requires no pillars in the dual-chip structure, it allows the packaging process to be implemented in a less complex and more cost-effective manner than the prior art. Moreover, since the underlying chip is attached to die pad, it allows an increased heat-dissipation efficiency to the package. In addition, since the invention can be implemented without having to adhere the packaged semiconductor chips to each other, it can help prevent delamination problem. The invention is therefore more advantageous to use than the prior art.
[0045] The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements, for example, replacing the opening or slot of the downset portion 12bof the die pad 12 by other shapes, modifying the arrangement of the slots of the slot group etc. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
What is claimed is:
1. A method for fabricating a semiconductor package, comprising the steps of:
(1) preparing a leadframe, which includes:
a die pad having a peripherally-located upper portion and a centrally-located downset portion; and
a set of leads arranged around the die pad;
(2) performing a first die-attachment process to mount a first semiconductor chip on the downset portion of the die pad;
the first semiconductor chip having a substantially rectangularly-shaped active surface formed with a plurality of I/O pads along the shorter sides thereof and an inactive surface adhered to the centrally-located downset portion of the die pad;
(3) performing a first wire-bonding pricess to bond a set of bonding wires for electrically connecting the respective I/O pads of the first semiconductor chip to the corresponding leads;
(4) performing a second die-attachment process to mount a second semiconductor chip on the die pad;
the second semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad so as to form an intercrossedly-stacked dual-chip arrangement with the first semiconductor chip; and
(5) performing a second wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the second semiconductor chip to the corresponding leads.
2. The semiconductor package of claim 1, wherein in said step (1), the centrally-located downset portion of the die pad is further formed with at least one opening to help prevent the first semiconductor chip from delamination.
3. The semiconductor package of claim 1, wherein in said step (1), the centrally-located downset portion of the die pad is further formed with at least on e slot to help prevent the first semiconductor chi from delamination.
4. The semiconductor package of claim 1, 2 or 3, wherein in said step (2), the inactive surface of the first semiconductor chip is adhered to the downset portion of the die pad by means of silver epoxy.
5. The semiconductor package of claim 1, 2 or 3, wherein in said step (3), the inactive surface of the second semiconductor chip is adhered to the upper portion of the die pad by means of silver epoxy.
6. The semiconductor package of claim 1, 2 or 3, wherein in said step (3) and (15), the bonding wires are gold wires.
7. A method for fabricating a semiconductor package, comprising the steps of:
(1) preparing a leadframe, which includes:
a die pad having a peripherally-located upper portion and a centrally-located downset portion;
a set of leads arranged around the die pad;
(2) forming at least one opening in the downset portion of the die pad;
(3) performing a first die-attachment process to mount a first semiconductor chip on the downset portion of the die pad; the first semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the centrally-located downset portion of the die pad;
(4) performing a first wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the first semiconductor chip to the corresponding leads;
(5) performing a second die-attachment process to mount a second semiconductor chip on the upper portion of the die pad;
the second semiconductor chip having an active surface formed with a plurality of I/O pads and an inactive surface adhered to the upper portion of the die pad, and being located above the first semiconductor chip to form an intercrossedly-stacked dual-chip arrangement; and
(6) performing a second wire-bonding process to bond a set of bonding wires for electrically connecting the respective I/O pads of the second semiconductor chip to the leads.
8. The semiconductor package of claim 7, wherein in said step (3), the inactive surface of the first semiconductor chip is adhered to the downset portion of the die pad by means of silver epoxy.
9. The semiconductor package of claim 8, wherein in said step (5), the inactive surface of the second semiconductor chip is adhered to the upper portion of the die pad by means of silver epoxy.
10. The semiconductor package of claim 7, wherein in said step (4) and (6), the bonding wires are gold wires.
11. The semiconductor package of claim 7, wherein the opening on the downset portion of the die pad is a slot.