Magnetic memory

[0002] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-401342, filed on Dec. 28, 2001, and the prior Japanese Patent Application No. 2002-286653, filed on Sep. 30, 2002; the entire contents of which are incorporated herein by reference.

[0003] This invention relates to a magnetic memory, and more particularly, to a large-capacity high-speed magnetic memory having a structure stacking memory arrays including magnetoresistance effect elements of a ferromagnetic tunneling type, for example, and reduced in influences from fluctuations of properties such as junction resistance and MR ratio.

[0004] Magnetoresistance effect elements using magnetic films are currently used in magnetic heads, magnetic sensors, etc., and there is a proposal to use magnetoresistance effect elements in a solid-state magnetic memory (magnetoresistance memory or MRAM (magnetic random access memory)).

[0005] Recently, a so-called “tunneling magnetoresistance effect element (TMR element) has been proposed as a magnetoresistance effect element configured to flow a current perpendicularly to the film plane in a sandwich-structured film interposing a single dielectric layer between two magnetic metal layers and to use the tunneling current. Since tunneling magnetoresistance effect elements have been improved to ensure 20% or higher ratio of change in magnetoresistance (J. Appl. Phys. 79, 4724 (1996)), the possibility of civilian applications of MRAM is increasing.

[0006] A tunneling magnetoresistance effect element can be obtained by first forming a thin Al (aluminum) layer, 0.6 nm through 2.0 nm thick, on a ferromagnetic electrode, and thereafter exposing its surface to a glow discharge of oxygen or oxygen gas to form a tunnel barrier layer of Al₂O₃.

[0007] There is also proposed a ferromagnetic single tunneling junction structure in which an anti-ferromagnetic layer is provided in one of the ferromagnetic layers on one side of the single ferromagnetic tunneling junction and the other ferromagnetic layer is used as a magnetically pinned layer (Japanese Patent Laid-Open Publication No. H10-4227).

[0008] Other type ferromagnetic tunneling junction structures, namely, one having a ferromagnetic tunneling junction via magnetic particles distributed in a dielectric material and one having double ferromagnetic tunneling junctions (continuous film) have been proposed as well (Phys. Rev. B56(10), R5747 (1997), J. The Magnetics Society of Japan 23, 4-2, (1999), Appl. Phys. Lett. 73(19), 2829 (1998), Jpn. J. Appl. Phys. 39, L1035(2001)).

[0009] Also these ferromagnetic tunneling junctions have been improved to ensure a ratio of magnetoresistive change from 20 to 50% and to prevent a decrease of the ratio of magnetoresistive change even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage, and there is the possibility of their applications to MRAM.

[0010] Magnetic recording elements using such a single ferromagnetic tunneling junction or double ferromagnetic tunneling junctions are nonvolatile and have high potentials such as high write and read speed not slower than 10 nanoseconds and programmable frequency not less than 10¹⁵times. Especially, ferromagnetic double-tunneling structures ensure large output voltages and exhibit favorable properties as magnetic recording elements because the ratio of magnetoresistive change does not decrease even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage value as mentioned above.

[0011] With regard to the memory cell size, however, those existing techniques involve the problem that the size cannot be decreased below semiconductor DRAM (dynamic random access memory) when a 1 Tr (transistor)-1 TMR architecture (disclosed, for example, in U.S. Pat. No. 5,734,605) is employed.

[0012] For overcoming the problem, there are proposals such as a diode-type architecture in which TMR cells and diodes are serially connected between bit lines and word lines (U.S. Pat. No. 5,640,343), and a simple-matrix architecture in which TMR cells are placed between bit lines and word lines (DE 19744095, WO 9914760).

[0013] However, if the bit size is decreased to increase the memory capacity, then the output from the magnetoresistance effect element also decreases, and S/N upon recording and reproduction decreases.

[0014] In case two magnetoresistance effect elements are combined to perform so-called “differential operation” by recording data in these elements in a complementary manner and detecting a difference between their outputs, it is possible to double the output signal and obtain higher S/N. However, in order to perform such differential operation, recording and reading with the pair of combined magnetoresistance effect elements must be conducted under the same condition. If the recording or reading condition of one of the magnetoresistance effect elements varies, the output signal also varies, and a recording/reproducing error occurs.

[0015] Therefore, an architecture less affected by such fluctuations is indispensable to realize a giant capacity magnetic memory.

[0016] According to an embodiment of the invention, there is provided a magnetic memory comprising:

[0017] a first wiring extending in a first direction;

[0018] a first magnetoresistance effect element formed on the first wiring and having a magnetic recording layer;

[0019] a second magnetoresistance effect element formed under the first wiring and having a magnetic recording layer;

[0020] a second wiring extending in a direction across the first direction above the first wiring;

[0021] a third wiring extending in a direction across the first direction below the first wiring;

[0022] a recording circuit which supplies a current to the first wiring while supplying a current to the second and third wirings respectively, and thereby exerting a current magnetic field to the magnetic recording layers in order to record one of two values of two-valued information; and

[0023] a reading circuit which detects a difference between output signals obtained from the magnetoresistance effect elements by supplying a sense current to the first and second magnetoresistance effect elements via the first wiring in order to read out the recorded data as one of two values of the two-valued information,

[0024] directions of magnetization in the recording layers of the first and second magnetoresistance effect elements being oriented in opposite directions from each other by supplying the current to the first wiring upon recording of one of two values of the two-valued information.

[0025] According to another embodiment of the invention, there is provided a magnetic memory comprising:

[0026] a first wiring extending in a first direction;

[0027] a first magnetoresistance effect element formed on the first wiring and having a magnetic recording layer;

[0028] a second magnetoresistance effect element formed under the first wiring and having a magnetic recording layer;

[0029] a second wiring extending in a direction across the first direction above the first wiring;

[0030] a third wiring extending in a direction across the first direction below the first wiring;

[0031] one end of the second wiring and one end of the third wiring being connected together to form a single current path;

[0032] a recording circuit which supplies a current to the first wiring while supplying a current to the single current path, and thereby exerting a current magnetic field to the magnetic recording layers in order to record one of two values of two-valued information; and

[0033] a reading circuit which detects a difference between output signals obtained from the magnetoresistance effect elements by supplying a sense current to the first and second magnetoresistance effect elements via the first wiring in order to read out the recorded data as one of two values of the two-valued information,

[0034] directions of magnetization in the recording layers of the first and second magnetoresistance effect elements being oriented in opposite directions from each other by supplying the current to the first wiring upon recording of one of two values of the two-valued information.

[0035] According to yet another embodiment of the invention, there is provided a magnetic memory comprising:

[0036] a first wiring extending in a first direction;

[0037] a first magnetoresistance effect element formed on the first wiring and having a magnetic recording layer;

[0038] a second magnetoresistance effect element formed under the first wiring and having a magnetic recording layer;

[0039] a second wiring extending in a direction across the first direction above the first wiring;

[0040] a third wiring extending in a direction across the first direction below the first wiring;

[0041] a recording circuit which supplies a current to the first wiring while supplying a current to at least one of the second and third wirings, and thereby exerting a current magnetic field to at least one of the magnetic recording layers in order to record one of multiple values of multi-valued information; and

[0042] a reading circuit which detects a difference between output signals obtained from the magnetoresistance effect elements by supplying a sense current to the first and second magnetoresistance effect elements via the first wiring in order to read out the recorded data as one of multiple values of the multi-valued information

[0043] According to yet another embodiment of the invention, there is provided a magnetic memory comprising:

[0044] a first wiring extending in a first direction;

[0045] a first magnetoresistance effect element formed on the first wiring and having a magnetic recording layer;

[0046] a second magnetoresistance effect element formed under the first wiring and having a magnetic recording layer;

[0047] a second wiring extending in a direction across the first direction above the first wiring;

[0048] a third wiring extending in a direction across the first direction below the first wiring;

[0049] a switching element connected between one end of the second wiring and one end of the third wiring;

[0050] a recording circuit which controls the switching element to hold the one end of the second wiring and the one end of the third wiring in connection to form a single current path and supplies a current to the first wiring while supplying a current to the single current path, and thereby exerting a current magnetic field to the magnetic recording layers in order to record one of multiple values of multi-valued information, the recording circuit controlling the switching element to hold the one end of the second wiring and the one end of the third wiring in disconnection and supplying a current to the first wiring while supplying a current to at least one of the second and third wirings, and thereby exerting a current magnetic field to at least one of the magnetic recording layers in order to record another of multiple values of the multi-valued information; and

[0051] a reading circuit which detects a difference between output signals obtained from the magnetoresistance effect elements by supplying a sense current to the first and second magnetoresistance effect elements via the first wiring in order to read out the recorded data as one of the multiple values of the multi-valued information.

[0052] Because the above-summarized structure uses the pair of magnetoresistance effect elements stacked on and under the first wiring and makes use of their differential operation, it contributes to preventing fluctuations of the wiring environment, stabilizing the differential operation, simplifying the memory cell structure and thereby realizing a large-capacity high-integrated memory.

[0053] In the specification, the term “multi-valued information” means information of three or more values, such as information of four values including the “0” level, “1” level, “2” level and “3” level.

[0054] According to this and other embodiments of the invention, wiring environments of the pair of magnetoresistance effect elements can be uniformed by locating these magnetoresistance effect elements closely on and under the bit line.

[0055] As a result, even upon differential operation or multi-valued recording, reading or writing errors caused by fluctuations of signals can be removed.

[0056] Additionally, since the degree of integration of memory cells can be increased and their structure can be simplified, a giant-capacity, high-speed magnetic memory can be realized easily.

[0057] The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the embodiments of the invention. However, the drawings are not intended to imply limitation of the invention to a specific embodiment, but are for explanation and understanding only.

[0058] In the drawings:

[0059] FIG. 1 is a schematic cross-sectional view illustrating a multi-layered structure of a unit cell in a magnetic memory according to an embodiment of the invention in a simplified form;

[0060] FIG. 2 is a schematic diagram showing a specific example in which a pair of magnetoresistance effect elements C1, C2 are offset in the lengthwise direction of a bit line BL;

[0061] FIGS. 3A and 3B are schematic diagrams for explaining data writing in case a differential operation architecture is employed;

[0062] FIGS. 4A and 4B are schematic diagrams showing a wiring structure in which end portions of digit lines DL1, DL2 connected respectively on and under the magnetoresistance effect elements C1, C2 are connected together;

[0063] FIGS. 5A and 5B are schematic diagrams showing a wiring structure in which end portions of digit lines DL1, DL2″ connected respectively on and under the magnetoresistance effect elements C1, C2 are connected together;

[0064] FIG. 6 is a transparent plan view schematically showing the reversal direction of magnetization M of a magnetic recording layer of the magnetoresistance effect element C1 interposed between a bit line BL and a digit line DL;

[0065] FIGS. 7A and 7B are schematic diagrams showing a multi-valued recording memory cell according to an embodiment of the invention;

[0066] FIGS. 8A through 8C are schematic diagrams showing a wiring structure of vertically differential MRAM capable of recording multi-valued information, in which one set of opposite ends of two digit lines DL1, DL2 extending across bit lines BL can be connected via a switching element;

[0067] FIGS. 9A through 9C are schematic diagrams showing a wiring structure of vertically differential MRAM capable of recording multi-valued information, in which one set of opposite ends of two digit lines DL1, DL2 extending across bit lines BL can be connected via a switching element;

[0068] FIGS. 10A through 10C are schematic diagrams showing a wiring structure of vertically differential MRAM capable of recording multi-valued information, in which one set of opposite ends of two digit lines DL1, DL2 extending across bit lines BL can be connected via a switching element;

[0069] FIGS. 11A through 11C are schematic diagrams showing a wiring structure of vertically differential MRAM capable of recording multi-valued information, in which one set of opposite ends of two digit lines DL1, DL2 extending across bit lines BL can be connected via a switching element;

[0070] FIG. 12 is a schematic diagram showing a cross-sectional structure of a magnetoresistance effect element having a single ferromagnetic tunneling junction;

[0071] FIG. 13 is a schematic diagram showing a cross-sectional structure of a magnetoresistance effect element having a single ferromagnetic tunneling junction;

[0072] FIG. 14 is a schematic diagram showing a cross-sectional structure of a magnetoresistance effect element having double ferromagnetic tunneling junctions;

[0073] FIG. 15 is a schematic diagram showing a cross-sectional structure of a magnetoresistance effect element having double ferromagnetic tunneling junctions;

[0074] FIG. 16 is a schematic diagram showing a cross-sectional structure of a magnetoresistance effect element having double ferromagnetic tunneling junctions;

[0075] FIGS. 17A through 17F are schematic diagrams exemplifying plane geometries and corresponding directions of magnetization of magnetic recording layers of magnetoresistance effect elements;

[0076] FIG. 18 is a diagram showing an architecture according to an embodiment of the invention when using CMOS;

[0077] FIG. 19 is a schematic diagram the second specific example of the architecture usable in an embodiment of the invention;

[0078] FIG. 20 is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using the architecture of FIG. 19;

[0079] FIGS. 21A and 21B are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 19;

[0080] FIG. 22 is a schematic diagram showing the third specific example of the architecture available for stacking memory arrays;

[0081] FIGS. 23A and 23B are cross-sectional schematic diagrams showing a memory cell of a differential operation type made by using the architecture of FIG. 22;

[0082] FIGS. 24A through 24C are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 22;

[0083] FIG. 25 is a schematic diagram showing the fourth specific example of the architecture available for stacking memory arrays;

[0084] FIGS. 26A and 26B are cross-sectional schematic diagrams showing a memory cell of a differential operation type made by using the architecture of FIG. 25;

[0085] FIGS. 27A through 27C are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 25;

[0086] FIG. 28 is a schematic diagram the fifth specific example of the architecture usable in an embodiment of the invention;

[0087] FIG. 29 is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using ferromagnetic single-tunneling elements as the magnetoresistance effect elements C1, C2 in the architecture of FIG. 28;

[0088] FIG. 30 is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using ferromagnetic double-tunneling elements as the magnetoresistance effect elements C1, C2 in the architecture of FIG. 28;

[0089] FIG. 31 is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using ferromagnetic single-tunneling elements as the magnetoresistance effect elements C1, C2 and using a three-layered structure of a ferromagnetic layer FM, nonmagnetic layer NM and ferromagnetic layer FM as the recording layer in the architecture of FIG. 28;

[0090] FIGS. 32A and 32B are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 28;

[0091] FIGS. 33A and 33B are schematic diagrams exemplifying a memory cell including an overcoat layer SM;

[0092] FIGS. 34A and 34B are schematic diagrams exemplifying a memory cell including an overcoat layer SM;

[0093] FIGS. 35A and 35B are schematic diagrams exemplifying a memory cell including an overcoat layer SM;

[0094] FIG. 36 is a schematic diagram exemplifying a cross-sectional structure of a magnetic memory made by stacking memory cells of the architecture of the differential operation type shown in FIG. 29;

[0095] FIGS. 37A through 37C are schematic diagrams exemplifying a cross-sectional structure of a magnetic memory made by stacking memory cells of the architecture of the multi-valued recording type shown in FIG. 24;

[0096] FIG. 38 is a schematic diagram showing a memory cross-sectional structure capable of uniforming the wiring environments of read wirings M1, M2;

[0097] FIG. 39 is a table showing measured values of output voltages of magnetoresistance effect elements C1, C2 obtained in the first Example of the invention;

[0098] FIGS. 40A and 40B are graph diagrams showing a result of differential operation;

[0099] FIGS. 41A and 41B are graph diagrams showing a result of multi-valued recording operation;

[0100] FIG. 42 is a table showing measured values of output voltages of magnetoresistance effect elements C1, C2 obtained in the second Example of the invention;

[0101] FIGS. 43A and 43B are graph diagrams showing a result of differential operation;

[0102] FIGS. 44A and 44B are graph diagrams showing a result of multi-valued recording operation;

[0103] FIG. 45 is a conceptual diagram exemplifying a whole structure of a magnetic memory according to the third Example of the invention; and

[0104] FIG. 46 is a conceptual diagram exemplifying a whole structure of a magnetic memory according to the fourth Example of the invention.

[0105] Some embodiments of the invention will now be explained below with reference to the drawings.

[0106] FIG. 1 is a schematic cross-sectional view illustrating a multi-layered structure of a unit cell in a magnetic memory according to an embodiment of the invention in a simplified form. In this embodiment, a pair of magnetoresistance effect elements C1, C2 are disposed on and under a bit line BL as shown in FIG. 1.

[0107] In the specific example shown here, digit lines DL1, DL2, read wirings M1, M2 are formed to extend across a bit line BL, and a pair of magnetoresistance effect elements C1, C2 are formed at the crossing area between the bit line BL and the digit lines DL1, DL2.

[0108] These magnetoresistance effect elements C1, C2, which will be explained later in greater detail, each have a recording layer made of a ferromagnetic layer, and magnetization of opposite directions is recorded in these recording layers. That is, the pair of magnetoresistance effect elements C1, C2 operate in a complementary manner. Reproduced signals from the magnetoresistance effect elements C1, C2 are differentially operated by an amplifier SA through read wirings M1, M2. In this manner, reproduced signals from the magnetoresistance effect elements can be doubled, and recording and reproduction with high S/N (signal to noise) can be carried out.

[0109] As explained later in greater detail, this architecture enables multi-valued recording when the upper and lower magnetoresistance effect elements C1, C2 are changed in signal output.

[0110] The embodiment of the invention makes it possible to prevent influences of a difference of the wiring environments, simultaneously reduce the cell area and therefore realize a high degree of integration by stacking the magnetoresistance effect elements for differential operation closely on and under the bit line BL.

[0111] That is, by close positioning of the pair of magnetoresistance effect elements C1, C2 on and under the bit line BL, information can be read out (or written) with the upper and lower magnetoresistance effect elements C1, C2 via the same bit line BL, and “deviation” caused by a difference of the wiring path environments can be prevented. This result is remarkable especially when differential operation or multi-valued recording is carried out by using the pair of magnetoresistance effect elements, and read (or write) errors caused by a difference of the wiring environment between the upper and lower magnetoresistance effect elements can be prevented reliably and easily.

[0112] Additionally, according to the embodiment of the invention, since the pair of magnetoresistance effect elements C1, C2 are closely located on and under the bit line BL, the element structure can be simplified and compacted. Therefore, the embodiment is advantageous also for realization of a high degree of integration and easier fabrication.

[0113] As explained later in greater detail, various specific examples can be employed for connection of the bit line BL and digit lines DL (DL1, DL2) with the magnetoresistance effect elements C (C1, C2). For example, two bit lines may be provided for the writing use and the reading use, respectively, and may be connected to the magnetoresistance effect elements. The digit lines may be connected to the magnetoresistance effect elements in a specific example, or need not be connected in another specific example.

[0114] Although FIG. 1 shows the pair of magnetoresistance effect elements C1, C2 as lying in approximately symmetric positions on and under the bit line BL, the invention is not limited to such configurations. In embodiments of the invention, it is sufficient that the wiring environments are substantially equal between the upper and lower magnetoresistance effect elements.

[0115] Therefore, as shown in FIG. 2, for example, the pair of magnetoresistance effect elements C1, C2 may be “offset” to a certain extent along the lengthwise direction of the bit line BL. Alternatively, the magnetoresistance effect elements C1, C2 may be offset along the width direction of the bit line BL.

[0116] Each magnetoresistance effect element C (C1, C2) has a “TMR (tunneling magnetoresistance effect)” structure, “spin valve” structure, or other like structure. In any of these cases, the magnetoresistance effect element includes a magnetic recording layer made of a ferromagnetic material. Information can be recorded in this recording layer by applying magnetization of a predetermined orientation.

[0117] Separately from the magnetic recording layer, each magnetoresistance effect element C includes a magnetically pinned layer in which direction of magnetization is fixed in a predetermined direction. Accordingly, in each magnetoresistance effect element C, its output signal changes in accordance with the relation of magnetization between the pinned layer and the magnetic recording layer. Therefore, if the directions of magnetization of the magnetic recording layers or the magnetically pinned layers are determined to double the outputs of the upper and lower magnetoresistance effect elements C1, C2, the two-valued information of “1” and “0” can be recorded or reproduced with a high S/N ratio by their differential operation.

[0118] If the magnetoresistance effect elements C1, C2 are configured to be different in output current level, multi-valued recording is possible. For example, as explained later in greater detail, when the output levels of the upper and lower magnetoresistance effect elements C1, C2 are changed by changing their structures, another output level other than two kinds of output levels, namely the doubled or canceling-out, when they elements are operated in a differential mode.

[0119] Writing of information in the magnetoresistance effect elements C (C1, C2) can be carried out with magnetic fields generated by, for example, flowing a current pulse to the digit lines DL (DL1, DL2) and the bit line BL on and under the elements C. More specifically, when an electric current is supplied to the bit line BL and the digit lines DL1, DL2, current magnetic fields are generated around them. A writing magnetic field composing these current magnetic fields reverts magnetization of the magnetic recording layers of the magnetoresistance effect elements C1, C2. Upon such writing, a current pulse in the optimum direction to generate a composite magnetic field in a predetermined direction may be appropriately flown to the bit line BL and the digit lines DL1, DL2.

[0120] In this manner, it is possible to reduce the quantity of current per each wiring and facilitate selection of a cell for writing as compared with the technique relying on generating magnetic reversal by flowing a current solely to the bit line or the digit lines. This contributes to realizing a reliable magnetic memory reduced in wiring fatigue.

[0121] FIGS. 3A and 3B are schematic diagrams for explaining data writing in case a differential operation architecture is employed. FIG. 3A is a cross-sectional view taken along a plane perpendicular to the lengthwise direction of the bit line BL. FIG. 3B is a cross-sectional view taken along a plane parallel to the lengthwise direction of the bit line BL.

[0122] The magnetoresistance effect elements C1, C2 shown here are tunneling magneto-resistance effect (TMR) elements in which a ferromagnetic layer 52, tunnel barrier layer 54, ferromagnetic layer magnetically pinned in a predetermined direction (also called “pinned layer” or “magnetically pinned layer”) 56, and anti-ferromagnetic layer 58 are stacked in the written order. The anti-ferromagnetic layer 58 functions to pin the magnetization of the ferromagnetic layer 56 as the pinned layer.

[0123] The magnetoresistance effect elements C1, C2 used in the embodiment of the invention are not limited to TMR elements. A “spin valve” structure having a nonmagnetic layer inserted between a pair of ferromagnetic layer, for example, is also usable.

[0124] For writing, a predetermined writing current I is flown to the digit lines DL1, DL2 and the bit line BL, respectively, to apply their composite magnetic field to the recording layers 52 of the magnetoresistance effect elements C1, C2 and appropriately revert the magnetization spins.

[0125] In case the magnetoresistance effect elements C1, C2 are operated in a differential mode for recording or reading two-valued information, complementary data are written in the upper and lower magnetoresistance effect elements C1, C2, and their combination is read out as one of two-valued information.

[0126] FIGS. 3A and 3B illustrate a method of magnetization spins of the magnetoresistance effect elements C1, C2 by arrows. In this specific example, magnetization of the ferromagnetic layers (pinned layers) 56 of the upper and lower magnetoresistance effect elements C1, C2 is pinned in the same direction. Then the writing is carried out to oppositely orient the upper and lower recording layers 52 in magnetization direction.

[0127] For example, as shown in FIGS. 3A and 3B, writing is carried out in the magnetoresistance effect element C1 to orient the magnetization of the recording layer 52 in the same direction (called “parallel direction”) of magnetization of the pinned layer 56, and in the magnetoresistance effect element C2 to orient the magnetization of the recording layer 52 in the opposite direction (called “anti-parallel direction”) from the magnetization of the pinned layer 56. Then a difference between output voltages (or resistance or current values) of the magnetoresistance effect elements C1, C2 is detected. In this manner, the output signal can be doubled by differential operation, and a high S/N ratio is obtained. This mode of operation will be explained later in greater detail in conjunction with Examples.

[0128] When the magnetoresistance effect elements C1, C2 are operated in a differential mode, their easy axes magnetization are preferably oriented in parallel, that is, perpendicularly to the bit line BL. As a result, magnetic fields applied to the upper and magnetoresistance effect elements C1, C2 by flowing a current pulse in the bit line BL function in parallel or in anti-parallel to the easy axes of magnetization of the recording layers. Therefore, information can be written simultaneously in the upper and lower magnetoresistance effect elements C1, C2, and high-speed writing is attained.

[0129] In the above-explained architecture, since a current is flown to the upper and lower digit lines, the sum of the current flowing in the digit lines is double the ordinary value, and the architecture is disadvantageous from the viewpoint of the power consumption. Additionally, since the double current must be supplied, the area of the driver for supplying the current to the digit lines inevitably increases. This invites the disadvantage that the ratio of the memory area relative to the chip area (array efficiency) decreases.

[0130] To overcome these problems, one of opposite ends of the digit line DL1 and an adjacent end of the digital line DL2 on and under the magnetoresistance effect elements C1, C2 may be connected together as shown in FIGS. 4A, 4B, 5A and 5B.

[0131] In case of the structure shown in FIGS. 4A, 4B, 5A and 5B, a plurality of magnetoresistance effect elements C1, C2 are symmetrically positioned on and under the bit line BL, and “1” and “0” can be detected by differential amplification of the upper and lower magnetoresistance effect elements C1, C2.

[0132] In the vertical differential MRAM of this type, two digit lines (writing word lines) DL1, DL2 formed to extend in a substantially perpendicular direction relative to the bit line BL are connected together at their adjacent ends into a single wiring. In this manner, writing can be carried out by sending a writing pulse to both digit lines DL1, DL2 from a single power source. The writing pulse continuously propagates through the upper and lower digit lines DL1, DL2. For example, the writing pulse is supplied from the power source (not shown) connected to one end of the digit line DL1 to flow in the digit line DL1. The writing pulse first flows in the digit line DL1 and then flows in the digit line L2 connected to the other end of the digit ling DL1. Writing is carried out in the magnetoresistance effect elements C1, C2 substantially at the same time.

[0133] This is because the propagation speed of the current (electrons) flowing in the digit lines DL1, DL2 is very fast in the order of 10⁸cm/second. Let an example be taken, in which a very short writing pulse as short as 10 nanoseconds is applied. Even in this case, taking the propagation speed of the current into consideration, the spatial size L to which a uniform current magnetic field is applied by means of the writing pulse is L=10 cm/second×10 nanoseconds=1 cm.

[0134] Since the chip area of a memory is approximately 1 cm²at the most and the proportion occupied by the memory area, i.e. array efficiency, is approximately 50%, if the pulse is applied for a very short duration of time as short as 10 nanoseconds, writing can be carried out substantially simultaneously in the upper and lower magnetoresistance effect elements C1, C2 even though the current pulse reciprocates.

[0135] That is, as shown in FIGS. 4A, 4B, 5A and 5B, substantially simultaneous writing has been confirmed to be possible by connecting the digit lines DL1, DL2 on and under the magnetoresistance effect elements C1, C2 to U-turn at one of the memory block.

[0136] FIG. 6 is a plan view schematically showing the reversal direction of magnetization M of a magnetic recording layer of the magnetoresistance effect element C1 interposed between a bit line BL and a digit line DL1. Reversal direction of magnetization is reverted depending upon the direction of the current flowing in the digit lines. In case of the configuration shown in FIGS. 4A, 4B, 5A and 5B, reversal directions of magnetization M are different between the upper and lower magnetoresistance effect elements C1, C2. It is clockwise in one element and the counterclockwise in the other. However, this is immaterial because the asteroidal curve is approximately symmetric in both directions.

[0137] As explained heretofore with reference to FIGS. 4A through 6, when the digit lines DL1 and DL2 on and under the magnetoresistance effect elements C1, C2 are connected together, no increase of the current occurs even in the architecture of the differential amplification type, and no decrease of the capacity of the MRAM memory bit is invited by an increase of the power consumption and/or upsizing of the driver. Thus, high array efficiency is realized.

[0138] The embodiment also enables multi-valued recording when outputs of the upper and lower magnetoresistance effect elements C1, C2 are combined.

[0139] FIGS. 7A and 7B are schematic diagrams showing a multi-valued recording memory cell according to an embodiment of the invention. FIG. 7A is a cross-sectional view taken along a plane perpendicular to the lengthwise direction of the bit line BL, and FIG. 7B is a cross-sectional view taken along a plane parallel to the lengthwise direction of the bit line BL.

[0140] For multi-valued recording, the device is configured to permit independent writing in the upper and lower magnetoresistance effect elements C1, C2, respectively. Then, a difference between their outputs is computed.

[0141] For example, assume that two outputs of the magnetoresistance effect elements C1, C2 are as follows.

[0142] In case the magnetoresistance effect elements C1, C2 are available for independent writing, there are the following four combinations as output differences obtained by deducting outputs of C1 from outputs of C2.

[0143] Therefore, when the outputs A through D of the upper and lower magnetoresistance effect elements C1, C2 are adjusted to appropriate values, those four kinds of output differences have significant differences, respectively, and four-valued information can be recorded and reproduced.

[0144] For the purpose of obtaining different outputs of the upper and lower magnetoresistance effect elements C1, C2 from each other, the specific example of FIGS. 7A and 7B employ different structures for the magnetoresistance effect elements. The upper magnetoresistance effect element C1 has a single ferromagnetic tunneling junction whereas the lower magnetoresistance effect element C2 has double ferromagnetic tunneling junctions. By employing different structures to form the pair of magnetoresistance effect elements from each other, it is possible to obtain different outputs and carry out stable multi-valued recording. Configuration of upper and lower magnetoresistance effect elements to vary their outputs is not limited to that shown in FIGS. 7A and 7B. Otherwise, the magnetoresistance effect elements may be different in multi-layered structure, or one or more of layers forming one of the magnetoresistance elements may be changed in material and/or thickness from those of such layers of the other magnetoresistance effect elements.

[0145] For multi-valued recording, it is required that the upper and lower magnetoresistance effect elements C1, C2 are available for independent recording. Therefore, as shown in FIGS. 7A and 7B, the easy axes of magnetization of the recording layers 52 are preferably parallel to the lengthwise direction of the bit line BL. That is, easy axes of magnetization of the recording layers 52 are oriented perpendicularly to the digit lines DL1, DL2. In this manner, when writing electric currents are supplied independently to the digit lines DL1, DL2, writing occurs independently in the upper and lower magnetoresistance effect elements C1, C2, and multi-valued recording is enabled.

[0146] Also in the architecture for multi-valued recording shown in FIGS. 7A and 7B, since electric currents are supplied to the upper and lower digit lines DL1, DL2, and current flowing in the digit lines is larger than that of ordinary architecture, and this is disadvantageous from the viewpoint of power consumption. Additionally, since a larger quantity of current must be supplied, the area of the driver for supplying the current to the digit lines inevitably increases. This invites the disadvantage that the ratio of the memory area relative to the chip area (array efficiency) decreases.

[0147] To overcome these problems, one of opposite ends of the digit line DL1 and an adjacent end of the digital line DL2, both extending substantially perpendicularly to the bit line BL in the vertical differential MRAM capable of recording multi-valued information, may be configured to selectively connected together as shown in FIGS. 8A through 11C. That is, the digit lines DL1, DL2 are connected together only when the switching element Tr1 is ON.

[0148] Here again, similarly to the reason already explained with reference to FIGS. 4A through 6, the reason why the multi-valued recording is possible lies in that the propagation speed of the current (electrons) flowing in the digit lines DL1, DL2 is very fast in the order of 10⁸cm/second. As explained before, even when a very short pulse as short as 10 nanosecond, for example, is applied, a uniform current magnetic field is formed by the pulse in the space sized approximately 1 cm. This size is large enough to cover the memory area of an ordinary memory chip. Therefore, even when an extremely short writing pulse as short as 10 nanoseconds is used, writing can be carried out simultaneously in the upper and lower magnetoresistance effect elements C1, C2 by connecting the upper and lower digit lines DL1, DL2 together and reciprocating the current pulse.

[0149] In case of multi-valued recording, however, the switching element Tr1 must be appropriately turned on or off, depending upon the writing bit. That is, in accordance with the writing bit information, the upper and lower digit lines DL1, DL2 must be connected or disconnected.

[0150] For example, in case of writing “0” in both of the upper and lower magnetoresistance effect elements C1, C2, the switching element Tr1 is turned on to connect the digit lines DL1, DL2 as shown in FIG. 8A. Then, a writing pulse is applied from a power source connected to one end of the digit line DL1, for example, and it is permitted to flow into the digit line DL2. The writing timing is as shown in FIG. 8A. That is, at substantially the same timing as the application of the writing pulse to the bit line BL, the switching element Tr1 is turned on to let the writing pulse flow into the digit lines DL1, DL2 as well.

[0151] Also when “1” is written in the upper and lower magnetoresistance effect elements C1, C2, respectively, substantially the same operations occur. As shown in FIG. 9A, the switching element Tr1 is turned on to connect the upper and lower digit lines DL1, DL2 together. Then a writing pulse is applied from the power source connected to one end of the digit line DL2, for example, and it is permitted to flow into the digit line DL1 as well. Here again, the writing timing is as shown in FIG. 9C. The switching element Tr1 is turned on substantially at the same timing as the application of the writing pulse to the bit line BL to permit the writing pulse to flow into the digit lines DL1, DL2 as well.

[0152] In contrast, in case of writing “0” in one of the upper and lower magnetoresistance effect elements C1, C2 and “1” in the other, the upper and lower digit lines DL1, DL2 must be disconnected.

[0153] For example, as shown in FIG. 10A, in case of writing “0” in the upper magnetoresistance effect element C1 having a single ferromagnetic tunneling junction and writing “1” in the lower magnetoresistance effect element C2 having double ferromagnetic tunneling junctions, the switching element Tr1 is turned off to disconnect the digit lines DL1, DL2. Then writing pulses are supplied in the same direction from power sources connected to respective ends of the digit lines DL1, DL2.

[0154] The writing timing in this case is as shown in FIG. 10C. The switching element Tr1 is turned off substantially at the same timing as the application of the writing pulses to the bit line BL to permit the writing pulses to flow into the digit lines DL1, DL2, respectively. In this case, however, to supply current pulses from a single power source (not shown) to the upper and lower magnetoresistance effect elements, respectively, the writing timing must be offset as shown in FIG. 10C. That is, after the writing current pulse is first supplied to one of the digit lines DL1, DL2 by connecting the power source thereto, power source is switched to the other digit line to supply the writing pulse thereto.

[0155] When data is written in the upper and lower magnetoresistance effect elements C1, C2, if the data then intended to record is the same as the data already stored, new writing need not be carried out. It is possible to omit the writing when the data intended to write is confirmed to be the same as the data already stored in the magnetoresistance effect element C1 or C2 by previously reading and checking it, for example.

[0156] The switching element Tr1 is held in OFF state at least until the current pulses are actually supplied to the upper and lower digit lines DL1, DL2, respectively.

[0157] In case of writing “1” in the upper magnetoresistance effect element C1 having a single ferromagnetic tunneling junction and writing “0” in the lower magnetoresistance effect element C2 having double ferromagnetic tunneling junctions, the switching element Tr1 is here again turned off as shown in FIG. 11. Then writing pulses in the same direction may be supplied the respective digit lines DL1, DL2 by switching the power source thereto.

[0158] As explained heretofore with reference to FIGS. 8A through 11C, by configuring the upper and lower digit lines DL1, DL2 to be selectively connected and disconnected and the power source to be selectively connected, no increase of the current occurs even in the architecture of the differential amplification type, and no decrease of the capacity of the MRA memory bit is invited by an increase of the power consumption and/or upsizing of the driver.

[0159] Next explained is a specific example of multi-layered configuration of magnetoresistance effect elements usable in a magnetic memory according to an embodiment of the invention.

[0160] FIG. 12 and FIG. 13 are schematic diagrams showing cross-sectional structures of magnetoresistance effect elements having a single ferromagnetic tunneling junction.

[0161] In case of the magnetoresistance effect element shown in FIG. 12, an anti-ferromagnetic layer AF, ferromagnetic layer FM1, tunneling barrier layer TB, ferromagnetic layer FM2, and protective layer PB are stacked in the written order. The ferromagnetic layer FM 1 adjacent to the anti-ferromagnetic layer AF functions as the magnetically pinned layer (pinned layer), and the ferromagnetic layer FM2 overlying the tunneling barrier layer TB functions as the recording layer (free layer).

[0162] In case of the magnetoresistance effect element of FIG. 13, multi-layered films SL each including a ferromagnetic layer FM, nonmagnetic layer NM and ferromagnetic layer FM are formed on and under a tunneling barrier layer TB. Here again, the multi-layered film SL interposed between the anti-ferromagnetic layer AF and the tunneling barrier layer TB functions as the magnetically pinned layer, and the multi-layered film SL overlying the tunneling barrier layer TB functions as the recording layer.

[0163] FIGS. 14 through 16 are schematic diagrams showing cross-sectional structures of magnetoresistance effect elements each having double ferromagnetic tunneling junctions. In these figures, the same or equivalent components as those already explained with reference to FIGS. 12 and 13 are labeled with common reference numerals, and their detailed explanation is omitted.

[0164] In case of the structures shown in FIGS. 14 through 16, each includes two tunneling barrier layers TB, and ferromagnetic layers FM or multi-layered films SL each including a ferromagnetic layer FM and a nonmagnetic layer NM are formed to overlie and underlie the ferromagnetic layer FM. In each of the double-tunneling elements shown here, the ferromagnetic layers FM or multi-layered films adjacent to the top and bottom of the ferromagnetic layer AF function as magnetically pinned layers, and ferromagnetic layers FM or multi-layered films SL interposed between two tunneling barrier layers TB function as recording layers.

[0165] The use of such a double-tunneling structure is advantageous for obtaining large changes of a current relative to the magnetization directions of the recording layers.

[0166] Magnetoresistance effect elements usable in a magnetic memory according to an embodiment of the invention are not limited to those shown in FIGS. 12 through 16. A magnetoresistance effect element having a so-called “spin valve” structure made by stacking a first ferromagnetic layer, nonmagnetic layer and second ferromagnetic layer can be used as well.

[0167] Whichever of these structures is employed as the magnetoresistance effect element, one of the ferromagnetic layers can be used to function as the “magnetically pinned layer (also called “pinned layer”) substantially pinned in magnetization direction, and the other ferromagnetic layer can be used to function as the “magnetic recording layer” variable in magnetization direction with an externally applied magnetic field.

[0168] Additionally, the ferromagnetic layer adjacent to the anti-ferromagnetic layer can be used as a recording layer in case a certain reading system is employed as explained later in greater detail.

[0169] Ferromagnetic materials usable as the magnetically pinned layers in these magnetoresistance effect elements are, for example, Fe (iron), Co (cobalt), Ni (nickel), their alloys, magnetite having large spin polarizability, oxides such as CrO₂, RXMnO_3-y(where R is a rare earth and X is one of Ca (calcium), Ba (barium) and Sr (strontium)), and Heusler alloys such as NiMnSb (nickel manganese antimony) and PtMnSb (platinum manganese antimony).

[0170] The magnetically pinned layer made of such a material preferably has unidirectional anisotropy. Its thickness is preferably in the range from 0.1 nm to 100 nm. This ferromagnetic layer must be thick enough to prevent itself from becoming super-paramagnetic, and it is more preferably not thinner than 0.4 nm.

[0171] An anti-ferromagnetic film is preferably added to the ferromagnetic layer used as the magnetically pinned layer to pin the magnetization. As anti-ferromagnetic films of this type, there are Fe (iron)-Mn (manganese), Pt (platinum)-Mn (manganese), Pt platinum)-Cr (chromium)-Mn (manganese), Ni (nickel)-Mn (manganese), Ir (iridium)-Mn (manganese), NiO (nickel oxide), Fe₂O₃(iron oxide) and the above-mentioned magnetic semiconductors,

[0172] These magnetic materials may be adjusted in magnetic property, or in other physical properties such as crystalline property, mechanical property and chemical property, for example, by addition of one or more nonmagnetic elements such as Ag (silver), Cu (copper), Au (gold), Al (aluminum), Mg (magnesium), Si (silicon), Bi (bismuth), Ta (tantalum), B (boron), C (carbon), O (oxygen), N (nitrogen), Pd (palladium), Pt (platinum), Zr (zirconium), Ir (iridium), W (tungsten), Mo (molybdenum), Nb (niobium) and H (hydrogen), for example.

[0173] On the other hand, a multi-layered film of a ferromagnetic layer and a nonmagnetic layer may be used as the magnetically pinned layer. For example, the three-layered structure of ferromagnetic layer/nonmagnetic layer/ferromagnetic layer as shown in FIG. 13 can be used. In this case, it is desirable that anti-ferromagnetic interaction works between the ferromagnetic layers in opposite sides of the non-magnetic layer.

[0174] More specifically, as a method of pinning the magnetic layer in one direction, it is desirable to use a three-layered film such as Co (Co—Fe)/Ru (ruthenium)/Co (CoFe), Co (Co—Fe)/Ir (iridium)/Co (Co—Fe), Co (Co—Fe)/Os (osmium)/Co (Co—Fe), magnetic semiconductor ferromagnetic layer/magnetic semiconductor nonmagnetic layer/magnetic semiconductor ferromagnetic layer as the magnetically pinned layer, and additionally form an anti-ferromagnetic film adjacent thereto.

[0175] Here again, as the anti-ferromagnetic film, Fe—Mn, Pt—Mn, Pt—Cr—Mn, Ni—Mn, Ir—Mn, NiO, Fe₂O₃, magnetic semiconductor, etc. can be used similarly to those mentioned above. The use of this structure contributes to firmly pinning the magnetization of the magnetically pinned layer, and additionally to decreasing (or adjusting) the stray field from the magnetically pinned layer. Therefore, by changing two ferromagnetic layers of the magnetically pinned layer in thickness, magnetization shift of the magnetic recording layer can be adjusted.

[0176] On the other hand, also as the material of the magnetic recording layer (free layer) similarly to the magnetically pinned layer, it is possible to use Fe (iron), Co (cobalt), Ni (nickel), their alloys, magnetite having large spin polarizability, oxides such as CrO₂, RXMnO_3-y(where R is a rare earth and X is one of Ca (calcium), Ba (barium) and Sr (strontium)), and Heusler alloys such as NiMnSb (nickel manganese antimony) and PtMnSb (platinum manganese antimony).

[0177] The ferromagnetic layer as the magnetic recording layer made of such a material preferably has unidirectional anisotropy in the direction substantially in parallel to the film plane. Its thickness is preferably in the range from 0.1 nm to 100 nm. This ferromagnetic layer must be thick enough to prevent itself from becoming super-paramagnetic, and it is more preferably not thinner than 0.4 nm.

[0178] As the magnetic recording layer, the two-layered structure of soft magnetic layer/ferromagnetic layer or the three-layered structure of ferromagnetic layer/soft magnetic layer/ferromagnetic layer may be used. When using the three-layered structure of ferromagnetic layer/nonmagnetic layer/ferromagnetic layer or the five-layered structure of ferromagnetic layer/nonmagnetic layer/ferromagnetic layer/nonmagnetic layer/ferromagnetic layer and controlling the interaction between the ferromagnetic layers, the favorable effect that the power consumption of the current magnetic field is prevented from increasing even when the cell width of the magnetic recording layer as the memory cell downsizes to a submicron or even smaller size. In case of the five-layered structure, the use of a soft magnetic layer or a ferromagnetic layer interrupted by nonmagnetic elements as the intermediate ferromagnetic layer is more preferable.

[0179] Also in the magnetic recording layer, these magnetic materials may be adjusted in magnetic property, or in other physical properties such as crystalline property, mechanical property and chemical property, for example, by addition of one or more nonmagnetic elements such as Ag (silver), Cu (copper), Au (gold), Al (aluminum), Mg (magnesium), Si (silicon), Bi (bismuth), Ta (tantalum), B (boron), C (carbon), O (oxygen), N (nitrogen), Pd (palladium), Pt (platinum), Zr (zirconium), Ir (iridium), W (tungsten), Mo (molybdenum), Nb (niobium) and H (hydrogen), for example.

[0180] These compounds need not be completely precise in composition from the stoichiometrical viewpoint, but hydrogen, nitrogen or fluorine, for example, may be short or excessive. This insulating layer (dielectric layer) had better be thin enough to permit a tunneling current to flow. Practically, it is preferably controlled not to exceed 10 nm.

[0181] The magnetoresistance effect element having the above-explained configuration can be made on a predetermined substrate by using a usual method for fabricating thin films, such as various kinds of sputtering, vapor deposition, molecular beam epitaxy and CVD, for example. As this substrate, various kinds of substrates are usable, such as Si (silicon), SiO₂(silicon oxide), Al₂O₃(aluminum oxide), spinel, AlN (aluminum nitride), GaAs and GaN, for example.

[0182] Additionally, a layer of Ta (tantalum), Ti (titanium), Pt (platinum), Pd (palladium), Au (gold), Ti (titanium)/Pt (platinum), Ta (tantalum)/Pt (platinum), Ti (titanium)/Pd (palladium), Ta (tantalum)/Pd (palladium), Cu (copper), Al (aluminum), Cu (copper), Ru (ruthenium), Ir (iridium), Os (osmium), or semiconductor base such as GaAs, GaN, ZnO and TiO₂may be formed on the substrate as the base layer or protective layer.

[0183] Heretofore, the multi-layered structure of the magnetoresistance effect element to be used in the magnetic memory according to the embodiment of the invention has been explained.

[0184] Direction of magnetization written in the magnetic recording layers of the magnetoresistance effect elements C1, C2 need not be straight, and it may be curved to have “edge domains” in accordance with the plane geometry of the magnetic recording layers.

[0185] FIGS. 17A through 17F are schematic diagrams exemplifying plane geometries and corresponding directions of magnetization of magnetic recording layers of magnetoresistance effect elements. That is, the magnetic recording layer of the magnetoresistance effect element may have a rectangular shape added with projections at diagonal opposite ends as shown in FIG. 17A, parallelogrammatic shape as shown in FIG. 17B, rhomboidal shape as shown in FIG. 17C, elliptical shape as shown in FIG. 17D, edge-slanted shape as shown in FIG. 17E, an elongated octagon as shown in FIG. 11F, or any of other various shapes. In case of asymmetric shapes as shown in FIGS. 17A and 17B, direction of magnetization is curved due to formation of “edge domains”. Magnetic recording layers of these types may be used in the embodiment of the invention. These asymmetric shapes can be easily made by using an asymmetrically patterned reticle in lithography.

[0186] In case of patterning the magnetic recording layer to any of the shapes shown in FIGS. 17A through 17C, 17E and 17F, corners are practically rounded in most cases. Such shaped with rounded corners are also acceptable. The magnetic recording layer preferably has unidirectional anisotropy with which the direction of magnetization is substantially regulated in a direction along one axis. For this purpose, ratio L/D between the width W and the length L of the magnetic recording layer is preferably larger than 1.2 to easily make the unidirectional anisotropy along the length L.

[0187] Heretofore, the basic structure of the magnetic memory according to the embodiment of the invention and magnetoresistance effect elements used therein have been explained.

[0188] Next explained is the cell structure of the magnetic memory according to the embodiment of the invention with reference to specific examples.

[0189] FIG. 18 is a diagram showing an architecture according to an embodiment of the invention when using CMOS.

[0190] In case CMOS (complementary metal-oxide-semiconductor) is used as the switching element, for the reading purpose, the lower selection transistor CMOS is turned ON to flow a sense current to the respective magnetoresistance effect elements C1, C2 via the bit line BL, extract it from the read wiring M1, M2 and effect differential operation with the amplifier SA.

[0191] Writing in the magnetoresistance effect elements C1, C2 is carried out by flowing a writing current to the bit line BL and the digit lines DL1, DL2 that cross orthogonally. Then, as already explained in conjunction with FIGS. 3A to 4, by changing the easy axes of magnetization of the recording layers 52 of the magnetoresistance effect elements C1, C2, a memory of a differential operation type or a multi-valued memory type can be made.

[0192] To realize a still giant capacity memory, some memory arrays are preferably multi-layered by using an architecture available for this purpose.

[0193] FIG. 19 is a schematic diagram the second specific example of the architecture usable in an embodiment of the invention. This figure shows a cross-sectional structure of a memory array. In this architecture, magnetoresistance effect elements are connected in parallel to the read/write bit line BL. To the other end of each magnetoresistance effect element C, the read/write word line W is connected via a diode D.

[0194] For reading, a bit line BL and a digit line D connected to the target magnetoresistance effect element C are selected by a selection transistors STB and STw, and a current is detected by the sense amplifier SA.

[0195] For writing, a bit line BL and a digit line D connected to the target magnetoresistance effect element C are selected by a selection transistors STB and STw, and a writing current is flown. Then magnetic fields are generated in the bit line BL and the digit line DL, respectively, and their composite writing magnetic field directs the magnetization in the magnetic recording layer of the magnetoresistance effect element to a predetermined orientation. Thus the writing takes place.

[0196] The diode functions to interrupt a bypass current that flows via other magnetoresistance effect elements in a matrix array upon reading or writing.

[0197] FIG. 20 is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using the architecture of FIG. 19.

[0198] FIGS. 21A and 21B are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 19.

[0199] For simplification, FIGS. 20 through FIG. 21B illustrates only a bit line BL, magnetoresistance effect elements C, diodes D and digit line DL and omits the other components from illustration. FIGS. 21A and 21B illustrate an example configured to change output voltages from each pair of magnetoresistance effect elements by constructing one of the magnetoresistance effect elements to have a single ferromagnetic tunneling junction and the other to have double ferromagnetic tunneling junctions. These memory cells are operative under the same operation principle as that already explained in conjunction with FIGS. 1 through 19.

[0200] The wiring (digit lines DL and bit line BL) is preferably made of Cu (copper), for example, and coated by an overcoat layer of a magnetic material as explained later. Usable magnetic materials for the overcoat layer are magnetic amorphous materials such as FeO_x(iron oxide), CoZnNb (cobalt zinc niobate), and magnetic alloys such as CoFeNi (cobalt iron nickel), NiFe (nickel iron) and Permalloy (trademark).

[0201] FIGS. 21A illustrates the example configuring the upper magnetoresistance effect element C1 to have a single tunneling junction and the lower magnetoresistance effect element C2 to have double tunneling junctions to change their outputs and thereby facilitate multi-valued recording. Instead, however, an element having a single tunneling junction as shown in FIG. 21B may be used as the lower magnetoresistance effect element C2. In this case, material or thickness, for example, of a layer may be changed from that of the upper magnetoresistance effect element C1, to change its output from that of the magnetoresistance effect element C1. This makes multi-valued recording easy as well.

[0202] Next explained is the third specific example of architecture usable in the magnetic memory according to the embodiment.

[0203] FIG. 22 is a schematic diagram showing the third specific example of the architecture available for stacking memory arrays. That is, this figure shows a cross-sectional structure of a memory array.

[0204] In this architecture, a plurality of magnetoresistance effect elements C are connected in parallel between the read/write bit line BLw and the read bit line BLr in a “ladder” configuration. Additionally, the write word lines W extend across the bit lines.

[0205] Writing in the magnetoresistance effect element can be carried out by a composite magnetic field of a magnetic field generated in the read/write bit line BLw by flowing a write current and a magnetic field generated in the write digit line DL by flowing a write current, which acts on the magnetic recording layer of the magnetoresistance effect element.

[0206] For reading, a voltage is applied between the bit lines BLw and BLr. Then, currents flow in all magnetoresistance effect elements connected in parallel between them. While the sense amplifier SA detects the sum of these current, a write current is applied to the word line W close to the target magnetoresistance effect element. Thus the direction of magnetization in the magnetic recording layer of the target magnetoresistance effect element is changed to a predetermined direction. By detecting a change of the current occurring at this time, reading from the target magnetoresistance effect element can be attained.

[0207] That is, if the magnetization direction in the magnetic recording layer before writing is the same as the magnetization direction after writing, there is no change in the current detected by the sense amplifier SA. However, if the magnetization direction of the magnetic recording layer changes by writing, the current detected by the sense amplifier SA changes due to a magnetoresistance effect. In this manner, magnetization direction of the magnetic recording layer before writing, which is just the storage data, can be read out.

[0208] In contrast, in case the magnetoresistance effect element has the structure of magnetic layer/insulating layer (nonmagnetic layer)/magnetic recording layer, so-called “nondestructive reading” is possible. In case of using a magnetoresistance effect element of this type, direction of magnetization of the magnetic recording layer can be read out by recording the magnetization direction beforehand and appropriately changing the magnetization direction of the magnetic recording layer upon reading and thereby comparing sense currents. In this case, however, the element must be designed such that the magnetization reversal magnetic field of the magnetically free layer is larger than the magnetization reversal magnetic field of the magnetic recording layer.

[0209] FIG. 23A is a cross-sectional schematic diagram showing a memory cell of a differential operation type made by using the architecture of FIG. 22. FIG. 22B is a schematic diagram showing multi-layered structures of the magnetoresistance effect elements C1, C2. In a differential operation model, it is possible to the same output by designing the structures of the upper and lower magnetoresistance effect elements C1, C2 in this manner.

[0210] FIGS. 24A is a cross-sectional schematic diagram showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 22. Also in FIGS. 23A through 24C, only the bit lines BL, magnetoresistance effect elements C and digit lines DL are shown, and the other components are omitted from illustration for simplicity. These memory cells are operative under the same operation principle as that already explained in conjunction with FIGS. 1 through 19.

[0211] Also in the memory cell shown in FIG. 24A, for the purpose of ensuring the pair of magnetoresistance effect elements C1, C2 to be different in output voltage, the magnetoresistance effect element C1 may have a single ferromagnetic tunneling junction and the other magnetoresistance effect element C2 may have double ferromagnetic tunneling junctions as shown in FIG. 24B. Alternatively, as shown in FIG. 24C, the lower magnetoresistance effect element C2 may have a single tunneling junction provided it is changed in material or thickness of at least one layer from that of the upper element C1 to supply an output different from that of C1.

[0212] Here again, the wiring (digit lines DL and bit line BL) is preferably made of Cu (copper), for example, and coated by an overcoat layer of a magnetic material as explained later. Usable magnetic materials for the overcoat layer are magnetic amorphous materials such as FeO_x(iron oxide), CoZnNb (cobalt zinc niobate), and magnetic alloys such as CoFeNi (cobalt iron nickel), NiFe (nickel iron) and Permalloy (trademark).

[0213] Next explained is the third specific example of architecture usable in the magnetic memory according to the embodiment.

[0214] FIG. 25 is a schematic diagram showing the fourth specific example of the architecture available for stacking memory arrays. That is, this figure shows a cross-sectional structure of a memory array.

[0215] In this architecture, a plurality of magnetoresistance effect elements are connected in parallel to the read/write bit lines BL, and read bit lines BLr are connected to the other ends of the magnetoresistance effect elements in a matrix arrangement.

[0216] Additionally, write digit lines DL extend closely to the read bit lines BLr.

[0217] Writing in a magnetoresistance effect element occurs when a composite magnetic field of a magnetic field generated in the read/write bit line BLw by flowing a write current and a magnetic field generated in the write digit line DL by flowing a write current acts on the magnetic recording layer of the magnetoresistance effect element.

[0218] For reading, bit lines BLw and BLr are selected by a selection transistor ST, and a sense current is flown to the target magnetoresistance effect element. Then the sense amplifier detects it.

[0219] FIGS. 26A and 26B are cross-sectional schematic diagrams showing a memory cell of a differential operation type made by using the architecture of FIG. 25.

[0220] FIGS. 27A through 27C are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 25. Also in FIGS. 26A through 27C, only the bit lines BL, magnetoresistance effect elements C and digit lines DL are shown, and the other components are omitted from illustration for simplicity. These memory cells are operative under the same operation principle as that already explained in conjunction with FIGS. 1 through 19.

[0221] Also in the memory cell shown in FIG. 27A, for the purpose of obtaining different output voltages from the pair of magnetoresistance effect elements C1, C2, a single ferromagnetic junction is formed in the magnetoresistance effect element C1 and double ferromagnetic tunneling junctions are formed in the other magnetoresistance effect element C2 as shown in FIG. 27B. Alternatively, as shown in FIG. 27C, the lower magnetoresistance effect element C2 may have a single tunneling junction provided it is changed in material or thickness of at least one layer from that of the upper element C1 to supply an output different from that of C1.

[0222] The foregoing explanation explained in conjunction with FIGS. 19 through 24C about the material of the wiring (digit lines DL and bit line BL) and the overcoat around them is applicable here again.

[0223] Next explained is the fifth specific example of architecture usable in the magnetic memory according to the embodiment.

[0224] FIG. 28 is a schematic diagram the fifth specific example of the architecture usable in an embodiment of the invention. This figure shows a cross-sectional structure of a memory array. This is different from other specific examples in that the read bit line BLr is connected to the magnetoresistance effect elements and the write digit line lie immediately under the magnetoresistance effect elements. In this configuration, the magnetoresistance effect elements and the digit lines can be located closer than the configuration of FIG. 25. As a result, the write magnetic field from the digit line can be invited to act on the magnetoresistance effect element more effectively.

[0225] FIGS. 29 through 31 are cross-sectional schematic diagrams showing memory cells of differential operation types made by using ferromagnetic single-tunneling elements as the magnetoresistance effect elements C1, C2 in the architecture of FIG. 28.

[0226] FIGS. 32A and 32B are cross-sectional schematic diagrams showing a memory cell of a multi-valued recording type made by using the architecture of FIG. 28. Also in FIGS. 29, 32A and 32B, only the bit lines BL, magnetoresistance effect elements C and digit lines DL are shown, and the other components are omitted from illustration for simplicity.

[0227] Also in the memory cell shown in FIGS. 32A and 32B for the purpose of obtaining different output voltages from the pair of magnetoresistance effect elements C1, C2, a single ferromagnetic junction is formed in the magnetoresistance effect element C1 and double ferromagnetic tunneling junctions are formed in the other magnetoresistance effect element C2. These memory cells are operative under the same operation principle as that already explained in conjunction with FIGS. 1 through 19.

[0228] The memory cell shown in FIG. 29 uses single-tunneling elements are used as the magnetoresistance effect elements C1, C2.

[0229] The memory cell shown in FIG. 30 uses double-tunneling elements are used as the magnetoresistance effect elements C1, C2.

[0230] In the memory cell shown in FIG. 31, both magnetoresistance effect elements C1, C2 have a single ferromagnetic tunneling junction, and the recording layer has a three-layered structure stacking a ferromagnetic layer FM, nonmagnetic layer NM and ferromagnetic layer FM.

[0231] In the memory cell shown in FIGS. 32A and 32B, for the purpose of facilitating multi-valued recording, the upper magnetoresistance effect element C1 has a single tunneling junction and the lower magnetoresistance effect element C2 has double tunneling junction such that these elements issue different outputs. However, the magnetoresistance effect element C2 may be modified to a single-tunneling structure as shown in FIG. 32B. In this case, by changing the material or thickness of at least one layer from that of the magnetoresistance effect element C1, a different output from that of the magnetoresistance effect element C1 can be obtained. This configuration also facilitates multi-valued recording.

[0232] Next explained is the overcoat layer SM usable to coat the wiring in the memory cell according to the embodiment.

[0233] FIGS. 33A through 35B are schematic diagrams exemplifying memory cells including an overcoat layer SM. FIGS. 33A, 34A and 35A are cross-sectional views taken along planes perpendicular to the lengthwise directions of the bit lines BL whereas FIGS. 33B, 34B and 35B are cross-sectional views taken along planes parallel to the lengthwise directions.

[0234] FIGS. 33A and 33B show a model corresponding to the memory cell shown in FIG. 1 but including the overcoat layer SM. The overcoat layer SM of a magnetic material surrounds the outer periphery of the wiring (digit lines DL and bit lines BL). That is, part of the outer surface of the wiring (digit lines DL and bit lines BL) of copper (Cu) or the like, which need not exert a magnetic field, is covered by the overcoat layer SM. This overcoat layer SM prevents writing cross talk by writing magnetic fields radiated from the digit lines DL and bit lines BL, that is, useless, undesirable writing to other magnetoresistance effect elements adjacent in the lateral and film-stacking directions.

[0235] Therefore, the overcoat layer SM functions to prevent leakage of the magnetic field, and its appropriate materials are amorphous materials such as FeO_x(iron oxide), CoZnNb (cobalt zinc niobate), and magnetic alloys such as CoFeNi (cobalt iron nickel), NiFe (nickel iron) and Permalloy (trademark).

[0236] As shown in FIGS. 34A and 34B, the overcoat layer SM may be extended to side surfaces of the magnetoresistance effect elements C1, C2. In this case, the overcoat layer SM effectively prevents radiation of the writing magnetic field from the write digit lines DL1, DL2 and can efficiently concentrate it to the recording layers of the magnetoresistance effect elements C1, C2. In this sense, the overcoat layer SM made of a magnetic metal functions as a so-called “magnetic yoke” as well. Therefore, if the overcoat layer SM is extended closely to the recording layers of the magnetoresistance effect elements C1, C2, it is possible to concentrate the writing current magnetic field to the recording layers via the overcoat layer SM and thereby enhance the writing efficiency more.

[0237] When the overcoat layer is extended as shown in FIGS. 34A and 34B, the extended portion need not be continuous. It is sufficient that part of the overcoat layer SM covering the digit lines D1, D2 is in magnetic coupling with part of the overcoat layer SM located closely to the magnetoresistance effect elements C1, C2, and spaces or other materials may exist between those parts.

[0238] FIGS. 33A and 33B show a model corresponding to the memory cell shown in FIG. 29 but including the overcoat layer SM. The overcoat layer SM of a magnetic material surrounds the outer periphery of the wiring (digit lines DL and bit lines BL). This overcoat layer SM prevents writing cross talk by writing magnetic fields radiated from the digit lines DL and bit lines BL, that is, useless and undesirable writing to other magnetoresistance effect elements adjacent in the lateral and film-stacking directions.

[0239] Also in this model, the overcoat layer SM may be extended to side surfaces of the magnetoresistance effect elements C1, C2 to effectively prevent radiation of the writing magnetic field and function as a magnetic yoke to concentrate the magnetic field to the recording layers.

[0240] FIG. 36 is a schematic diagram exemplifying a cross-sectional structure of a magnetic memory made by stacking memory cells of the architecture of the differential operation type shown in FIG. 29. By stacking matrix-type differentially operative memory cells in this manner, a highly integrated large-capacity memory can be realized. Not limited to the model shown in FIG. 29, this multi-layered structure can be similarly employed to other architectures of differential operation types explained heretofore.

[0241] FIGS. 37A through 37C are schematic diagrams exemplifying a cross-sectional structure of a magnetic memory made by stacking memory cells of the architecture of the multi-valued recording type shown in FIG. 24. Also in a multi-valued recording model, by stacking memory cells in a matrix arrangement, a highly integrated large-capacity memory can be realized. Not limited to the model shown in FIG. 24, this multi-layered structure can be similarly employed to other architectures of differential operation types explained heretofore.

[0242] Also in the memory cell shown in FIG. 37A, for the purpose of obtaining different output voltages from the pair of magnetoresistance effect elements C1, C2, a single ferromagnetic junction is formed in the magnetoresistance effect element C1 and double ferromagnetic tunneling junctions are formed in the other magnetoresistance effect element C2 as shown in FIG. 37B. Alternatively, the lower magnetoresistance effect element C2 may have a single-tunneling structure similarly to the upper magnetoresistance effect element C1, and may be changed in material or thickness of at least one layer from that of the upper element C1 to issue an output different from that of the upper element C1.

[0243] In some embodiments of the invention, by forming the pair of magnetoresistance effect elements C1, C2 in combination for differential operation or multi-valued recording on and under the bit line BL, fluctuation of the wiring path between the upper and lower magnetoresistance effect elements can be prevented. Also by specially designing the wiring structure of read wirings M1, M2 and others, the wiring environments including the path length and parasitic capacitance can be uniformed.

[0244] FIG. 38 is a schematic diagram showing a memory cross-sectional structure capable of uniforming the wiring environments of read wirings M1 and M2. The magnetic memory is made by integrating a plurality of memory cells in a matrix arrangement. In this model, these memory cells are divided into a plurality memory blocks MB, and the read wirings M1, M2 are formed to cross between these memory blocks MB. That is, the read wirings M1, M2 are formed to revert the upper and lower positional relation for every memory block.

[0245] The term “memory block” used here means a group of a predetermined number of adjacent memory cells, such as 256 memory cells for example, and a plurality of such memory blocks compose the magnetic memory. However, the number of memory cells belonging to a single memory block need not be equal in all memory blocks.

[0246] The configuration shown in FIG. 38 enables substantial equalization of the wiring environments such as wiring length and parasitic capacity between read wirings M1 and M2. That is, the read wirings M1, M2 can be equalized in deterioration of the signal level, delay of the transmission speed, and so on. As a result, the it is possible to equalize the pair of magnetoresistance effect elements on and under the bit line BL in deterioration of the signal level and delay of the read signal read out from them, and thereby to stably execute differential operation or multi-valued recording.

[0247] The use of the structure for uniforming the wiring environments shown in FIG. 38 is not limited to the read wirings M1, M2. It is similarly usable to bit lines and/or word lines, depending on the memory structure used, and the same effect will be obtained.

[0248] Embodiments of the invention will be explained below in greater detail with reference to Examples.

[0249] As the first Example of the invention, a memory cell was prepared by stacking two layers of memory cells, based on a memory array of a simple matrix structure as shown in FIGS. 33A through 33C and aligning 3×3 TMR cells and vertically stacking two memory arrays. In this Example, each upper magnetoresistance effect element C1 had a single tunneling junction whereas each lower magnetoresistance effect element C2 had double tunneling junctions.

[0250] The structure of the magnetic memory is explained below following its manufacturing procedures.

[0251] On a substrate, not shown, a 1 μm thick wiring layer of copper (Cu) was formed by damascening as the lower-layer wiring M2 and the digit line DL2. Thereafter, an insulating film was formed by CVD (chemical vapor deposition) and a via was made by RIE (reactive ion etching). Then the surface was smoothes by CMP (chemical mechanical polishing).

[0252] After that, a multi-layered film of the TMR element C2 having double ferromagnetic tunneling junctions was formed by sputtering. Materials and thicknesses of respective layers were, in the order from the bottom, Ta (30 nm)/Ru (3 nm)/Ir—Mn (8 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm)/AlO_x(1 nm)/COFeNi (2 nm)/Cu (1.5 nm)/CoFeNi (2 nm)/AlO_x(1 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (9 nm)/Ru (30 nm).

[0253] Subsequently, using the uppermost Ru (ruthenium) layer as a hard mask, the multi-layered film was etched to the depth reaching the lower Ru/Ta wiring layer MX2 by RIE using a chlorine-based etching gas. Thus an isolated pattern of the TMR element C2 was made out.

[0254] Thereafter, by selective etching to the depth of the Ru/Ta wiring MX2 by RIE, the lower-layer connection wiring MX2 was made out.

[0255] After that, SiO_xwas deposited as the insulator by the low-temperature TEOS (tetra ethyl ortho silicate) method and smoothed by CMP. Then the bit line BL was formed by depositing and patterning a film for it.

[0256] After that, a multi-layered film of the TMR element C1 having a single ferromagnetic tunneling junction was formed by sputtering. Materials and thicknesses of respective layers were, in the order from the bottom, Ta (5 nm)/CoFeNi (2 nm)/Cu (1.5 nm)/CoFeNi (2 nm)/AlO_x(1 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (3 nm)/IrMn (8 nm)/Ta (9 nm)/Ru (30 nm).

[0257] In the same manner as explained above, the TMR element C1 was formed and smoothed. Then the connection wiring MX1 was formed and patterned.

[0258] After that, a via was formed in the same manner, and copper (Cu) wirings DL1, M1 were formed by plating.

[0259] Subsequently, the substrate was introduced into an annealing furnace capable of applying a magnetic field. There, unidirectional anisotropy was given to the magnetic recording layers 52 of the TMR elements C1, C2, and unidirectional anisotropy was given to the magnetically pinned layers 56. For a memory of a differential operation type, the unidirectional anisotropy was given in parallel to the lengthwise direction of the digit line DL. For a memory of a multi-valued recording type, the unidirectional anisotropy is given in parallel to the lengthwise direction of the bit line BL.

[0260] With the magnetic memory according to an embodiment of the invention prepared as explained above, an experiment was carried out to measure signal outputs, differential operation and effectiveness of multi-valued operation.

[0261] FIG. 39 is a table showing measured values of output voltages of magnetoresistance effect elements C1, C2 obtained in the first embodiment of the invention. More specifically, output voltages V_APin the anti-parallel state and output voltages V_Pin the parallel state of the TMR elements C1, C2 are shown. It is appreciated also from this results that the TMR element C2 having double junctions exhibits a larger output difference between the anti-parallel state and the parallel state.

[0262] FIGS. 40A and 40B are graph diagrams showing a result of differential operation in the memory cell according to this Example. While a predetermined current is supplied to the digit lines DL1, DL2, a pulsating write current is supplied to the bit line BL as shown in FIG. 40A. In this manner, it is possible to carry out writing in opposite directions simultaneously in the recording layers 52 of the TMR elements C1, C2 and to record information corresponding to “1” of two-valued information.

[0263] After that, by supplying write current pulses in opposite directions to the bit line BL, writing for magnetizing the recording layers of the TMR elements C1, C2 in opposite directions. In this manner, information corresponding to “0” of the two-valued information can be recorded.

[0264] The output difference between “1” and “0” obtained in this manner reaches 250 mV in the differential operation mode. This value is equal to the value obtained by integration of 170 mV as the output difference (Va−Vb) upon writing in the TMR element C2 alone and 80 mV as the output difference (Vc−Vd) upon writing in the TMR element C1 alone.

[0265] That is, differential operation increases the output difference of two-valued information and enables recording and reproduction with a high S/N ratio. Additionally, according to the embodiment of the invention, by closely stacking the magnetoresistance effect elements C1, C2 on and under the common bit line BL, it is possible to substantially equalize the wiring environments of these elements C1, C2 and thereby remove the problems of offsets of write magnetic fields and read-out values upon differential operation.

[0266] Furthermore, this placement of the magnetoresistance effect elements C1, C2 on and under the common bit line BL contributes to downsizing and simplifying the magnetic memory in structure, and thereby makes higher integration easy.

[0267] FIGS. 41A and 41B are graph diagrams showing a result of multi-valued recording operation. In case of multi-valued recording operation, by adequately supplying write current pulses to the digit lines DL1, DL2 while supplying a current to the bit line BL, writing is carried out appropriately in the upper and lower magnetoresistance effect elements C1, C2.

[0268] Output signals obtained by differential operation of the magnetoresistance effect elements C1, C2 in response to the write pulses shown in FIG. 41A, that is, by taking a difference between their outputs, are as shown in FIG. 41B.

[0269] When both of the upper and lower magnetoresistance effect elements C1, C2 are driven to anti-parallel states, the difference of their outputs is Va−Vd, namely, 160 mV. This is determined as the “0” level.

[0270] When the magnetoresistance effect element C2 is driven to the anti-parallel state and the magnetoresistance effect element C1 is driven to the parallel state, their output difference is Va−Vc, namely 80 mV. This is determined as “1” level.

[0271] When the magnetoresistance effect element C2 is driven to the parallel state and the magnetoresistance effect element C1 is driven to the anti-parallel state, their output difference is Vb−Vb, namely −10 mV. This is determined as “2” level.

[0272] When both magnetoresistance effect elements C2, C1 are driven to the parallel state, their output difference is Vb−Vc, namely −90 mV. This is determined as “3” level.

[0273] As such, four-valued data “0” to “3” can be set in intervals of 80 to 90 mV, and it enhances the resolution among different data. Thus the four-valued information can be recorded and reproduced reliably and easily.

[0274] Additionally, according to the embodiment of the invention, by closely stacking the magnetoresistance effect elements C1, C2 on and under the common bit line BL, it is possible to substantially equalize the wiring environments of these elements C1, C2 and thereby remove the problems of offsets of write magnetic fields and read-out values upon multi-valued recording operation.

[0275] Furthermore, this placement of the magnetoresistance effect elements C1, C2 on and under the common bit line BL contributes to downsizing and simplifying the magnetic memory in structure, and thereby makes higher integration easy.

[0276] As the second Example of the invention, a memory cell was prepared by stacking two layers of memory cells, based on a memory array of a “ladder type” structure as shown in FIGS. 24A through 24C and aligning 3×3 TMR cells and vertically aligning two memory arrays. Here again, each upper magnetoresistance effect element C1 had a single tunneling junction whereas each lower magnetoresistance effect element C2 had double tunneling junctions.

[0277] The structure of the magnetic memory is explained below following its manufacturing procedures.

[0278] On a substrate, not shown, a 1 μm thick wiring layer of copper (Cu) was formed by damascening as the lower-layer wiring M2 and the digit line DL2. Thereafter, an insulating film was formed by CVD and smoothed by CMP. Additionally, as the lower-layer bit line BL1, a 1 μm thick Cu/Ta wiring layer was formed by sputtering, and the multi-layered film of the TMR element C2 having double ferromagnetic tunneling junctions was formed by sputtering.

[0279] Materials and thicknesses of respective layers were, in the order from the bottom, Ta (2 nm)/Ru (3 nm)/Pt—Mn (12 nm)/CoFe (2.5 nm)/Ru (1 nm)/CoFe (3 nm)/AlO_x(1 nm)/CoFeNi (1.8 nm)/Ru (1.5 nm)/CoFeNi (1.8 nm) AlO_x(1 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (2.5 nm)/IrMn (9 nm)/Ta (9 nm)/Ru (30 nm).

[0280] Subsequently, using the uppermost Ru (ruthenium) layer as a hard mask, the multi-layered film was etched to the depth reaching the lower Ru/Ta/Cu wiring layer BL1 by RIE using a chlorine-based etching gas. Thus an isolated pattern of the TMR element C2 was made out.

[0281] Thereafter, by selective etching to the depth of the Ru/TaCu wiring layer BL1 by RIE, the lower-layer bit line BL1 was made out.

[0282] After that, SiO_xwas deposited as the insulator by the low-temperature TEOS method and smoothed by CMP. Then the bit line BL2 was formed by depositing and patterning a film for it.

[0283] After that, a multi-layered film of the TMR element C1 having a single ferromagnetic tunneling junction was formed by sputtering. Materials and thicknesses of respective layers were, in the order from the bottom, Ta (10 nm)/CoFeNi (2 nm)/Ru (1.5 nm)/CoFeNi (2 nm)/AlO_x(1 nm)/CoFe (3 nm)/Ru (1 nm)/CoFe (2.2 nm)/IrMn (8 nm)/Ta (9 nm)/Ru (30 nm).

[0284] In the same manner as that of the TMR element C2, the TMR element C1 was formed and smoothed. Then the bit line BL3 was formed and patterned.

[0285] From the next step on, this Example was prepared by substantially the same process as that already explained in conjunction with the first Example. So, its explanation is not repeated here.

[0286] Subsequently, the substrate was introduced into an annealing furnace capable of applying a magnetic field. There, unidirectional anisotropy was given to the magnetic recording layers 52 of the TMR elements C1, C2, and unidirectional anisotropy was given to the magnetically pinned layers 56. For a memory of a differential operation type, the unidirectional anisotropy was given in parallel to the lengthwise direction of the digit line DL. For a memory of a multi-valued recording type, the unidirectional anisotropy is given in parallel to the lengthwise direction of the bit line BL.

[0287] With the magnetic memory according to an embodiment of the invention prepared as explained above, an experiment was carried out to measure signal outputs, differential operation and effectiveness of multi-valued operation.

[0288] FIG. 42 is a table showing measured values of output voltages of magnetoresistance effect elements C1, C2 obtained in the first embodiment of the invention. More specifically, output voltages V_APin the anti-parallel state and output voltages V_Pin the parallel state of the TMR elements C1, C2 are shown. It is appreciated also from this results that the TMR element C2 having double junctions exhibits a larger output difference between the anti-parallel state and the parallel state.

[0289] FIGS. 43A and 43B are graph diagrams showing a result of differential operation in the memory cell according to this Example. While a predetermined current is supplied to the digit lines DL1, DL2, a pulsating write current is supplied to the bit line BL as shown in FIG. 40A. In this manner, it is possible to carry out writing in opposite directions simultaneously in the recording layers 52 of the TMR elements C1, C2 and to record information corresponding to “1” of two-valued information.

[0290] After that, by supplying write current pulses in opposite directions to the bit line BL, writing for magnetizing the recording layers of the TMR elements C1, C2 in opposite directions. In this manner, information corresponding to “0” of the two-valued information can be recorded.

[0291] The output difference between “1” and “0” obtained in this manner reaches 280 mV in the differential operation mode. This value is equal to the value obtained by integration of 185 mV as the output difference (Va−Vb) upon writing in the TMR element C2 alone and 95 mV as the output difference (Vc−Vd) upon writing in the TMR element C1 alone.

[0292] That is, differential operation here again increases the output difference of two-valued information and enables recording and reproduction with a high S/N ratio. Additionally, according to the embodiment of the invention, by closely stacking the magnetoresistance effect elements C1, C2 on and under the common bit line BL, it is possible to substantially equalize the wiring environments of these elements C1, C2 and thereby remove the problems of offsets of write magnetic fields and read-out values upon differential operation.

[0293] Furthermore, this placement of the magnetoresistance effect elements C1, C2 on and under the common bit line BL contributes to downsizing and simplifying the magnetic memory in structure, and thereby makes higher integration easy.

[0294] FIGS. 44A and 44B are graph diagrams showing a result of multi-valued recording operation. In case of multi-valued recording operation, by adequately supplying write current pulses to the digit lines DL1, DL2 while supplying a current to the bit line BL, writing is carried out appropriately in the upper and lower magnetoresistance effect elements C1, C2.

[0295] Output signals obtained by differential operation of the magnetoresistance effect elements C1, C2 in response to the write pulses shown in FIG. 44A, that is, by taking a difference between their outputs, are as shown in FIG. 44B.

[0296] When both of the upper and lower magnetoresistance effect elements C1, C2 are driven to anti-parallel states, the difference of their outputs is Va−Vd, namely, 187.5 mV. This is determined as the “0” level.

[0297] When the magnetoresistance effect element C2 is driven to the anti-parallel state and the magnetoresistance effect element C1 is driven to the parallel state, their output difference is Va−Vc, namely 92.5 mV. This is determined as “1” level.

[0298] When the magnetoresistance effect element C2 is driven to the parallel state and the magnetoresistance effect element C1 is driven to the anti-parallel state, their output difference is Vb−Vb, namely −2.5 mV. This is determined as “2” level.

[0299] When both magnetoresistance effect elements C2, C1 are driven to the parallel state, their output difference is Vb−Vc, namely −92.5 mV. This is determined as “3” level.

[0300] As such, four-valued data “0” to “3” can be set in intervals of 90 to 95 mV, and it enhances the resolution among different data. Thus the four-valued information can be recorded and reproduced reliably and easily.

[0301] Additionally, according to the embodiment of the invention, by closely stacking the magnetoresistance effect elements C1, C2 on and under the common bit line BL, it is possible to substantially equalize the wiring environments of these elements C1, C2 and thereby remove the problems of offsets of write magnetic fields and read-out values upon multi-valued recording operation.

[0302] Furthermore, this placement of the magnetoresistance effect elements C1, C2 on and under the common bit line BL contributes to downsizing and simplifying the magnetic memory in structure, and thereby makes higher integration easy.

[0303] As the third Example of the invention, the whole configuration of a magnetic memory having the wiring structure shown in FIGS. 4 to 5B is next explained below.

[0304] FIG. 45 is a conceptual diagram exemplifying the whole structure of the magnetic memory according to the third Example of the invention. As already explained with reference to FIGS. 4 through 6, in some embodiments of the invention, write pulses can be supplied from a single power source by connecting corresponding ends of the digit lines DL1, DL2 together, which extend above and below a pair of differentially operated magnetoresistance effect elements C1, C2.

[0305] As shown in FIG. 45, the magnetic memory having the wiring structure of this type includes drivers for supplying a current to the bit line BL and sinkers for absorbing a current from the bit line BL, which are located at opposite ends of the memory array, i.e. at its opposite ends in the extending direction of the bit line BL.

[0306] In the instant embodiment of the invention, since currents in both forward and backward directions are supplied to the bit line BL, drivers 210, 230 are located at opposite ends of the memory array 110. Similarly, sinkers 220, 240 are located at opposite ends of the memory array 110.

[0307] The current supplied from the driver 210 to the bit line BL is absorbed by the sinker 240. A current supplied from the driver 230 to the bit line BL is absorbed by the sinker 220.

[0308] In the extending direction of the digit lines DL1, DL2, a driver 310 and a sinker 320 are provided at only one end of the memory array 110. This is because the upper and lower digit lines DL1, DL2 are connected together at one end of their extension to form a single continuous wiring path as explained in conjunction with FIGS. 4 through 6. Therefore, a current supplied to one of the digit lines DL1, DL2 from the driver 310 turns back at their connected end at the other end of the memory array 110 and flows into the other of the digit lines DL1, DL2, and it is thereafter absorbed by the sinker 320.

[0309] According to this Example, a single driver 310 and a single sinker 320 are sufficient for supplying a current to the pair of upper and lower digit lines DL1, DL2. Therefore, drivers and sinkers need not be increased, and the ratio of the memory area, i.e. array efficiency, can be enhanced.

[0310] As the fourth Example of the invention, the whole configuration of a magnetic memory having the wiring structure shown in FIGS. 8A to 11C is next explained below.

[0311] FIG. 46 is a conceptual diagram exemplifying the whole structure of the magnetic memory according to the fourth Example of the invention. As already explained with reference to FIGS. 8A through 11C, in some embodiments of the invention, write pulses can be supplied from a single power source by selectively connecting corresponding ends of the digit lines DL1, DL2 together, which extend above and below a pair of differentially operated magnetoresistance effect elements C1, C2, by means of a switching element Tr1 positioned at one end of the extension of the digit lines DL1, DL2.

[0312] As shown in FIG. 46, the magnetic memory having the wiring structure of this type includes drivers for supplying a current to the bit line BL and sinkers for absorbing a current from the bit line BL, which are located at opposite ends of the memory array, i.e. at its opposite ends in the extending direction of the bit line BL.

[0313] Its reason lies in the need of supplying currents in both positive and negative directions to the bit line BL as explained in conjunction with FIG. 45, and memory drivers 210, 230 are provided at opposite ends of the memory array 110. Similarly, sinkers 220, 240 are provided at opposite sides of the memory array.

[0314] In the extending direction of the digit lines DL1, DL2, drivers 310 and sinkers 320 are provided at opposite ends of the memory array 110 via switching portions 400, 410. This is because the current supplied to the digit lines must be changed in direction depending on the recording mode.

[0315] More specifically, as already explained in conjunction with FIGS. 8A through 9C, it is necessary to turn on the switching element Tr1 located at the other end of the digit lines to connect them together, then supply a current from the driver 310 to one of the digit lines DL1, DL2, and absorb the current from the other digit line into the sinker 320. The switching portion 400 is activated to connect the driver 310 and the sinker 320 to one of the digit lines DL1, DL2 in accordance with the intended flowing direction of the current.

[0316] In some cases, the upper and lower digit lines are disconnected by turning off the switching element Tr1, thereby to supply write currents in the same direction to these digit lines. In these cases, write current pulses can be sequentially supplied to the upper and lower digit lines DL1, DL2 from one or the other of the drivers 310, 330 by sequentially switching one of the switching portions 410, 420 on the part for supplying the current. This current is absorbed by the sinker connected to the other ends of the digit lines DL1, DL2 via the switching portion.

[0317] This Example can supply a current to the pair of upper and lower digit lines DL1, DL2 by using two sets of drivers and sinkers. Therefore, drivers and sinkers need not be increased, and the ratio of the memory area, i.e. array efficiency, can be enhanced.

[0318] Heretofore, some embodiments of the invention have been explained with reference to specific examples. The invention, however, is not limited to these specific examples. For example, the invention contemplates in its own cope all alternatives concerning materials, thicknesses, shapes, sizes, etc. of the ferromagnetic layer, insulating film, anti-ferromagnetic layer, nonmagnetic metal layer, electrode that are components of the magnetoresistance effect element as far as persons skilled in the art can appropriately select them and can practically use the invention to obtain substantially the same effects.

[0319] Similarly, the invention contemplates in its own scope all alternatives concerning structures, materials, shapes and sizes of the bit line, digit line, word line, overcoat layer, selection transistor, diode and other composing the magnetic memory according to any embodiment of the invention as far as persons skilled in the art can appropriately select them and can practically use the invention to obtain substantially the same effects.

[0320] Furthermore, the invention contemplates in its scope all magnetic memories that persons skilled in the art can make by modifying the magnetic memories shown here as embodiments of the invention.

[0321] While the present invention has been disclosed in terms of the embodiment in order to facilitate better understanding thereof, it should be appreciated that the invention can be embodied in various ways without departing from the principle of the invention. Therefore, the invention should be understood to include all possible embodiments and modification to the shown embodiments which can be embodied without departing from the principle of the invention as set forth in the appended claims.