High bandwidth memory interface

[0002] This application is a Continuation Application from U.S. application Ser. No. 09/182,494, filed Oct. 30, 1998 now U.S. Pat. No. 6,510,503, which claims priority from Canadian Application Serial No. 2,243,892, filed Jul. 27, 1998.

[0003] The present invention relates to computer memory interfaces and more specifically to chip-to-chip interfaces for dynamic random access type memories capable of operating at high speed. This application incorporates herein by reference Canadian Patent Application Number 2,243,892 filed on Jul. 27, 1998.

[0004] The evolution of the dynamic random access memories used in computer systems has been driven by ever-increasing speed requirements mainly dictated by the microprocessor industry. Dynamic random access memories (DRAMs) have generally been the predominant memories used for computers due to their optimized storage capabilities. This large storage capability comes with the price of slower access time and the requirement for more complicated interaction between memories and microprocessors/microcontrollers than in the case of say static random access memories (SRAMs) or non-volatile memories.

[0005] In an attempt to address this speed deficiency, various major improvements have been implemented in DRAM design, all of which are well documented. DRAM designs evolved from Fast Page Mode (FPM) DRAM to Extended Data Out (EDO) DRAMs synchronous DRAMs (SDRAMs). Further speed increases have been achieved with Double Data Rate (DDR) SDRAM, which synchronizes data transfers on both clock edges. However, as the speed requirements from the microprocessor industry continue to move ahead, new types of memory interfaces have had to be contemplated to address the still existing vast discrepancy in speed between the DRAMs and microprocessors.

[0006] Recently, a number of novel memory interface solutions aimed at addressing the speed discrepancy between memory and microprocessors have been presented.

[0007] Several generations of high bandwidth DRAM-type memory devices have been introduced. Of note is Rambus Inc which first introduced a memory subsystem in which data and command/control information is multiplexed on a single bus and described in U.S. Pat. No. 5,319,755 which issued Jun. 7, 1994. Subsequently, Concurrent Rambus™ was introduced which altered the command/data timing but retained the same basic bus topology. Finally, Direct Rambus™ described in R. Crisp “Direct Rambus Technology: The New Main Memory Standard”, IEEE Micro, November/December 1997, p.18-28, was introduced in which command and address information is separated from data information to improve bus utilization. Separate row and column command fields are provided to allow independent control of memory bank activation, deactivation, refresh, data read and data write (column) commands. All three Rambus variations however share the same bus topology as illustrated in FIG. 1(a).

[0008] In this topology a controller 10 is located at one end of a shared bus 12, while a clock driver circuit 14 and bus terminations 16 are located at an opposite end. The shared bus includes, data and address/control busses, which run from the controller at one end to the various memory devices MEMORY 1 . . . MEMORY N and the terminations at the far end. The clock signal generated by the clock driver 14 begins at the far end and travels towards the controller 10 and then loops back to the termination at the far end. The clock bus is twice as long as the data and address/control busses. Each memory device has two clock inputs ClkFromController and ClkToController respectively, one for the clock traveling towards the controller cTc, and another for the clock traveling away from the controller cFc towards the termination. When the controller 10 reads from a memory device, the memory device synchronizes the data it drives onto the bus with the clock traveling towards the controller. When the controller is writing to a memory device, the memory device uses the clock traveling away from the controller to latch in data. In this way the data travels in the same direction as the clock, and clock-to-data skew is reduced. The memory devices employ on-chip phase locked loops (PLL) or delay locked loops (DLL) to generate the correct clock phases to drive data output buffers and to sample the data and command/address input buffers.

[0009] There are a number of shortcoming with this topology as will be described below.

[0010] For the bus topology of FIG. 1(a) the clock frequency is 400 MHz. FIG. 1(b) shows the timing of control and data bursts on the bus 12. Since data is transmitted or received on both edges of the clock, the effective data rate is 800 Mb/s. A row command ROW burst consists of eight (8) consecutive words, beginning on a falling edge of the clock from the controller cFc and applied on the three (3) bit row bus. A column command COL consists of eight (8) consecutive words transmitted on the five (5) bit column bus. Independent row and column commands can be issued to the same or different memory devices by specifying appropriate device identifiers within the respective commands. At the controller 10 the phases of the two clock inputs, cFc and cTc, are close together. There is a delay to the memory chip receiving the commands due to finite bus propagation time, shown in FIG. 1 as approximately 1.5 bit intervals or 1.875 ns. The clock signal cFc propagates with the ROW and COL commands to maintain phase at the memory inputs. Read data resulting from a previous COL command is output as a burst of eight (8) consecutive 16 or 18 bit words on the data bus, starting on a falling edge of cTc. The data packet takes roughly the same amount of time to propagate back to the controller, about 1.5 bit intervals. The controller spaces COL command packets to avoid collisions on the databus. Memory devices are programmed to respond to commands with fixed latency. A WRITE burst is driven to the databus two bit intervals after the end of the READ burst. Because of the finite bus propagation time, the spacing between READ and WRITE bursts is enlarged at the memory inputs. Likewise, the spacing between a WRITE and READ burst would be smaller at the memory device than at the controller.

[0011] For example, there is a summation of clock-to-data timing errors in transferring data from one device to another. FIG. 2(a) is a schematic diagram of the loop-back clock, data lines and clock synchronization circuit configuration. In this configuration, the bus clock driver 14 at one end of the ClockToController line 22 of the clock bus propagates an early bus clock signal in one direction along the bus, for example from the clock 14 to the controller 10. The same clock signal then is passed through the direct connection shown to a second line 24 of the bus and loops back, as a late ClockFromController, along the bus where it terminates with resistance R_term. Thus, each memory device 26 receives the two bus clock signals at a different time. The memory device 26 includes a clock and data synchronization circuit for sampling the two bus clocks cFc and cTc and generating its own internal transmit and receive clocks TX_clk and RX_clk respectively, for clocking transmit and receive data to and from the databus respectively. The bus clock signals cFc and cTc are fed via respective input receiver comparators 11 and 20 into corresponding PLL/DLL circuits 40 and 50. For the input of data from the controller to a memory device, the role of the on-chip PLL/DLL circuit 40 is to derive from the cFc clock input, internal clocks to sample control, address, and data to be written to the memory on (positive 90° and negative 270°) edges of the clock, at the optimum point in the data eye. These internal receive data clocks may also be used to drive the internal DRAM core 32. For the output of data from the memory device 26 to the controller 10, the role of the on-chip PLL/DLL circuit 50 is to derive from the cTc clock input internal transmit data clocks (0° and 180°) to align transmitted data (read data from the memory core) with the edges of the external clock.

[0012] The data I/O pin has an output transistor 27 for driving the data bus. An actual memory device will have 16 or 18 such data pins. The other data pins are not shown in FIG. 2(a) for simplicity. During times when the device is not driving read data onto the databus the gate of output transistor 27 is held at logic 0 by OE being logic 0, so as not to interfere with write data or read data from another device which may appear on the bus.

[0013] Row control and column control input pins are also shown in FIG. 2(a) and it is understood that address signals are also received via the data bus. They have a structure identical to the data I/O pin, except that the gate of the output transistor 27′ is tied to logic 0, since output drive is never required. The disabled output transistor 27′ matches the capacitive load presented to the external bus to that of a data I/O pin, so that signal propagation characteristics are identical for all inputs, address row control, column control, and data. The two clock inputs have similar dummy output transistors 28 and 29, to equalize loading.

[0014] In the prior art system, Vterm is equal to 1.8 v, Rterm is 20Ω, and the current Iout provided by the device driving the bus is 40 mA. This is shown schematically in FIG. 2(b). In this configuration, a high level signal is equal to the bus termination voltage, Vterm (1.8 v) and a low level signal is equal to Vterm=Iout*Rterm (1.0 v). Power consumed while the signal is pulled low is 72 mW, of which 40 mW is dissipated on chip, and 32 mW in the termination. Assuming an equal probability of high and low data, the average power dissipation would be 36 mW, of which 20 mW is dissipated on chip and 16 mW in the termination.

[0015] Given the high and low voltage range, the reference voltage for the comparator is set to 1.4 v, which is midway between high and low levels on the bus. The input timing waveforms for this circuit configuration is shown in FIG. 3. The cFc signal is delayed from the pin through the input comparator 11. The rising edges of the clock cFc signal are shown as a shaded area 134 on the timing diagram because of the differences between the generation of rising and falling edges. Falling edges are more accurate since they are generated by on chip drivers and are calibrated to produce the desired low level signal on the bus. On the other hand, the rising edges are created by the bus termination pullup resistor and will have different edge characteristics depending on the distance from the termination, number of loads on the bus, etc. Because of the differences in rising and falling edges, the received clock and data signals may not have precise 50/50 duty cycles. The DLL/PLL block 40 responds only to the falling edge of the clock input, since it is the most accurate edge. The DLL/PLL generates four outputs at 0°, 90°, 180° and 270°. These outputs are phase locked to the data input. The DLL/PLL shifts the free running clock input to align the 0° and 180° outputs to input data edge transitions. The 90° and 270° outputs can then be used to sample input data in odd and even latches corresponding to data generated on rising and falling edges of the clock respectively.

[0016] There will be some timing error Δr and Δf, on the rising edge and falling edges of DLL outputs respectively, with respect to the output of the clock comparator, as shown in FIG. 3. These timing errors may occur due to any one or a combination of static phase offset, timing jitter and wander resulting from inaccuracies and mismatches within the components making up the DLL/PLL loop. The 0° and 180° outputs will be aligned to the average transition points. Since the DLL/PLL outputs a 50/50 duty cycle signal, while the data inputs may have a degraded duty cycle due to the aforementioned asymmetrical drive problem, this results in a further error in positioning the clock for optimal data sampling. The timing errors between clock and data created at the transmitting device and the receiving device are cumulative and can result in data errors.

[0017] The output timing waveforms for the circuit of FIG. 2(a) are shown in FIG. 4. The DLL/PLL 50 shown in FIG. 2(a) takes the free running ClockToController and creates delayed versions of the free running clock. The DLL/PLL monitors transmit data (read data from the core memory) output to the databus via output driver transistor 27 through comparator 30 and adjusts the delay of the 0° and 180° clocks which drive the output latches 51 to align output data transitions to transitions of the ClockToController transmit clock. Due to the asymmetrical nature of the rising and falling edges appearing on the ClockToController bus, all outputs from the DLL/PLL 50 are generated from falling edges of the free running input ClockToController clock. The output data latching function is shown conceptually to include odd and even data latches and a multiplexer which alternates between the two data streams. The output data latch is followed by an AND gate which performs an output disable function, holding the gate of output driver transistor 27 at logic zero when data is not being read from the device. Similarly to the input data case, timing errors between clock and data are cumulative and can result in data errors.

[0018] Another shortcoming of the prior art implementation shown in FIG. 1(a) is the system's method for dealing with intersymbol interference. Data transitions do not always occur in the same position relative to clock edges due to a number of factors. The clock is a repetitive waveform with which there will be a constant delay from one rising edge to another or from one falling edge to another. Data transitions are dependent on the previous bits transmitted, particularly on a long bus whose propagation delay exceeds one bit period. This effect is known as intersymbol interference (ISI). The effect of different data histories creates data transitions at different times relative to the clock. Basing the input sampling time purely on a fixed phase of the input clock, as in the architecture of FIG. 1(a), will be suboptimal in the presence of ISI. Other effects such as crosstalk coupling between other wires near the signal in question, which can be either in phase or out of phase, and data dependent power supply coupling affecting both input buffers and output drivers, can also close the effective data eye, i.e., the window during which data can be successfully sampled.

[0019] A further shortcoming of the prior art is that open drain outputs, shown schematically in FIG. 2(b) are used to drive signals from a device onto the bus in the system of FIG. 1(a). Because the falling edge of the clock is created by a clock generator pull-down transistor (not shown), while the rising edge is created by the bus termination resistor, it is difficult to match pulse rise time and pulse fall time. This can lead to non-symmetric duty cycle on the clock bus. To resolve this problem, the clock falling edge can be used as a timing reference and the clock rising edge can be re-synthesized internally with the DLL/PLL. However, this approach creates an internal sampling instant that is unrelated to the data edge of the bit being sampled, compounding the effects described above and resulting in further closure of the data eye, since subsequent data bits cannot be known in advance whereas a clock sequence is repetitive and therefore, determinable in advance.

[0020] Each device discussed above in the prior art self-calibrates its output pulse amplitude levels. Either an external reference or an internally generated reference level is required, along with precision comparator circuits and calibration control circuitry. Inaccuracies in any of these elements may lead the output amplitudes from different devices to vary, resulting in further closure of the data eye.

[0021] The number of devices in a the prior art configuration described above is limited to 32 because of the loading and length of the bus. With 64M devices the total memory capacity is limited to 256 MB. If a larger memory configuration is required the controller must support several busses in parallel, consuming additional pins, silicon area, and power.

[0022] The packaging technology for the prior art implementation described above is called Chip Scale Packaging or uBGA (micro Ball Grid Array). The intent of this packaging technology is to minimize the stub length from the connection to the bus to the on-chip input and output buffers. The length of the stub on the module is virtually eliminated by routing the bus through the module. Although stub length is reduced compared to standard packaging and module technology, there is still as much as 5 mm of stub within the uBGA package itself. This stub can cause reflections on the bus to the detriment of signal integrity.

[0023] Another shortcoming of the prior art approach is the requirement for a separate clock generator chip. Furthermore, there is twice as much load on the clock as on any other signal, and the clock line is twice as long. Ultimately, the maximum frequency at which the system can operate will be limited by the doubly loaded clock line. The pulse symbols in FIG. 5 show how systematic skew can develop between clock and write data at the far end of the bus. The clock reaching the controller cTc has already been attenuated by traveling the full length from the clock generator to the controller, and most of the higher order harmonics have been removed. At this point, cTc and cFc clocks should be identical and the controller synchronizes transitions of write data with zero crossings of the filtered cFc clock. The write data appears on the bus at this point with sharp edges and unattenuated amplitude. Because of the different frequency composition of the clock and write data, there is different group delay between clock and data at the far end of the bus. Since the cFc clock is somewhat attenuated already, further attenuation will not significantly affect its zero crossings. On the other hand, the write data, when attenuated, will lose its higher order harmonics which create the square wave form, resulting in a wave form as shown where the zero crossings have been significantly shifted. Therefore, transitions between clock and write data at the far end are skewed by an amount shown as t_skew. As a result, write data sampling will not occur at the correct time.

[0024] Thus it may be seen that the prior art configuration described suffers from various disadvantages. The present invention seeks to mitigate at least some of these disadvantages.

[0025] Accordingly, one object of the present invention is to provide an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load.

[0026] Another object of the invention is to eliminate the requirement for a separate clock generator chip.

[0027] A further object of the invention is to provide a clock adjustment scheme to compensate for intersymbol interference, crosstalk, noise, and voltage and temperature drift in memory devices.

[0028] A still further object is to provide an improved bus topology in which clocks travel the same distance as data and do not limit overall bus performance.

[0029] A still even further object is to provide an improved packaging for these devices.

[0030] A still yet even further object is to provide a means to expand the number of memory devices that can be supported by a single controller.

[0031] In accordance with this invention, there is provided a memory subsystem comprising

[0032] a) at least two semiconductor devices;

[0033] b) a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines;

[0034] c) a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

[0035] According to a further aspect of the invention there is provided

[0036] a) a core memory;

[0037] b) a plurality of terminal for coupling to a,bus including a free running clock and a data clock terminal and data I/O terminals;

[0038] c) a source synchronous clock generator for synchronising the output data clock with the output data in response to the free running clock.

[0039] According to one aspect of the invention the semiconductor devices include a clock offset fine adjustment for optimizing the sampling of received data, wherein the adjustment can be set during power up and periodically during operation by the controller to compensate for temperature and voltage drift.

[0040] A further aspect of the invention provides a memory subsystem including synchronous data clocks for source synchronous clocking, while the loopback clock is used to provide a free running clock to transmit data and to time the start of bursts to position consecutive data bursts appropriately in order to avoid overlap between consecutive bursts.

[0041] A further aspect of the invention provides a memory subsystem including means for calibrating the clock offset fine adjustment by utilizing a power up synchronization sequence. Preferably, the synchronization sequence is a bit sequence that includes a number of bit patterns such as a psuedorandom pattern to evaluate substantially all meaningful intersymbol interference histories in order to set an optimum time for a sampling instant.

[0042] A further aspect of the invention provides a memory subsystem loopback clock architecture including a push pull I/O. This allows both rising and falling edges to be used for sampling data, thereby reducing the sensitivity of the system to clock duty cycle variation. This approach also saves power in the device itself allowing more cost-effective packaging.

[0043] A further aspect of the invention provides a memory subsystem wherein the semiconductor device includes a controller, which in turn includes means for calibrating the output high/output low voltage levels Voh/Vol of the memory devices by writing to registers in the memories to increment or decrement output levels and comparing the result on the bus to a reference voltage level local to the controller.

[0044] A further aspect of the invention provides a memory subsystem wherein a repeater appears as a single load on the main bus but drives a set of signals identically to the controller to create a sub-bus on which memory devices can be connected. The repeater acts as a controller on this sub-bus and memory devices cannot distinguish between the main bus and the sub-bus and therefore, operate identically on either one. The increased latency of devices on the sub-bus compared to those connected directly to the main bus may be corrected by the controller by scheduling activity appropriately.

[0045] A still further aspect of the invention provides a memory subsystem, wherein the semiconductor devices include series stub resistors wherein the main bus is routed through the device to mitigate the effects of the stubs. Furthermore conventional TSOP type packaging is used for lower cost.

[0046] In accordance with a further aspect of this invention, there is provided a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all address, data and control information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; where read and write data are accompanied by echo clocks, and burst placement is performed via vernier adjustment under control of the controller.

[0047] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which:

[0048] FIG. 1(a) is a schematic diagram of a bus topology according to the prior art;

[0049] FIG. 1(b) is a schematic diagram showing packet timing for the architecture of FIG. 1(a);

[0050] FIG. 2(a) is a schematic diagram of a memory device and its clock synchronization circuitry for the bus topology of FIG. 1(a);

[0051] FIG. 2(b) is a schematic diagram of a bus termination circuit;

[0052] FIG. 3 is a timing diagram showing data input timing for the circuit of FIG. 2(a);

[0053] FIG. 4 is a timing diagram showing data output timing for the circuit of FIG. 2(a);

[0054] FIG. 5 is a schematic diagram showing a systematic skew between a clock and data signal in the topology of FIG. 1(a);

[0055] FIG. 6(a) is a schematic diagram of a bus topology implementing a synchronous clock scheme according to a first embodiment of the present invention;

[0056] FIG. 6(b) is a diagram showing timing signals of the bus topology shown 6(a);

[0057] FIG. 7 is a schematic diagram of a bus topology according to a second embodiment of the present invention;

[0058] FIG. 8(a) is a schematic diagram of an input interface according to an embodiment of the present invention;

[0059] FIG. 8(b) is a timing diagram for the bus topology shown in FIG. 7;

[0060] FIG. 8(c) is a schematic diagram of an input interface for a controller according to an embodiment of the present invention;

[0061] FIG. 9 is a timing diagram showing data recovery with non-symmetrical duty cycle;

[0062] FIGS. 10(a) and (b) are flow charts showing controller and memory synchronization operation;

[0063] FIG. 11(a) is a circuit diagram and timing diagram illustrating a psuedorandom sequence generator according to an embodiment of the present invention;

[0064] FIG. 11(b) is a circuit diagram of a synchronization pattern detector circuit;

[0065] FIG. 12 is a schematic diagram of a bus topology according to a third embodiment of the present invention;

[0066] FIGS. 13(a) and (b) are schematic diagrams of a memory module according to the prior art;

[0067] FIG. 14(a) is a schematic diagram of a termination module according to the embodiment of the invention;

[0068] FIG. 14(b) is a schematic diagram of a termination module according to a further embodiment of the present invention;

[0069] FIGS. 15(a) and 15(b) are respective top and bottom plan views of a semiconductor packaging according to one embodiment of the invention.

[0070] Referring to FIG. 1(a) a general prior art architecture on which the present memory subsystem is based is indicated by numeral 2 and is described in greater detail in R. Crisp “Direct Rambus Technology: The New Main Memory Standard”, IEEE Micro, November/December 1997, p. 18-28, incorporated herein by reference. The memory subsystem 2 includes a main bus or channel 12 which consists of a plurality of high speed controlled impedance matched transmission lines, a controller 10 and at least one memory device 11 connected thereto in parallel. The channel 12 has a bus topology with the controller 10 at one end, terminators 16 at the other end and memory devices 11 in-between. The transmission lines include a ClockToController line; a ClockFromController line; a data bus; a row bus and column bus each carrying correspondingly named signals. These signals are terminated at their characteristic impedance R_termat the far end of the channel.

[0071] The terminators pull the signals up to the system supplied V_termvoltage, which corresponds to logic 0. The semiconductor devices (controller and memory) assert a logic 1 by sinking current from the wire, using an open-drain NMOS transistor. The logic levels are generated about a reference voltage V_refset by a resistive divider as shown in FIG. 1(a). As shown V_refconnects to each device.

[0072] In the embodiment of FIG. 1(a), the clock source is shown as a separate generator 14, however it can be integrated into the memory controller. The clock loop consists of first and second lines connected at one end. As shown, the clock loop begins at the clock generator end of the channel and propagates to the controller end as ClockToController, where it loops back at the connection between the first and second lines as ClockFromController to the memory devices and terminates. Improvements in the above architecture, which constitute embodiments of the present invention are now described below.

[0073] Referring to FIG. 6(a) a memory subsystem for implementing “controller source synchronous clocking” according to an embodiment of the present invention is shown generally by numeral 60. The memory subsystem 60 includes a main bus or channel 62 which consists of a plurality of high speed controlled impedance matched transmission lines, a controller 64 and at least one memory device 66 connected thereto in parallel. The channel 62 has a bus topology with the controller 10 at one end, terminators 68 at the other end and memory devices 66 in-between. The transmission lines include a ClockToController line cTc; a ClockFromController line cFc; a data bus; a row bus; column bus and a Vref line each carrying correspondingly named signals. These signals are terminated at their characteristic impedance R_termat the end of the channel 68. The reference voltage V_refset by a resistive divider 69. Each device connected to the bus has correspondingly named terminals.

[0074] The terminators 68 pull the signals up to the system supplied V_termvoltage, which corresponds to logic 0. The semiconductor devices (controller and memory) assert a logic 1 by sinking current from the wire, using an open-drain NMOS transistor. The logic levels are generated about the reference voltage V_ref. As shown V_refconnects to each device.

[0075] The controller includes a clock generator 70 for generating the free running clock signal which is driven on to the bus from the cFc pin. The clock line cFc loops around at the far end 68 and returns as the cTc line. The cTc line re-enters the controller to clock in read data from the memory devices 66. The termination resistor R_ctermfor the looparound clock is located, near the controller 64. Each of the output pins of the controller have push-pull drivers. The clock output driver circuit (not shown) is matched to the row command, column command, and write data output drivers. Any temperature or voltage supply variations affecting the command or data output drivers will affect the clock output equally. Because clock and data are produced by identical drive circuits in the controller 64, and both signals propagate over similar busses, some of the skew problems associated with the loop-around clock shown in FIG. 1(a) are overcome. The controller does not have to implement a PLL/DLL aligning circuit to align control and data bursts originating from the controller to the cFc clock. This technique for matching clock and data is known as “source synchronous clocking”. The clock line cFc loops around at the far end and returns as the cTc line. The cTc line re-enters the controller to clock in read data from the memory devices 66. The termination resistor R_ctermfor the looparound clock is located, near the controller 64.

[0076] A further advantage of the present topology is that no changes are necessary in the memory devices 66 from the prior art memory shown in FIG. 2(a) and devices as these will function correctly with the modified source synchronous bus topology. Bus timing will be identical to that shown in FIG. 1(b).

[0077] An alternative approach is change the phase relationship between clock and data to simplify receiving circuitry in both controller an memory devices.

[0078] Referring to FIG. 6(b), the timing waveforms for the bus signal at the controller 64 and the memory device 66 of FIG. 6(a) are shown respectively by numerals 72 and 74. The clock 76 and data 77 waveforms are generated with a 90° relative phase shift, to position clock transitions in the center of the data eye.

[0079] Positioning of the clock transitions in the centre of the data eye is accomplished in the controller by selecting appropriate outputs from an on-chip PLL/DLL locked to the free running system clock cFc to separately drive data output and clock output circuits. The approach of the subject invention allows the receiving memory device to use the received clock cFc to latch data directly, without the need for a PLL/DLL, provided clock and data delays to the actual receive data latch are matched. Only one PLL/DLL is required in the memory devices to center read data transitions between edges of the cTc clock, saving both power and die area.

[0080] Another embodiment of the present invention is illustrated in FIG. 7 is shown by numeral 80, which shows a bus scheme having fully source synchronous clocking, including data clocks 81, dclk0, dclk1, and a free running reference clock 86. The memory devices 84 and the controller 82 drive clocks to accompany read data and write data. The controller 82 includes a clock generator 86 for generating the free running reference clock CLK 86. This single clock 86 is driven from the controller 82 in a source synchronous fashion with row and column command packets on the ROW and COL lines. The clock line ClK is now identical in length and loading to the ROW/COL command and data busses in the system. The clock is terminated at the far end 85.

[0081] Clock and data waveforms are matched at all points in the system. The proper positioning of data bursts from different devices is achieved by latency calibration under control of the memory controller. This makes the loop-back clock bus as described in FIG. 6(a) unnecessary. Although the clock is shown as a single ended signal, it may in fact be implemented as a differential signal driving both inputs of an input comparator within each memory device. This eliminates sensitivity of the clock path to Vref threshold variations and common mode noise throughout the system.

[0082] The controller 82 and memory devices 84 also include an SO and SI terminal for providing a low speed serial daisy chain from controller through all the memory devices 84 and back to the controller 82 to indicate when all memories have synchronized. The operation of this will be described later.

[0083] The source synchronous data clocks dclk0 and dclk1 are provided in the controller 82 for timing data in a source synchronous manner. During read operations, the memory devices 84 drive one of the data clocks dclk0 and dclk1 in a source synchronous manner along with read data on the databus. The controller 82 schedules which of the data clocks should be used and supplies this information to the memory either in the column command packet or through another control path. The controller 82 therefore knows which data clock to use to latch in read data. In one embodiment, the memory devices use the free running clock to latch write data in the same way that ROW and COL command packets are latched. However, the preferred embodiment uses data clocks for write data input latching in the memory devices. This allows the data path to be routed or buffered independently of the control path. This has advantages in creating hierarchical memory subsystems as will be described later.

[0084] Referring to FIG. 8(a) a memory device interface circuit for use in the source synchronous scheme of FIG. 7 is shown generally by numeral 90. The interface comprises input terminals for connection of the device to appropriate signals on the bus; an I/O driver section 94 employing push-pull configured transistors for driving both ‘0’ and ‘1’ data; an input stub section having series stub resistors R_sinterposed between each input terminal and the push-pull drivers; a reference voltage input 96 and a command and data interface section 98 converting the externally received command and data signals as well as clock signals into internal signals. The command and data interface section 98 includes programmable delay elements for driving the core DRAM with appropriately delayed internal signals (as will be described later). This section also receives signals from the core DRAM for driving onto the bus including generating the dclk0 and dclk1 clocks for source synchronous transmission with the data.

[0085] An advantage of the above interface configuration is that signal logic level transitions are better controlled since both 0′s and 1′s originate from drivers within the transmitting device. This allows both rising and falling edge clocks to be used to latch data compared to the prior art wherein only falling edges were used.

[0086] The command and data interface 98 shown in FIG. 8(a) includes a first set of programmable delay circuits 102 and 104 for delaying both the rising and falling edges of the received clock CLK, producing the even clock CLK_E and odd clock CLK_O signals, which latch even and odd row commands row_E, row_O as well as even and odd column commands col_E, col_O in the core DRAM via D-type flip-flops 106.

[0087] Separate programmable fine vernier delays 107 and 108 receive as inputs the clock signal CLK and delay the rising and falling edges to generate delayed signals OUTCLKE and OUTCLKO. These signals drive the clock input of respective D-type latches 120 and 122 for latching the even Data_Out_E and odd Data_Out_O output data signals from the core DRAM. The latched data output signals are processed one at a time by multiplexer 124, which drives the selected latched data signal onto the data line. The multiplexer 124 is controlled by one of the clock signals, OUTCLKO in this case. The same signal controls a multiplexer 126, which selects one of the signals OUTCLKE and OUTCLKO latched in respective D-type latches 128 and 130, which drive the dclk0 and dclk1 lines to achieve source synchronous clocking. The first multiplexer 124 selects between odd and even data and the second multiplexer selects between odd and even clocks. This allows synchronization of the output data with the output clocks. The input latching circuitry can therefore be optimized to work in the presence of non-symmetrical clock duty cycles, since odd and even data are latched by odd and even edges of the associated source synchronous clock. An instruction decoder 132 provides the relevant signals, such as the data clock output enable signals DCOE1, {overscore (DCOE1)}, DCOE0, {overscore (DCOE0)}; select data clock signal SDCL; signal for initiating the preamble state machine GO; and data output enable signals DOE and {overscore (DOE)}.

[0088] The data input to the memory is also synchronized with the data clocks dclk0 and dclk1. The data clocks dclk0 and dclk1 are received at the inputs of a multiplexer 116, which is controlled by a SDCL signal generated by the instruction decoder 132. The data clocks are delayed by programmable delays 109 and 110 to produce respective even and odd delayed clocks DCLK_E and DCLK_O. These even and odd clocks are used to clock respective D-type latches 134 and 136, for latching the incoming data as data_in_E and data_in_O.

[0089] The latching of odd and even data is shown in FIG. 9 where a delay Δ_Ebetween the falling edge of the clock input to the rising edge of clk_E centers the sampling instant in the middle of the data generated with the falling edge of the clock input, and a Δ_Obetween the rising edge of the clock input to the rising edge of clk_O centers the sampling instant in the middle of the data generated with the rising edge of the clock input.

[0090] With respect to the output buffer structure illustrated in FIG. 8(a), the preferred embodiment employs a push-pull output buffer which drives both ‘0’ (Vol=0.9V) and ‘1’(Voh=1.6V) data. This is based on EIA/JEDEC Standard “Stub Series Terminated Logic for 3.3 Volts (SSTL_—3)”, EIA/JESD8-8, August 1996, although the levels are scaled down for 2.5 v operation. The series stub resistors Rs isolates the device load from the main transmission line, reducing the bus impedance lowering effect of the device's point capacitive load. Power is lower than the prior art open drain approach because current output levels are +I/2,−I/2 rather than +I,0 for the open drain case.

[0091] The reference voltage V_refis equal to the termination voltage of 1.25 V. Assuming for comparison purposes a 20 ohm termination and a 20 ohm series resistor, the current required to create a 0.8 v swing equivalent to the prior art is +/−20 mA. Power consumption is thus data independent at 25 mW per pin, of which only 9 mW is dissipated on chip. Since output current is lower, the output driver transistors can be smaller, further reducing pin capacitance. Most importantly, on-chip I/O power dissipation is much smaller because of the smaller current and the smaller on-chip voltage drop resulting from the series stub resistor. The combined effect of series stub resistor and smaller output driver load capacitance results in higher effective transmission line characteristic impedance, perhaps 30Ω. Consequently, the termination resistor value can be increased which results in further power savings.

[0092] As illustrated in FIGS. 8(a) and 8(b), two data clocks are used to improve bus utilization, dclk0 and dclk1. During the transition between data bursts originating from one device to another, the clock and data lines return to the voltage set by the termination resistor. During this inactive time, the device that is to receive the next data burst must enable its input buffers to start receiving data with the next transition on the clock input. If only a single dataclock were employed, the inactive time would have to be extended to allow sufficient safety margin in the receiving device to unambiguously enable its input clock path. Glitches on the data inputs are acceptable since data is sampled, but glitches on the internal clocks can cause a complete breakdown of input data pipelines. The time to merely power up differential input buffers may be longer than a single bit period. Furthermore, there may be different delays in the control path to each device, possibly as a result of address/control buffers that may or may not be present on a module. If a device enables its input path too soon, it may latch the last bit of the preceding burst. If it enables its input path too late, it may miss the first bit of the burst it is intended to receive. The inactive time could be widened to ensure that neither of these errors occur, but this approach would reduce data bus utilization and overall system bandwidth.

[0093] A solution, according to an embodiment of the present invention, is to provide the two data clocks dclk0 and dclk1 to allow devices to pass control of the data bus with minimum gap as shown in FIG. 8(b). Dual data clocks allow source synchronous clocking to achieve as tight a burst-to-burst timing as in the prior art. The device receiving a burst can enable its input path well in advance of the beginning of the actual data burst during the preamble period when the dclk (dclk1 in this case is used for the right burst) is held at a low level for 3 bit periods. At this time a preceding data burst may actually be present on the data bus with associated activity on the other data clock (in this case a read burst controlled by dclk0 is shown). Each successive burst uses the opposite data clock from the previous burst. This can be synchronized on power up by having each device count odd and even bursts, or, by having the controller provide within each read and write command to the memory devices, an indication of which clock to use.

[0094] As a further improvement to this scheme, a preamble can be transmitted before the clock transition associated with the first bit of data. Referring back to FIG. 8(a), a state machine 134 is shown for generating the preamble. The state machine receives as inputs the clocks OUTCLKE and OUTCLKO. The preamble is initiated by applying a signal to its GO input. A 1-bit preamble is shown in FIG. 8b. With the 1-bit preamble, the receiving device would ignore the first edge of the clock and begin clocking data on the second edge (with appropriate delay through the vernier). The preamble removes intersymbol interference from the clock pulses. Because the clock starts from a constant low level, the first transitions may be skewed relative to subsequent transitions that occur after the response has reached a steady state. The dual clock approach allows such preambles to be added to the burst without increasing the space between bursts.

[0095] Referring to FIG. 8(c) a schematic diagram of a controller interface is shown generally by the numeral 150. The interface circuitry 150 in the controller is simpler than that of the memory device shown in FIG. 8(b). Clock CLK 152, ROW 154 and COL 150 command are all outputs driven by identical I/O circuits 158. The outputs are latched on edges of the same internal clock {overscore (CLK)}. Dummy input buffers may be included to match input capacitance with the data bus interface circuits. The write data output path is driven by the same clock driving CLK, ROW and COL outputs. Therefore, the write data output fine verniers are not required. The read data input path is the same as the write data input path in the memory device. Programmable delay elements 155 which are programmed on receipt of the synchronization pattern adjust the received data clock to latch received read data in the controller. As in the memory device interface a state machine 157 is provided for generating the preamble on the dclk's.

[0096] Referring to FIGS. 10(a) and (b) the sequence of events required on system initialization to synchronize the memory devices to the controller is shown. This relies on the low speed serial daisy chain connection from the controller through all the memory devices and back to the controller to indicate when all memories have synchronized. The controller first sets its programmable delay to minimum and then begins to transmit a synchronization pattern on the outputs accompanied by clock(s). Preferably, the synchronization pattern will be transmitted on all outputs, including row, column, and data busses, although the memories could synchronize based on a single input. The synchronization pattern (hereinafter referred to as the sync pattern) should be a pattern that cannot be confused with a valid command, even when the receiving device is not in sync. The preferred sync pattern will be discussed later in greater depth.

[0097] Referring specifically to FIG. 10(a), illustrating the controller synchronization flow, the controller sets its SO output to logic ‘1’ and begins transmitting the sync pattern. When the controller receives a logic ‘1’ at its SI input, indicating that all memory devices in the chain have synchronized, it can begin transmitting normal command packets to the devices.

[0098] Referring now to FIG. 10(b) the synchronization flow chart for memory devices is shown. When a memory device detects the sync pattern on its input(s), it drives its SO terminal to a logic ‘0’ level and sets the programmable delay blocks 104 and 102 shown in FIG. 8(a) generating CLK_E and CLK_O to the minimum delay settings. The latched received even and odd data from row and column inputs, ROW_E, ROW_O, COL_E, and COL_O is compared to the expected sync pattern. If the received data is identical to the sync pattern on all inputs the device is said to be in sync. The delay settings are incremented to identify a window where the sync pattern is received without error. This represents the composite eye opening for all inputs and the synchronization sequence essentially amounts to stepping through the composite data eye to define its boundaries sync min and sync max. The final delay values written into the programmable delay circuits are set to the center of the window for maximum timing margin.

[0099] An identical process occurs for write data inputs to determine the proper settings for DCLK_E and DCLK_O delay circuits 109 and 110. Once all 4 delay values have been determined, the memory device sets SO=SI. A logic ‘1’ will ripple through the serial daisy chain bus as each device completes its synchronization sequence, producing finally, a logic ‘1’ level at the SI input of the controller.

[0100] The I/O levels and duty cycle are calibrated and matched in a similar fashion. After synchronization, the controller sends commands to each memory device in turn to drive the data bus with high and low logic levels. The controller then measures the Voh and Vol levels of individual memory devices and sends commands to registers within each device to increase or decrease the levels appropriately. The output drivers are composed of binary weighted segments that can be enabled or disabled depending on the programmed Voh or Vol levels. Because all I/O's are calibrated to a single reference level in the controller, there is less variation between devices and the data eye opening will be improved. In contrast, in the prior art each device calibrates its own output level resulting in variation due to differences in the local reference and termination resistor.

[0101] Following the synchronization sequence and I/O level calibration, the controller can then adjust the timing of read data bursts by requesting a read data burst from each memory device in sequence, observing the phase of the received data burst, and then making appropriate adjustments to the output clock delay registers in the memory devices.

[0102] The controller may also perform input sampling clock calibration by instructing a memory device to transmit a synchronization pattern on the data bus, and then following the procedure outlined in FIG. 10(b) to adjust its own input sampling clock delay circuits. By performing input sample clock timing adjustment in this manner rather generating a fixed phase based on the input clock as in the prior art, the preferred embodiment can compensate for skews and mismatches in the wiring, crosstalk between different signals, ground bounce and ISI. Likewise, the read data burst timing adjustment also compensates for system-wide skew, rather than just on-chip skew.

[0103] The synchronization pattern must be selected to create a worst case ISI scenario. The sync pattern generator according to an embodiment of the present invention, as shown in FIG. 11(a), creates all possible 3 bit sequences with the exception of ‘111’. The circuit generates a 7-bit repeating psuedorandom pattern. A useful property of the pattern is that if every 2^ndbit is sampled, the same 7-bit repeating pseudorandom pattern will result. Therefore, the adjustment of odd and even clock delays in the receiving device can be done independently. The sync pattern can be most easily detected by a sequence of 3 successive ‘0’s. Even if the input clock delays are not properly adjusted it is guaranteed that at least 2 successive ‘0’s would be latched. As long as one bit of a valid instruction stream can never have 2 successive ‘0’s, there will be no ambiguity in identifying when a sync pattern is received. For example, each of the ROW and COL busses should include framing bits that have this property. Psuedorandom sequences of any desired length 2^N-1 can be generated in this manner with the appropriate feedback polynomial. Generally, the length of the polynomial should span the settling time of the bus.

[0104] FIG. 11(b) shows the sync detector. In the preferred embodiment, all lines in the bus will be driven with the sync pattern. A best 2 of 3 vote is taken on 3 of the inputs, and the result is compared to each individual input. If any input is different from the best 2 of 3 vote result, then there is an error and the device cannot be considered “in-sync” for that particular input clock delay setting. The best 2 of 3 vote is provided as input to a feed forward version of the psuedorandom generator, which is used to predict the next bit of the sequence. This is compared to the actual received bit to determine whether the device is “in-sync”. If the error flag remains inactive and the sync flag remains active for the duration of one full cycle of the 7-bit psuedorandom sequence, then the programmable clock delay setting represents a valid sampling point within the composite eye.

[0105] Another advantage of the present invention is that the number of memory devices connected to a source synchronous bus can be increased through the use of simple bus repeaters, while keeping the loads on a single set of lines to a minimum.

[0106] FIG. 12 shows a buffered module 160 that contains two memory devices 162, each driving its respective separate data bus data A and data B back to the controller and having a bus topology similar to that of FIG. 7. This configuration is useful when the application requires more bandwidth than a single memory device could provide. A single row and column command stream 163 is received by a buffer 164 and is directed to more than one memory device 162 on the module along a local row and column command buss 166. The module therefore presents only one load to the bus. Each memory device can operate in parallel to deliver a higher data bandwidth back to the controller 165. The local row and column command bus 166 may be terminated 167. Although the buffer 164 introduces delay into the command path, the relationship between clocks and the associated data remains unchanged. In the buffer, the row and column command busses 163 are latched exactly as they are within the memory devices 162, and then they are regenerated along with the clock clk0 to drive the internal bus 166. Read data and write data on busses dataA and dataB are clocked by their respective data clocks dclkA and dclkB in both directions. The additional delay within the buffer 164 can be compensated through timing adjustments made by the controller 165 through writing appropriate delay registers in the memory devices. Because all timing adjustments are made by the controller, it is possible to mix buffered and unbuffered modules in the same system and achieve consistent timing between all memories. This increased bandwidth with no additional drawbacks to the system contrasts the prior art approach which was limited to 32 devices.

[0107] For memory systems requiring deeper address space it is also possible to buffer the data busses and connect more than one memory device on each module to the main databus. The databus buffers must capture and regenerate signals bidirectionally.

[0108] Referring to FIGS. 13(a) and 13(b), a prior art memory module in which the main busses are run through the module itself to minimize stub lengths, is indicated generally by numeral 170. The modules include a circuit board 172, having a plurality of memory devices 174 and a pair of connectors 175 arranged along one edge of the board 172 and spaced at opposite ends thereof. A clock generator 176 and termination resistors 178 are positioned on the main motherboard 180 at the far end of the bus. The bus enters the module at one end 182, travels through the module making connection to each memory device, and then exists the module at the opposite end 184. To maintain bus connectivity in systems that are not fully populated with memory, it is necessary to insert dummy modules.

[0109] Referring to FIG. 14(a), a schematic termination diagram of a module with memory 190 according to an embodiment of the present invention is shown. The module 190 includes a clock generator 192 and the termination resistor 194 with a plurality of memory devices 196. Computing of signals to the module from the bus is made via a set of contacts 198 at one edge of the module. Only one such termination module would be required in a system, rather than many dummy modules in a highly expandable but sparsely populated memory system. The termination module can be made reversible so that it can plug into even or odd module sockets. When the memory system is to be upgraded with an additional module, the termination module may be shifted one slot further out to create a space for the additional memory. The termination module includes memory devices, so that motherboard sockets can be maximally utilized. A system that is not fully populated may operate at a higher frequency because the bus is shorter and attenuation and timing skew at a given frequency will be lower. In FIG. 14(b), a schematic diagram of a termination module without memory is shown generally by numeral 200. This module differs from that of FIG. 14(a) only in that it does not include memory devices. It may be seen that in the modules 190 and 200, the bus does not travel through the module.

[0110] The chip packaging employed in the prior art devices is a uBGA (micro Ball Grid Array) chip scale package which is roughly the same size as the die. These packages have shorter stub lengths than conventional packaging. The stub includes the length of the bond wire, the lead frame, and the via to the main bus. This length may be approximately 5 mm. At lower frequencies, a stub of this length will not degrade the transmission line properties of the main bus significantly, although the point capacitive load of the chip I/O structure is of concern. At operating speeds greater than 1 Gb/s, even a 5 mm stub can degrade performance.

[0111] Referring to FIG. 15(a) and 15(b), a respective top and bottom views of a uBGA package according to an embodiment of the present invention, is shown by numeral 220. The packaging consists of a BGA substrate 222, to which is mounted on a top surface thereof chip 224. Bonding wires 236 are connected from the bonding pads 228 via through-holes 230 to a bottom surface of the substrate 222. The top side is encased in a plastic encapsulation 232.

[0112] Referring to FIG. 15(b), the bonding wires are connected to deposited resistors 234 to BGA balls 236 on the bottom of the substrate.

[0113] The series resistor film 234 near the BGA solder ball 236 acts to minimize the effect of the stub and point load of the chip I/O. The resistor, typically 20 ohms, is located as close to the ball as possible to isolate as much of the stub as possible from the main bus so that reflections are quickly damped. The resistor is created by depositing a resistive material on selected areas of one layer of the uBGA substrate, or by depositing resistive material over the entire layer and then etching the unwanted material away, using pholithographic processes. With this approach, the series resistor is located very close to the main transmission line, and no additional board area is required for discrete resistors.

[0114] While the invention has been described concerning a specific embodiment thereof and in a specific use, various modifications thereof will occur to those skilled in the art without departing from the spirit of the invention.

[0115] The terms and expressions which have been employed in the specification are used as terms of description and not of limitations, there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention.