Method and apparatus for creating a reliable long RC time constant

[0002] The present invention generally relates to integrated circuits (ICs) and, more particularly, to a method and apparatus for creating a reliable long resistor/capacitor (RC) time constant in order to reduce the possibility of electrostatic discharge (ESD) core shunts being turned on in the IC when they shouldn't be.

[0003] One well known use for creating long RC time constants is in ESD structures, which are used to shunt static electricity from power supplies (VDD) in an IC to ground. As is commonly known in the art, static electricity can build up on VDD nodes within an IC due to various causes, such as when a person handling the IC touches a pin of the IC. This is one type of ESD event that causes a VDD node to begin charging up, and this charge needs to be shunted to ground to prevent damage to the IC. The manner in which an ESD event is commonly handled can be seen in FIG. 1.

[0004] FIG. 1 illustrates a schematic diagram of a typical ESD structure 1. During an ESD event, the VDD node 2 begins being charged and the power supply begins to rise. The SHUNTN signal remains constant due to the high RC time constant of the resistor 3/capacitor 4 combination. When VDD rises to a high enough level, it will begin to turn on the PFET, p1, labeled with the numeral 5. This, in turn, will charge up the gate node 6, which will turn on a relatively large NFET, n2, labeled with the numeral 7. The NFET n27 is designed to shunt large amounts of current between VDD and ground, GND. This provides an ESD path from VDD to GND during an ESD event, thereby preventing elements in the IC from being damaged due to high voltages caused by the build up of electrostatic charges.

[0005] In current ESD structure designs, it is known to use either a poly, active, or nwell resistor in combination with a diode to create the RC combination represented by the resistor 3/capacitor 4 combination shown in FIG. 1. The problem with such an ESD structure is that, because of the large RC time constant needed (e.g., >300 nanoseconds (ns)), this design may allow charge to leak off of the SHUNTN node 8. The charge on the SHUNTN node needs to remain relatively stable to ensure that the RC time constant is longer than an ESD event. Otherwise, the ESD structure will not operate properly, i.e., the gate node 6 will not charge up and turn on NFET n27, and the charge on VDD will not be shunted from VDD through NFET n27 to GND.

[0006] Accordingly, a need exists for an ESD structure with a reliable long RC time constant. By ensuring that the RC time constant is reliable, any potential damage to elements of the IC due to high voltage levels caused by electrostatic charge build up can be prevented.

[0007] In accordance with the present invention, an electrostatic discharge (ESD) structure is provided for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between the shunt node and ground to ensure that, during an ESD event, electrostatic charge on the power supply VDD is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems due to parasitic capacitance associated with an RC component comprised of either a poly, active, or nwell resistor in combination with a diode are eliminated. The problem with such an ESD structure is that, because of the large RC time constant needed, this design may allow charge to leak off of the SHUNTN node. By using metal to create the metal resistor and capacitor, such charge leakage problems caused by parasitic capacitance are eliminated, which results in a more reliable RC component and thus a more reliable RC time constant.

[0008] These and other features and advantages of the present invention will become apparent from the following description, drawings and claims.

[0009] FIG. 1 is a schematic diagram of an ESD structure of an IC.

[0010] FIG. 2 is a top view of an example embodiment of the capacitor of the ESD structure of the present invention.

[0011] FIG. 3 is a side view of an example embodiment of the metal resistor of ESD structure of the present invention.

[0012] FIG. 4 is a top view of the metal resistor structure shown in FIG. 3 without the lower metal portion.

[0013] FIG. 5 is a top view of a portion of the ESD structure of the present invention that utilizes the capacitor shown in FIG. 2 and the resistor shown in FIG. 3.

[0014] In accordance with the present invention, the capacitor used for the ESD structure is capacitance created by placing metallic lines on the IC that have relatively high side walls in a pattern such as that shown in FIG. 2. The resistor used for the ESD structure is via resistance of metallic interconnected structures formed on the IC that have a design such as that shown in FIG. 3. By using metallic capacitance and resistance, and by removing coupling to the silicon, charge leakage problems of the RC component caused by, for example, parasitic capacitance devices such as diodes, are obviated.

[0015] Although metal is of relatively low resistance, via resistance is relatively large. Therefore, by connecting many of the structures shown in FIG. 3 in series, a sufficiently high resistance can be obtained to generate the necessary RC time constant of the ESD structure, as discussed in detail below with reference to FIG. 4. With respect to the metal capacitor shown in FIG. 2, the metal height of the walls is larger than the metal spacing of the walls, which creates a lot of capacitance between neighboring side walls. This feature of the present invention also takes advantage of improvements in IC process technologies.

[0016] As IC processes become increasingly capable of scaling down component sizes, the ratio of the heights of the metal lines to the minimum widths of the metal lines has increased. This is intentionally done in current IC processes to prevent metal signal lines from having too much resistance.

[0017] Also, with current IC processing technologies the heights of the metal lines compared to the space between the metal side walls of the metal lines is approximately 2-to-1 in units. Thus, the capacitance attributed to the spacing between neighboring metallic side walls of the metal lines can be very large. Furthermore, by placing metal layers one atop of the other, such as by placing one of the structures shown in FIG. 2 a small distance above or below another of the same structures, additional capacitance can be created.

[0018] FIG. 2 illustrates one of the metal capacitor structures 10 of the present invention in accordance with an example embodiment. The structure 10 is comprised of interleaved metal lines 12, some of which are connected to ground, GND 13, and some of which are connected to SHUNTN 14. The drawing of the structure 10 is not to scale and therefore does not precisely show the aforementioned width-to-height ratios of the metal lines 12 or the spacing between the metal lines 12, both of which contribute to the capacitance of the structure 10. Also, because FIG. 2 is a top view, these physical features are not illustrated.

[0019] As stated above, one or more structures such as the structure 10 shown in FIG. 2 can be placed one atop of the other with a spacing in between them to create additional capacitance. Also, the structure 10 is, in reality, only a portion of what the actual metal capacitor would look like in an IC. The actual structure would have a large number of extremely thin metal lines with extremely small spacings in between them. The width-to-height ratios of the lines and their lengths are not limited to any particular dimensions and are scalable in accordance with the IC process used to fabricate the IC. Therefore, these dimensions are subject to change depending on the IC fabrication process used to create the IC, regardless of whether the process is one currently being used or one developed or modified in the future.

[0020] FIG. 3 is a side view of an example embodiment of the metal resistor 20 of the present invention connected on one end 21 to the VDD node (FIG. 1, labeled 2) and on the opposite end 22 to the SHUNTN node (FIG. 1, labeled 8). The metal resistor 20 is comprised of lower metal portions 23 and upper metal portions 24 that are connected together by metal vias 25. Although the lower and upper metal portions 23 and 24 are not extremely high in resistance, the metal vias 25 provide very high resistance.

[0021] FIG. 4 is a top view of the metal resistor structure 20 shown in FIG. 3 without the lower metal portions 23. In FIG. 4, the lower metal portion is not shown in order to enable the arrangement of the structures 24 of the metal resistor in accordance with the example embodiment to be clearly illustrated. The structures 24 are arranged in a staggered configuration as shown. The interconnections between the individual resistive structures 24 are shown in FIG. 5.

[0022] FIG. 5 illustrates a top view of the EDS structure 40 of the present invention in accordance with the example embodiment, which illustrates the metal capacitor structure 41 and the metal resistor structure 42 interconnected through the SHUNTN metal line 43. In actuality, the ESD structure 40 shown in FIG. 5 represents only a small section of what the actual ESD structure would look like on an IC. The actual ESD structure would likely have many more metal lines 12 for the capacitor structure 41 and many more resistive structures 24 for the metal resistor 42.

[0023] In accordance with this example embodiment, the metal resistive structures 24 are connected in a “dog bone” configuration by the lower metal portions 23 (FIG. 3), which interconnect the vias 25 (FIGS. 3 and 4) of each resistive structure 24 to the vias 25 of the adjacent resistive structure 24. The vias 25 are shown in FIG. 5, but are not numbered due to the lack of space in FIG. 5 to label the vias 25 with numbers.

[0024] The configuration shown is being provided merely for the purposes of demonstrating one possible implementation of the metal resistor. However, it should be noted that the metal resistor of the present invention is not limited to any particular configuration, as will be understood by those skilled in the art in view of the present disclosure.

[0025] One of the vias of one of the resistive structures 24 that is furthermost from SHUNTN 43 will be connected to the VDD node (FIG. 1, labeled with numeral 2). One of the vias of a resistive structure 24 that is closer to SHUNTN 43 will be connected to SHUNTN 43. In FIG. 5, the lowest via that is closest to SHUNTN provides the conductive connection to SHUNTN.

[0026] It should be noted that the present invention is not limited to the configuration shown in FIG. 5. Those skilled in the art will understand the manner in which other ESD structure configurations can be derived from the concepts and examples provided herein. One modification that can be made to the ESD structure shown in FIG. 5 is that an additional metal resistor similar or identical to the metal resistor 42 can be placed in parallel with metal resistor 42. Doing this would provide redundancy that would further enhance the reliability of the EDS structure because if, for example, a section of the resistor 42 was damaged or simply was not created during the IC fabrication process, the additional metal resistor would still provide the resistance needed to provide a long RC time constant.

[0027] The necessary RC time constant of the ESD structure can vary without affecting the performance of the ESD structure. The only requirements on the RC time constant is that (1) it is long enough so that during an ESD event, PFET, p1, labeled with numeral 5 in FIG. 1, turns on to enable node 2 to discharge through NFET n2 to ground and (2) shorter than the normal amount of time that is required for the IC to power up so that powering up the IC does not look like an ESD event and cause the current associated with the power supply VDD to be shunted to ground through NFET n27. These requirements are not difficult to meet, which allows for variations in process conditions to occur without resulting in the creation of an ESD structure that is ineffective or unreliable.

[0028] The example embodiments of FIGS. 2-5 have been provided for the purpose of demonstrating the concepts and principles of the present invention, and for the purpose of demonstrating the manner in which the present invention can be implemented. Those skilled in the art will understand from the discussion provided herein that modifications can be made to the RC component described herein without deviating from the scope of the invention. Also, it should be noted that the RC component of the present invention can be used for purposes other than for an ESD structure. Those skilled in the art will understand that other modifications may be made to the embodiments discussed herein that are also within the scope of the present invention.