Fluorine-containing layers for damascene structures

[0002] 1. Field of the Invention

[0003] The present invention relates to silicon carbide layers, silicon nitride layers, and organosilicate layers and, more particularly to methods of forming silicon carbide layers, silicon nitride layers and organosilicate layers.

[0004] 2. Background of the Invention

[0005] Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demands for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.

[0006] As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. For example, low resistivity metal interconnects (e.g., aluminum and copper) provide conductive paths between the components on integrated circuits.

[0007] Typically, the metal interconnects are electrically isolated from each other by a bulk insulating material. When the distance between adjacent metal interconnects and/or the thickness of the bulk insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross-talk and/or resistance-capacitance (RC) delay, which degrades the overall performance of the integrated circuit.

[0008] In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 3.5) are needed. Typically, bulk insulating materials with dielectric constants less than about 3.5 are tensile materials (e.g., tensile stresses greater than about 10⁸dynes/cm²). Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO₂), silicate glass, and organosilicates, among others.

[0009] In addition, a low dielectric constant (low k) barrier layer often separates the metal interconnects from the bulk insulating materials. The barrier layer minimizes the diffusion of the metal from the interconnects into the bulk insulating material. Diffusion of the metal from the interconnects into the bulk insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit (e.g., cross-talk and/or RC delay), or render it inoperative.

[0010] The demands for greater integrated circuit densities also impose demands on the process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers on a substrate. Many of these underlying material layers are reflective to ultraviolet light. Such reflections can distort the dimensions of features such as lines and vias that are formed in the energy sensitive resist material.

[0011] One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist.

[0012] Silicon carbide (SiC) has been suggested for use as a barrier layer and/or ARC on integrated circuits, since silicon carbide layers can have a low dielectric constant (dielectric constant less than about 5.5), are good metal diffusion barriers and can have good light absorption properties. Silicon nitride has also been suggested as a barrier layer and/or ARC, since it also has good metal diffusion barrier and can have good light absorption properties.

[0013] Thus, there is an ongoing need for silicon carbide layers, silicon nitride layers, and organosilicate layers with low dielectric constants as well as improved film characteristics.

[0014] A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a fluorine source in the presence of an electric field.

[0015] A method of forming a silicon nitride layer for use in integrated circuit fabrication processes is provided. The silicon nitride layer is formed by reacting a gas mixture comprising a silicon source, a nitrogen source, and a fluorine source in the presence of an electric field.

[0016] A method of forming an organosilicate layer for use in integrated circuit fabrication processes is provided. The organosilicate layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, an oxygen source and a fluorine source in the presence of an electric field.

[0017] The silicon carbide layer, the silicon nitride layer and the organosilicate layer are all compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as both a hard mask and a barrier layer for fabricating integrated circuit structures such as, for example, a dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a silicon carbide barrier layer on a metal layer formed on a substrate. After the silicon carbide barrier layer is deposited on the substrate a first dielectric layer is formed thereon. A silicon carbide hard mask layer is formed on the first dielectric layer. The silicon carbide hard mask is patterned to define vias therein. Thereafter, a second dielectric layer is formed on the patterned silicon carbide hard mask layer. The second dielectric layer is patterned to define interconnects therein. The interconnects formed in the second dielectric layer are positioned over the vias defined in the silicon carbide hard mask layer. After the second dielectric layer is patterned, the vias defined in the silicon carbide hard mask layer are transferred into the first dielectric layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.

[0018] Alternatively, a silicon nitride layer may be used as both a hard mask and a barrier layer for fabricating the dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a silicon nitride barrier layer on a metal layer formed on a substrate. After the silicon nitride barrier layer is deposited on the substrate a first dielectric layer is formed thereon. A silicon nitride hard mask layer is formed on the first dielectric layer. The silicon nitride hard mask is patterned to define vias therein. Thereafter, a second dielectric layer is formed on the patterned silicon nitride hard mask layer. The second dielectric layer is patterned to define interconnects therein. The interconnects formed in the second dielectric layer are positioned over the vias defined in the silicon nitride hard mask layer. After the second dielectric layer is patterned, the vias defined in the silicon nitride hard mask layer are transferred into the first dielectric layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.

[0019] In another integrated circuit fabrication process, an organosilicate material may be used as the first and second dielectric layers in the dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a barrier layer on a metal layer formed on a substrate. After the barrier layer is deposited on the substrate a first organosilicate layer is formed thereon. A hard mask layer is formed on the first organosilicate layer. The hard mask is patterned to define vias therein. Thereafter, a second organosilicate layer is formed on the patterned hard mask layer. The second organosilicate layer is patterned to define interconnects therein. The interconnects formed in the second organosilicate layer are positioned over the vias defined in the hard mask layer. After the second organosilicate layer is patterned, the vias defined in the hard mask layer are transferred into the first organosilicate layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.

[0020] The silicon carbide layer, the silicon nitride layer, or the organosilicate may also function as an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. For such an embodiment, a preferred process sequence includes forming a silicon carbide layer (alternatively a silicon nitride layer or an organosilicate layer) on a substrate. The silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) has a refractive index (n) in a range of about 1.6 to about 2.2 and an absorption coefficient (κ) in a range of about 0.1 to about 0.9 at wavelengths less than about 250 nm (nanometers). The refractive index (n) and the absorption coefficient (κ) are tunable, in that they can be varied in the desired range as a function of the composition of the gas mixture during silicon carbide layer formation. After the silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) is formed on the substrate, a layer of energy sensitive resist material is formed thereon. A pattern is defined in the energy sensitive resist at a wavelength less than about 250 nm. Thereafter, the pattern defined in the energy sensitive resist material is transferred into the silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) and, optionally, into the substrate.

[0021] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0022] FIG. 1 depicts a schematic illustration of an apparatus that can be used for the practice of embodiments described herein;

[0023] FIGS. 2a-2eillustrate schematic cross-sectional views of a substrate structure at different stages of integrated circuit fabrication incorporating a silicon carbide layer as a hard mask;

[0024] FIGS. 3a-3eillustrate a schematic cross-sectional views of a substrate structure at different stages of integrated circuit fabrication incorporating a silicon nitride layer as a hard mask;

[0025] FIGS. 4a-4eillustrate schematic cross-sectional views of a substrate structure at different stages of integrated circuit fabrication incorporating a silicon carbide layer as an anti-reflective coating (ARC);

[0026] FIGS. 5a-5eillustrate schematic cross-sectional views of a substrate structure at different stages of integrated circuit fabrication incorporating a silicon nitride layer as an anti-reflective coating (ARC);

[0027] FIGS. 6a-6eillustrate schematic cross-sectional views of a substrate structure at different stages of integrated circuit fabrication incorporating an organosilicate layer as an anti-reflective coating (ARC);

[0028] FIGS. 7a-7gillustrate schematic cross-sectional views of a damascene structure at different stages of integrated circuit fabrication incorporating a silicon carbide layer as both a hard mask and a barrier layer;

[0029] FIGS. 8a-8gillustrate schematic cross-sectional views of a damascene structure at different stages of integrated circuit fabrication incorporating a silicon nitride layer as both a hard mask and a barrier layer; and

[0030] FIGS. 9a-9gillustrate schematic cross-sectional views of a damascene structure at different stages of integrated circuit fabrication incorporating organosilicate layers as the bulk insulating material layers.

[0031] FIG. 1 is a schematic representation of a wafer processing system 10 that can be used to perform silicon carbide layer, silicon nitride layer, and organosilicate layer deposition in accordance with embodiments described herein. System 10 typically comprises a process chamber 100, a gas panel 130, a control unit 110, along with other hardware components such as power supplies 119, 106 and vacuum pumps 102. Examples of wafer processing system 10 include plasma enhanced chemical vapor deposition (PECVD) chambers such as DXZ™ chambers, commercially available from Applied Materials Inc., located in Santa Clara, Calif.

[0032] Details of wafer processing system 10 are described in commonly assigned U.S. patent application Ser. No. 09/211,998, entitled “High Temperature Chemical Vapor Deposition Chamber”, filed on Dec. 14, 1998, and is herein incorporated by reference. The salient features of this system 10 are briefly described below.

[0033] The process chamber 100 generally houses a support pedestal 150, which is used to support a substrate such as a semiconductor wafer 190. This pedestal 150 can typically be moved in a vertical direction inside the chamber 100 using a displacement mechanism (not shown).

[0034] Depending on the specific process, the wafer 190 can be heated to some desired temperature prior to layer deposition. For example, referring to FIG. 1, the wafer support pedestal 150 is heated by an embedded heater element 170. The pedestal 150 may be resistively heated by applying an electric current from an AC power supply 106 to the heater element 170. The wafer 190 is, in turn, heated by the pedestal 190.

[0035] A temperature sensor 172, such as a thermocouple, may also be embedded in the wafer support pedestal 150 to monitor the temperature of the pedestal in a conventional manner. The measured temperature can be used in a feedback loop to control the power supplied to the heater element 170, such that the wafer temperature can be maintained or controlled at a desired temperature which is suitable for the particular process application. The pedestal may optionally be heated using radiant heat (not shown).

[0036] A vacuum pump 102, is used to evacuate the process chamber 100 and to maintain the proper gas flows and pressure inside the chamber 100. A showerhead 120, through which process gases are introduced into the chamber 100, is located above the wafer support pedestal 150. The showerhead 120 is connected to a gas panel 130, which controls and supplies various gases used in different steps of the process sequence.

[0037] The showerhead 120 and wafer support pedestal 150 also form a pair of spaced apart electrodes. When an electric field is generated between these electrodes, the process gases introduced into the chamber 100 are ignited into a plasma. The electric field is generated by connecting the showerhead 120 to a source of radio frequency (RF) power (not shown) through a matching network (not shown). Alternatively, the RF power source and the matching network may be coupled to both the showerhead 120 and the wafer support pedestal 150.

[0038] The electric filed may optionally be generated by coupling the showerhead 120 to a source of mixed radio frequency (RF) power 119. Details of the mixed RF power source 119 are described in commonly assigned U.S. Pat. No. 6,041,734, entitled, “Use of an Asymmetric Waveform to Control Ion Bombardment During Substrate Processing”, issued Mar. 28, 2000, and is herein incorporated by reference.

[0039] Typically, the source of mixed RF power 119 under the control of a controller unit 110 provides a high frequency power (e.g., RF power in a range of about 10 MHz to about 15 MHz) as well as a low frequency power (e.g., RF power in a range of about 150 KHz to about 450 KHz) to the showerhead 120. Both the high frequency RF power and the low frequency RF power may be coupled to the showerhead 120 through a matching network (not shown). The high frequency RF power source and the low frequency RF power source may optionally be coupled to the wafer support pedestal 150, or alternatively one may be coupled to the showerhead 120 and the other may be coupled to the wafer support pedestal 150.

[0040] Plasma enhanced chemical vapor deposition (PECVD) techniques promote excitation and/or disassociation of the reactant gases by the application of the electric field to a reaction zone 195 near the substrate surface, creating a plasma of reactive species. The reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, in effect lowering the required temperature for such PECVD processes.

[0041] Proper control and regulation of the gas flows through the gas panel 130 is performed by mass flow controllers (not shown) and the controller unit 110. The showerhead 120 allows process gases from the gas panel 130 to be uniformly introduced and distributed in the process chamber 100.

[0042] Illustratively, the control unit 110 comprises a central processing unit (CPU) 113, as well as support circuitry 114, and memories containing associated control software 116. The control unit 110 is responsible for automated control of the numerous steps required for wafer processing—such as wafer transport, gas flow control, mixed RF power control, temperature control, chamber evacuation, and other steps. Bi-directional communications between the control unit 110 and the various components of the wafer processing system 10 are handled through numerous signal cables collectively referred to as signal buses 118, some of which are illustrated in FIG. 1.

[0043] The central processing unit (CPU) 113 may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling process chambers as well as sub-processors. The computer may use any suitable memory, such as random access memory, read only memory, floppy disk drive, hard drive, or any other form of digital storage, local or remote. Various support circuits may be coupled to the CPU for supporting the processor in a conventional manner. Process sequence routines as required may be stored in the memory or executed by a second CPU that is remotely located.

[0044] The process sequence routines are executed after the substrate 190 is positioned on the wafer support pedestal 150. The process sequence routines, when executed, transform the general purpose computer into a specific process computer that controls the chamber operation so that the deposition process is performed. Alternatively, the chamber operation may be controlled using remotely located hardware, as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware.

[0045] A silicon carbide layer is formed by reacting a gas mixture including a silicon source, a carbon source, and a fluorine source. The silicon source may be an organosilane compound. Suitable organosilane compounds may have the general formula Si_xC_yH_z, where x has a range from 1 to 2, y has a range from 1 to 6, and z has a range from 4 to 18. For example, methylsilane (SiCH₆), dimethylsilane (SiC₂H₈), trimethylsilane (SiC₃H₁₀), tetramethylsilane (SiC₄H₁₂), and diethylsilane (SiC₄H₁₂), among others may be used as the organosilane compound. Alternatively, silane (SiH₄), disilane (Si₂H₆), methane (CH₄), and combinations thereof, may be used as the silicon source and the carbon source.

[0046] Carbon tetrafluoride (CF₄), fluoroethane (C₂F₆), trifluoromethane (CHF₃), difluoromethane (CH₂F₂), and nitrogen fluoride (NF₃), or combinations thereof, among others may be used for the fluorine source.

[0047] The gas mixture may further comprise an inert gas. Helium (He), argon (Ar), neon (Ne), or combination thereof, among others, may be used for the inert gas.

[0048] In general, the following deposition process parameters can be used to form the silicon carbide layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a wafer temperature of about 150° C. to about 450° C., a chamber pressure of about 1 torr to about 15 torr, a silicon source and/or carbon source flow rate of about 10 sccm to about 2000 sccm, a fluorine source flow rate of about 50 sccm to about 10,000 sccm, an inert gas flow rate of less than about 1000 sccm, a plate spacing of about 300 mils to about 600 mils, and an RF power of about 1 watt/cm²to about 10 watts/cm²(for either of the single or mixed frequency RF powers). Additionally, the ratio of the silicon source to the fluorine source in the gas mixture should have a range of about 1:1 to about 1:100. The above process parameters provide a deposition rate for the silicon carbide layer in a range of about 100 Å/min to about 3000 Å/min when implemented on a 200 mm (millimeter) substrate in a deposition chamber available from Applied Materials, Inc., located in Santa Clara, Calif.

[0049] Other deposition chambers are within the scope of the invention, and the parameters listed above may vary according to the particular deposition chamber used to form the silicon carbide layer. For example, other deposition chambers may have a larger (e.g., configured to accommodate 300 mm substrates) or smaller volume, requiring gas flow rates that are larger or smaller than those recited for deposition chambers available from Applied Materials Inc., Santa Clara, Calif.

[0050] Some fluorine from the fluorine source may be incorporated into the silicon carbide layer during layer formation. Such incorporation is believed to reduce the dielectric constant thereof, such that is less than about 5.5, making it suitable for use as a barrier material in integrated circuits. The dielectric constant of the silicon carbide layer may be varied as a function of the composition of the gas mixture during layer formation. As the fluorine (F) and/or carbon (C) concentration in the gas mixture increases, the F and/or C content of the silicon carbide layer increases, decreasing its dielectric constant. In addition, as the F content of the silicon carbide layer increases the etch rate thereof similarly increases. Also, as the C content of the silicon carbide layer increases the hydrophobic properties thereof increase, making such layer suitable for use as moisture barriers in integrated circuits.

[0051] The dielectric constant of the silicon carbide layer may also be varied as a function of the RF power. In particular, as the RF power is increased the dielectric constant of the as-deposited silicon carbide layer also increases.

[0052] The silicon carbide layer also has a light absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at DUV wavelengths. The absorption coefficient (κ) of the silicon carbide layer may be varied as a function of the composition of the gas mixture. In particular, as the concentration of the carbon source is increased, the absorption coefficient (κ) of the as-deposited silicon carbide layer likewise increases.

[0053] After the silicon carbide layer is formed, it may be plasma treated with an inert gas. Helium (He), argon (Ar), neon (Ne), and combinations thereof, may be used for the inert gas. Such plasma treatment is believed to stabilize the layer, such that it becomes less reactive with moisture and/or oxygen under atmospheric condition as well as to improve the adhesion of layers formed thereover.

[0054] In general, the following process parameters can be used to plasma treat the silicon carbide layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a chamber pressure of about 5 torr to about 10 torr, an inert gas flow rate of about 1000 sccm to about 7000 sccm, and a radio frequency (RF) power of about 1 watt/cm²to about 10 watts/cm². The silicon carbide layer is plasma treated for less than about 1000 seconds.

[0055] A silicon nitride layer is formed by reacting a gas mixture including a silicon source, a nitrogen source, and a fluorine source. The silicon source may be silane (SiH₄) and disilane (Si₂H₆), trisilane (Si₃H₈), tetrasilane (Si₄H₁₀), and combinations thereof, among others. Ammonia (NH₃), nitrogen (N₂), and combinations thereof, among others may be used as the nitrogen source.

[0056] Carbon tetrafluoride (CF₄), fluoroethane (C₂F₆), trifluoromethane (CHF₃), difluoromethane (CH₂F₂), and nitrogen fluoride (NF₃), or combinations thereof, among others may be used for the fluorine source.

[0057] The gas mixture may further comprise an inert gas. Helium (He), argon (Ar), neon (Ne), or combination thereof, among others, may be used for the inert gas.

[0058] In general, the following deposition process parameters can be used to form the silicon nitride layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a wafer temperature of about 200° C. to about 600° C., a chamber pressure of about 1 torr to about 20 torr, a silicon source flow rate of about 50 sccm to about 500 sccm, a nitrogen source flow rate of about 10 sccm to about 300 sccm, a fluorine source flow rate of about 1 sccm to about 10,000 sccm, an inert gas flow rate of less than about 10000 sccm, a plate spacing of about 300 mils to about 600 mils, and an RF power of about 1 watt/cm²to about 10 watts/cm²(for either of the single or mixed frequency RF powers). Additionally, the ratio of the silicon source to the fluorine source in the gas mixture should have a range of about 1:1 to about 1:100. The above process parameters provide a deposition rate for the silicon nitride layer in a range of about 100 Å/min to about 10000 Å/min when implemented on a 200 mm (millimeter) substrate in a deposition chamber available from Applied Materials, Inc., located in Santa Clara, Calif.

[0059] Other deposition chambers are within the scope of the invention, and the parameters listed above may vary according to the particular deposition chamber used to form the silicon nitride layer. For example, other deposition chambers may have a larger (e.g., configured to accommodate 300 mm substrates) or smaller volume, requiring gas flow rates that are larger or smaller than those recited for deposition chambers available from Applied Materials Inc., Santa Clara, Calif.

[0060] Some fluorine from the fluorine source may be incorporated into the silicon nitride layer during layer formation. Such incorporation is believed to reduce the dielectric constant thereof, such that is less than about 7, making it suitable for use as a barrier material in integrated circuits.

[0061] The dielectric constant of the silicon nitride layer may be varied as a function of the composition of the gas mixture during layer formation. As the fluorine (F) and/or silicon (Si) concentration in the gas mixture increases, the F and/or Si content of the silicon nitride layer increases, decreasing its dielectric constant. In addition, as the F content of the silicon nitride layer increases the etch rate thereof similarly increases. Also, as the nitrogen (N) content of the silicon nitride layer increases the hydrophobic properties thereof increase, making such layer suitable for use as moisture barriers in integrated circuits.

[0062] The dielectric constant of the silicon nitride layer may also be varied as a function of the RF power. In particular, as the RF power is increased the dielectric constant of the as-deposited silicon nitride layer also increases.

[0063] The silicon nitride layer also has a light absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at DUV wavelengths. The absorption coefficient (κ) of the silicon nitride layer may be varied as a function of the composition of the gas mixture. In particular, as the concentration of the silicon source is increased, the absorption coefficient (κ) of the as-deposited layer likewise increases.

[0064] After the silicon nitride layer is formed, it may be plasma treated with an inert gas. Helium (He), argon (Ar), neon (Ne), and combinations thereof, may be used for the inert gas. Such plasma treatment is believed to stabilize the layer, such that it becomes less reactive with moisture and/or oxygen under atmospheric condition as well as to improve the adhesion of layers formed thereover.

[0065] In general, the following process parameters can be used to plasma treat the silicon nitride layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a chamber pressure of about 5 torr to about 10 torr, an inert gas flow rate of about 1000 sccm to about 7000 sccm, and a radio frequency (RF) power of about 1 watt/cm²to about 10 watts/cm². The silicon nitride layer is plasma treated for less than about 1000 seconds.

[0066] An organosilicate layer is formed by reacting a gas mixture including a silicon source, a carbon source, an oxygen source, and a fluorine source. The silicon source may be an organosilane compound. Suitable organosilane compounds may have the general formula Si_xC_yH_z, where x has a range from 1 to 2, y has a range from 1 to 6, and z has a range from 4 to 18. For example, methylsilane (SiCH₆), dimethylsilane (SiC₂H₈), trimethylsilane (SiC₃H₁₀), tetramethylsilane (SiC₄H₁₂), bis(methylsilano)methane (Si₂C₃H₁₂), 1,2-bis(methylsilano)ethane (Si₂C₄H₁₄), and diethylsilane (SiC₄H₁₂), among others may be used as the organosilane compound. Silane (SiH₄), disilane (Si₂H₆), methane (CH₄), and combinations thereof, may also be used as the silicon source and the carbon source.

[0067] Alternatively, the organosilane compound may have the general formula Si_aC_bH_cO_d, where a has a range from 1 to 2, b has a range from 1 to 10, c has a range from 6 to 30, and d has a range from 1 to 6. For example, methoxysilane (SiCH₆O), dimethyldimethoxysilane (SiC₄H₁₂O₂), diethyldiethoxysilane (SiC₈H₂₀O₂), dimethyldiethoxysilane (SiC₆H₁₆O₂), diethyldimethoxysilane (SiC₆H₁₆O₂), and hexamethyldisiloxane (Si₂C₆H₁₈O), among others are also suitable organosilane compounds.

[0068] Oxygen (O₂), ozone (O₃), nitrous oxide (N₂O), carbon monoxide (CO), carbon dioxide (CO₂), or combinations thereof, among others, may be used for the carbon source.

[0069] Carbon tetrafluoride (CF₄), fluoroethane (C₂F₆), trifluoromethane (CHF₃), difluoromethane (CH₂F₂), and nitrogen fluoride (NF₃), or combinations thereof, among others may be used for the fluorine source.

[0070] The gas mixture may optionally include an inert gas. Helium (He), argon (Ar), neon (Ne), and xenon (Xe), as well as combinations thereof, among others, may be used for the inert gas.

[0071] In general, the following deposition process parameters can be used to form the organosilicate layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a wafer temperature of about 50° C. to about 500° C., a chamber pressure of about 1 torr to about 500 torr, a silicon source and/or carbon source flow rate of about 10 sccm to about 2,000 sccm, an oxygen source flow rate of about 10 sccm to about 200 sccm, a fluorine source flow rate of about 15 sccm to about 10,000 sccm, an inert gas flow rate of about 10 sccm to about 1,000 sccm, a plate spacing of about 300 mils to about 600 mils, and an RF power of about 1 watt/cm²to about 500 watts/cm²(for either of the single or mixed frequency RF powers). The above process parameters provide a deposition rate for the organosilicate layer in the range of about 0.1 microns/minute to about 2 microns/minute when implemented on a 200 mm (millimeter) substrate in a deposition chamber available from Applied Materials, Inc., Santa Clara, Calif.

[0072] Other deposition chambers are within the scope of the invention, and the parameters listed above may vary according to the particular deposition chamber used to form the organosilicate layer. For example, other deposition chambers may have a larger (e.g., configured to accommodate 300 mm substrates) or smaller volume, requiring gas flow rates that are larger or smaller than those recited for deposition chambers available from Applied Materials, Inc., Santa Clara, Calif.

[0073] Some fluorine from the fluorine source may be incorporated into the organosilicate layer during layer formation. Such incorporation is believed to reduce the dielectric constant thereof, such that is less than about 3.5, making it suitable for use as a dielectric material in integrated circuits. The dielectric constant of the organosilicate layer may be varied as a function of the composition of the gas mixture during layer formation. As the fluorine (F) and/or carbon (C) concentration in the gas mixture increases, the F and/or C content of the organosilicate layer increases, decreasing its dielectric constant. In addition, as the F content of the organosilicate layer increases the etch rate thereof similarly increases. Also, as the C content of the organosilicate layer increases the hydrophobic properties thereof increase, making such layer suitable for use as moisture barriers in integrated circuits.

[0074] The dielectric constant of the organosilicate layer may also be varied as a function of the RF power. In particular, as the RF power is increased the dielectric constant of the as-deposited organosilicate layer also increases.

[0075] The organosilicate layer also has a light absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at DUV wavelengths. The absorption coefficient (κ) of the organosilicate layer may be varied as a function of the composition of the gas mixture. In particular, as the concentration of the carbon source is increased, the absorption coefficient (κ) of the as-deposited layer likewise increases.

[0076] After the organosilicate layer is formed, it is treated with a plasma comprising an inert gas. For example, helium (He), argon (Ar), nitrogen (N₂), and combinations thereof, among others, may be used for the inert gas.

[0077] In general, the following process parameters may be used to plasma treat the organosilicate layer in a process chamber similar to that shown in FIG. 1. The process parameters range from a wafer temperature of about 50° C. to about 400° C., a chamber pressure of about 1 torr to about 10 torr, an inert gas flow rate of about 500 sccm to about 5,000 sccm, and a radio frequency (RF) power of about 1 watt/cm²to about 10 watts/cm². The organosilicate layer is plasma treated with the inert gas for less than about 1000 seconds.

[0078] The plasma treatment improves the adhesion of overlying material layers to the organosilicate layer. It is believed that the fracture strength of plasma treated organosilicate layers is greater than that of untreated organosilicate layers, minimizing cracking of the treated organosilicate layer so as to improve the adhesion of material layers thereto.

[0079] FIGS. 2a-2eillustrate schematic cross-sectional views of a substrate 200 at different stages of an integrated circuit fabrication sequence incorporating a silicon carbide layer as a hard mask. In general, the substrate 200 refers to any workpiece on which processing is performed, and a substrate structure 250 is used to generally denote the substrate together with other material layers formed on the substrate 200. Depending on the specific stage of processing, the substrate 200 may correspond to a silicon wafer, or other material layer that has been formed on the silicon wafer. FIG. 2a, for example, illustrates a cross-sectional view of a substrate structure 250, having a material layer 202 that has been conventionally formed thereon. The material layer 202 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). In general, the substrate 200 may include a layer of silicon, silicides, metals, or other materials. FIG. 2aillustrates one embodiment in which the substrate 200 is silicon having a silicon dioxide layer formed thereon.

[0080] FIG. 2bdepicts a silicon carbide layer 204 formed on the substrate structure 250 of FIG. 2a. The silicon carbide layer 204 is formed on the substrate structure 250 according to the process parameters described above. The thickness of the silicon carbide layer is variable depending on the specific stage of processing. Typically, the silicon carbide layer is deposited to a thickness of about 50 Å to about 1000 Å.

[0081] A layer of energy sensitive resist material 208 is formed on the silicon carbide layer 204. The layer of energy sensitive resist material 208 may be spin coated on the substrate to a thickness of within a range of about 4,000 Å to about 10,000 Å. Most energy sensitive resist materials are sensitive to ultraviolet (UV) radiation having a wavelength less than about 450 nm (nanometers). Deep ultraviolet (DUV) resist materials are sensitive to UV radiation having wavelengths less than about 250 nm.

[0082] Dependent on the etch chemistry of the energy sensitive resist material used in the fabrication sequence, an intermediate layer 206 may be formed on the silicon carbide layer 204. When the energy sensitive resist material 208 and the silicon carbide layer 204 can be etched using the same chemical etchants or when resist poisoning may occur, the intermediate layer 206 functions as a mask for the silicon carbide layer 204. The intermediate layer 206 is conventionally formed on the silicon carbide layer 204. The intermediate layer 206 may be a silicon carbide cap layer, an oxide, amorphous silicon, or other suitable material layer.

[0083] An image of a pattern is introduced into the layer of energy sensitive resist material 208 by exposing such energy sensitive resist material 208 to UV radiation via mask 210. The image of the pattern introduced into the layer of energy sensitive resist material 208 is developed in an appropriate developer to define the pattern therethrough, as shown in FIG. 2c. Thereafter, referring to FIG. 2d, the pattern defined in the energy sensitive resist material 208 is transferred through the silicon carbide layer 204. The pattern is transferred through the silicon carbide layer 204 using the energy sensitive resist material 208 as a mask. The pattern is transferred through the silicon carbide layer 204 using an appropriate chemical etchant. For example, fluorocarbon compounds such as trifluoromethane (CF₃H) may be used to chemically etch the silicon carbide layer 204.

[0084] Alternatively, when the intermediate layer 206 is present, the pattern defined in the energy sensitive resist material 208 is first transferred through the intermediate layer 206 using the energy sensitive resist material as a mask. Thereafter, the pattern is transferred through the silicon carbide layer 204 using the intermediate layer 206 as a mask. The pattern is transferred through both the intermediate layer 206 as well as the silicon carbide layer 204 using appropriate chemical etchants.

[0085] FIG. 2eillustrates the completion of the integrated circuit fabrication sequence by the transfer of the pattern defined in the silicon carbide layer 204 through the silicon dioxide layer 202 using the silicon carbide layer 204 as a hard mask. After the silicon dioxide layer 202 is patterned, the silicon carbide layer 204 can optionally be stripped from the substrate 200 by etching it in a suitable chemical etchant.

[0086] FIGS. 3a-3eillustrate schematic cross-sectional views of a substrate 300 at different stages of an integrated circuit fabrication sequence incorporating a silicon nitride layer as a hard mask. In general, the substrate 300 refers to any workpiece on which processing is performed, and a substrate structure 350 is used to generally denote the substrate together with other material layers formed on the substrate 300. Depending on the specific stage of processing, the substrate 300 may correspond to a silicon wafer, or other material layer that has been formed on the silicon wafer. FIG. 3a, for example, illustrates a cross-sectional view of a substrate structure 350, having a material layer 302 that has been conventionally formed thereon. The material layer 302 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). In general, the substrate 300 may include a layer of silicon, silicides, metals, or other materials. FIG. 3aillustrates one embodiment in which the substrate 300 is silicon having a silicon dioxide layer formed thereon.

[0087] FIG. 3bdepicts a silicon nitride layer 304 formed on the substrate structure 350 of FIG. 3a. The silicon nitride layer 304 is formed on the substrate structure 350 according to the process parameters described above. The thickness of the silicon nitride layer is variable depending on the specific stage of processing. Typically, the silicon nitride layer is deposited to a thickness of about 50 Å to about 1000 Å.

[0088] A layer of energy sensitive resist material 308 is formed on the silicon nitride layer 304. The layer of energy sensitive resist material 308 may be spin coated on the substrate to a thickness of within a range of about 4,000 Å to about 10,000 Å. Most energy sensitive resist materials are sensitive to ultraviolet (UV) radiation having a wavelength less than about 450 nm (nanometers). Deep ultraviolet (DUV) resist materials are sensitive to UV radiation having wavelengths less than about 250 nm.

[0089] Dependent on the etch chemistry of the energy sensitive resist material used in the fabrication sequence, an intermediate layer 306 may be formed on the silicon nitride layer 304. When the energy sensitive resist material 308 and the silicon nitride layer 304 can be etched using the same chemical etchants or when resist poisoning may occur, the intermediate layer 306 functions as a mask for the silicon nitride layer 304. The intermediate layer 306 is conventionally formed on the silicon nitride layer 304. The intermediate layer 306 may be a silicon carbide cap layer, an oxide, amorphous silicon, or other suitable material layer.

[0090] An image of a pattern is introduced into the layer of energy sensitive resist material 308 by exposing such energy sensitive resist material 308 to UV radiation via mask 310. The image of the pattern introduced into the layer of energy sensitive resist material 308 is developed in an appropriate developer to define the pattern therethrough, as shown in FIG. 3c. Thereafter, referring to FIG. 3d, the pattern defined in the energy sensitive resist material 308 is transferred through the silicon nitride layer 304. The pattern is transferred through the silicon nitride layer 304 using the energy sensitive resist material 308 as a mask. The pattern is transferred through the silicon nitride layer 304 using an appropriate chemical etchant. For example, fluorocarbon compounds such as trifluoromethane (CF₃H) may be used to chemically etch the silicon nitride layer 304.

[0091] Alternatively, when the intermediate layer 306 is present, the pattern defined in the energy sensitive resist material 308 is first transferred through the intermediate layer 306 using the energy sensitive resist material as a mask. Thereafter, the pattern is transferred through the silicon nitride layer 304 using the intermediate layer 306 as a mask. The pattern is transferred through both the intermediate layer 306 as well as the silicon nitride layer 304 using appropriate chemical etchants.

[0092] FIG. 3eillustrates the completion of the integrated circuit fabrication sequence by the transfer of the pattern defined in the silicon nitride layer 304 through the silicon dioxide layer 302 using the silicon nitride layer 304 as a hard mask. After the silicon dioxide layer 302 is patterned, the silicon nitride layer 204 may optionally be stripped from the substrate 200 by etching it in a suitable chemical etchant.

[0093] FIGS. 4a-4eillustrate schematic cross-sectional views of a substrate 400 at different stages of an integrated circuit fabrication sequence incorporating a silicon carbide layer as an anti-reflective coating (ARC). In general, the substrate 400 refers to any workpiece on which film processing is performed, and a substrate structure 450 is used to generally denote the substrate together with other material layers formed on the substrate 400. Depending on the specific stage of processing, substrate 400 may correspond to a silicon wafer or other material layer, which has been formed on the substrate 400. FIG. 4a, for example, illustrates a cross-sectional view of a substrate structure 450 in which the substrate 400 is a silicon wafer having an oxide layer thereon.

[0094] A silicon carbide layer 402 is formed on the substrate structure 450. The silicon carbide layer 402 is formed on the substrate structure 450 according to the process parameters described above. The silicon carbide layer 402 has an absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below about 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at deep ultraviolet (DUV) wavelengths. The absorption coefficient (κ) of the silicon carbide layer 402 is tunable, in that it can be varied in the desired range as a function of the gas composition (e.g., carbon source concentration). The thickness of the silicon carbide layer 402 is variable depending on the specific stage of processing. Typically, the silicon carbide layer 402 has a thickness of about 200 Å to about 2,000 Å.

[0095] FIG. 4bdepicts a layer of energy sensitive resist material 404 formed on the substrate structure 450 of FIG. 4a. The layer of energy sensitive resist material 404 can be spin coated on the substrate structure 450 to a thickness within a range of about 2,000 Å to about 6,000 Å. The energy sensitive resist material 404 is sensitive to DUV radiation having a wavelength less than 250 nm.

[0096] An image of a pattern is introduced into the layer of energy sensitive resist material 404 by exposing such layer to DUV radiation via mask 406. When the image of the pattern is introduced into the layer of energy sensitive resist material 404, the silicon carbide layer 402 suppresses any reflections off underlying material layers (e.g., oxides, metals) which can degrade the image of the pattern introduced in the layer of energy sensitive resist material 404.

[0097] The image of the pattern introduced into the layer of energy sensitive resist material 404 is developed in an appropriate developer to define the pattern through such layer, as shown in FIG. 4c. Thereafter, referring to FIG. 4d, the pattern defined in the energy sensitive resist material 404 is transferred through the silicon carbide layer 402. The pattern is transferred through the silicon carbide layer 402 using the energy sensitive resist material mask. The pattern is transferred through the silicon carbide layer 402 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0098] After the silicon carbide layer 402 is patterned, such pattern is typically transferred into the substrate 400, as shown in FIG. 4e. The pattern is transferred into the substrate 400 using the silicon carbide ARC layer 402 as a hard mask. The pattern is transferred into the substrate 400 by etching it using an appropriate chemical etchant. Thereafter, the silicon carbide ARC layer 402 is optionally removed from the substrate structure 450 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0099] FIGS. 5a-5eillustrate schematic cross-sectional views of a substrate 500 at different stages of an integrated circuit fabrication sequence incorporating a silicon nitride layer as an anti-reflective coating (ARC). In general, the substrate 500 refers to any workpiece on which film processing is performed, and a substrate structure 550 is used to generally denote the substrate together with other material layers formed on the substrate 500. Depending on the specific stage of processing, substrate 500 may correspond to a silicon wafer or other material layer, which has been formed on the substrate 500. FIG. 5a, for example, illustrates a cross-sectional view of a substrate structure 550 in which the substrate 500 is a silicon wafer having an oxide layer thereon.

[0100] A silicon nitride layer 502 is formed on the substrate structure 550. The silicon nitride layer 502 is formed on the substrate structure 550 according to the process parameters described above. The silicon nitride layer 502 has an absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below about 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at deep ultraviolet (DUV) wavelengths. The absorption coefficient (κ) of the silicon nitride layer 502 is tunable, in that it can be varied in the desired range as a function of the gas composition (e.g., silicon source concentration). The thickness of the silicon nitride layer 502 is variable depending on the specific stage of processing. Typically, the silicon nitride layer 502 has a thickness of about 200 Å to about 2,000 Å.

[0101] FIG. 5bdepicts a layer of energy sensitive resist material 504 formed on the substrate structure 550 of FIG. 5a. The layer of energy sensitive resist material 504 can be spin coated on the substrate structure 550 to a thickness within a range of about 2,000 Å to about 6,000 Å. The energy sensitive resist material 504 is sensitive to DUV radiation having a wavelength less than 250 nm.

[0102] An image of a pattern is introduced into the layer of energy sensitive resist material 504 by exposing such layer to DUV radiation via mask 506. When the image of the pattern is introduced into the layer of energy sensitive resist material 504, the silicon nitride layer 502 suppresses any reflections off underlying material layers (e.g., oxides, metals) which can degrade the image of the pattern introduced in the layer of energy sensitive resist material 504.

[0103] The image of the pattern introduced into the layer of energy sensitive resist material 504 is developed in an appropriate developer to define the pattern through such layer, as shown in FIG. 5c. Thereafter, referring to FIG. 5d, the pattern defined in the energy sensitive resist material 504 is transferred through the silicon nitride layer 502. The pattern is transferred through the silicon nitride layer 502 using the energy sensitive resist material 504 as a mask. The pattern is transferred through the silicon nitride layer 502 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0104] After the silicon nitride layer 502 is patterned, such pattern is typically transferred into the substrate 500, as shown in FIG. 5e. The pattern is transferred into the substrate 500 using the silicon nitride ARC layer 502 as a hard mask. The pattern is transferred into the substrate 500 by etching it using an appropriate chemical etchant. Thereafter, the silicon nitride ARC layer 502 is optionally removed from the substrate structure 550 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0105] FIGS. 6a-6eillustrate schematic cross-sectional views of a substrate 600 at different stages of an integrated circuit fabrication sequence incorporating an organosilicate layer as an anti-reflective coating (ARC). In general, the substrate 600 refers to any workpiece on which film processing is performed, and a substrate structure 650 is used to generally denote the substrate together with other material layers formed on the substrate 600. Depending on the specific stage of processing, substrate 600 may correspond to a silicon wafer or other material layer, which has been formed on the substrate 600. FIG. 6a, for example, illustrates a cross-sectional view of a substrate structure 650 in which the substrate 600 is a silicon wafer having an oxide layer thereon.

[0106] An organosilicate layer 602 is formed on the substrate structure 650. The organosilicate layer 602 is formed on the substrate structure 650 according to the process parameters described above. The organosilicate layer 602 has an absorption coefficient (κ) that can be varied between about 0.1 to about 0.9 at wavelengths below about 250 nm (nanometers), making it suitable for use as an anti-reflective coating (ARC) at deep ultraviolet (DUV) wavelengths. The absorption coefficient (κ) of the organosilicate layer 602 is tunable, in that it can be varied in the desired range as a function of the gas composition (e.g., carbon source concentration). The thickness of the organosilicate layer 602 is variable depending on the specific stage of processing. Typically, the organosilicate layer 602 has a thickness of about 200 Å to about 2,000 Å.

[0107] FIG. 6bdepicts a layer of energy sensitive resist material 604 formed on the substrate structure 650 of FIG. 6a. The layer of energy sensitive resist material 604 can be spin coated on the substrate structure 650 to a thickness within a range of about 2,000 Å to about 6,000 Å. The energy sensitive resist material 604 is sensitive to DUV radiation having a wavelength less than 250 nm.

[0108] An image of a pattern is introduced into the layer of energy sensitive resist material 604 by exposing such layer to DUV radiation via mask 606. When the image of the pattern is introduced into the layer of energy sensitive resist material 604, the organosilicate layer 602 suppresses any reflections off underlying material layers (e.g., oxides, metals) which can degrade the image of the pattern introduced in the layer of energy sensitive resist material 604.

[0109] The image of the pattern introduced into the layer of energy sensitive resist material 604 is developed in an appropriate developer to define the pattern through such layer, as shown in FIG. 6c. Thereafter, referring to FIG. 6d, the pattern defined in the energy sensitive resist material 604 is transferred through the organosilicate layer 602. The pattern is transferred through the organosilicate layer 602 using the energy sensitive resist material 604 as a mask. The pattern is transferred through the organosilicate layer 602 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0110] After the organosilicate layer 602 is patterned, such pattern is typically transferred into the substrate 600, as shown in FIG. 6e. The pattern is transferred into the substrate 600 using the organosilicate ARC layer 602 as a hard mask. The pattern is transferred into the substrate 600 by etching it using an appropriate chemical etchant. Thereafter, the organosilicate ARC layer 602 is optionally removed from the substrate structure 650 by etching it using an appropriate chemical etchant (e.g., trifluoromethane (CF₃H)).

[0111] FIGS. 7a-7gillustrate schematic cross-sectional views of a substrate 700 at different stages of a dual damascene structure fabrication sequence incorporating a silicon carbide barrier layer as well as a silicon carbide hard mask. Dual damascene structures are typically used to form multi-layer metal interconnects on integrated circuits. Depending on the specific stage of processing, substrate 700 may correspond to a silicon wafer, or other material layer that has been formed on the substrate 700. FIG. 7a, for example, illustrates a cross-sectional view of a substrate 700 having a metal layer 702 (e.g., copper (Cu), aluminum (Al), tungsten (W)) formed thereon.

[0112] FIG. 7aillustrates one embodiment in which the substrate 700 is silicon having a copper (Cu) layer formed thereon. The copper layer 702 has a thickness of about 5,000 Å to about 5 microns, depending on the size of the structure to be fabricated.

[0113] Referring to FIG. 7b, a silicon carbide barrier layer 704 is formed on the copper layer 702. The silicon carbide barrier layer 704 is formed on the copper layer 702 according to the process parameters described above. The silicon carbide barrier layer 704 has a dielectric constant less than about 5.5. The dielectric constant can be varied as a function of the gas composition (e.g., fluorine source concentration and/or carbon source concentration) during layer formation. The thickness of the silicon carbide barrier layer 704 is variable depending on the specific stage of processing. Typically, the silicon carbide barrier layer 704 has a thickness of about 200 Å to about 1,000 Å.

[0114] A first dielectric layer 705 is formed on the silicon carbide barrier layer 704, as illustrated in FIG. 7c. The first dielectric layer 705 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). The first dielectric layer 705 has a thickness of about 5,000 Å to about 10,000 Å.

[0115] Referring to FIG. 7d, a silicon carbide hard mask layer 706 is formed on the first dielectric layer 705, patterned and etched to defined vias therein. The silicon carbide hard mask layer 706 is formed on the first dielectric layer 705 according to the process parameters described above. The silicon carbide hard mask layer 705 has a dielectric constant less than about 5.5. The dielectric constant of the silicon carbide hard mask layer can be varied as a function of the gas composition (e.g., fluorine source concentration and/or carbon source concentration) during layer formation.

[0116] The thickness of the silicon carbide hard mask layer 706 is variable depending on the specific stage of processing. Typically, the silicon carbide hard mask layer 706 has a thickness of about 200 Å to about 1,000 Å.

[0117] Referring to FIG. 7e, after the silicon carbide hard mask layer 706 is patterned, a second dielectric layer 708 is deposited thereover. The second dielectric layer 708 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). The thickness of the second dielectric layer 708 is variable depending on the specific stage of processing. Typically, the second dielectric layer 708 has a thickness of about 5,000 Å to about 10,000 Å.

[0118] The second dielectric layer 708 is then patterned to define interconnect lines 710, as illustrated in FIG. 7f, preferably using conventional lithography processes described above. The interconnect lines 710 formed in the second dielectric layer 708 are positioned over the via openings 706H formed in the silicon carbide hard mask layer 706. Thereafter, as shown in FIG. 7g, the vias 706H are transferred through the first dielectric layer 704 and the barrier layer 704 by etching them using reactive ion etching or other anisotropic etching techniques.

[0119] The interconnect lines 710 and the vias 706H are filled with a conductive material 714 such as aluminum (Al), copper (Cu), tungsten (W), or combinations thereof. Preferably copper (Cu) is used to fill the interconnect lines 710 and the vias 706H due to its low resistivity (resistivity of about 1.7 μΩ-cm). The conductive material 714 may be deposited using chemical vapor deposition (CVD) techniques, physical vapor deposition (PVD) techniques, electroplating techniques, or combinations thereof, to form the damascene structure.

[0120] Additionally, a barrier layer 716 such as tantalum (Ta), tantalum nitride (TaN), or other suitable barrier material may be deposited conformably on the sidewalls of the interconnect lines 710 and the vias 706H, before filling them with the conductive material 714, to prevent metal migration into the surrounding first and second dielectric layers 705, 708, as well as the barrier layer 704 and the hard mask layer 706.

[0121] FIGS. 8a-8gillustrate schematic cross-sectional views of a substrate 800 at different stages of a dual damascene structure fabrication sequence incorporating a silicon nitride barrier layer as well as a silicon nitride hard mask. Dual damascene structures are typically used to form multi-layer metal interconnects on integrated circuits. Depending on the specific stage of processing, substrate 800 may correspond to a silicon wafer, or other material layer that has been formed on the substrate 800. FIG. 8a, for example, illustrates a cross-sectional view of a substrate 800 having a metal layer 802 (e.g., copper (Cu), aluminum (Al), tungsten (W)) formed thereon.

[0122] FIG. 8aillustrates one embodiment in which the substrate 800 is silicon having a copper (Cu) layer formed thereon. The copper layer 802 has a thickness of about 5,000 Å to about 5 microns, depending on the size of the structure to be fabricated.

[0123] Referring to FIG. 8b, a silicon nitride barrier layer 804 is formed on the copper layer 802. The silicon nitride barrier layer 804 is formed on the copper layer 802 according to the process parameters described above. The silicon nitride barrier layer 804 has a dielectric constant less than about 7. The dielectric constant can be varied as a function of the gas composition (e.g., fluorine source concentration and/or silicon source concentration) during layer formation. The thickness of the silicon nitride barrier layer 804 is variable depending on the specific stage of processing. Typically, the silicon nitride barrier layer 804 has a thickness of about 200 Å to about 1,000 Å.

[0124] A first dielectric layer 805 is formed on the silicon nitride barrier layer 804, as illustrated in FIG. 8c. The first dielectric layer 805 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). The first dielectric layer 805 has a thickness of about 5,000 Å to about 10,000 Å.

[0125] Referring to FIG. 8d, a silicon nitride hard mask layer 806 is formed on the first dielectric layer 805, patterned and etched to defined vias therein. The silicon nitride hard mask layer 806 is formed on the first dielectric layer 805 according to the process parameters described above. The silicon nitride hard mask layer 805 has a dielectric constant less than about 7. The dielectric constant of the silicon nitride hard mask layer can be varied as a function of the gas composition (e.g., silicon source and fluorine source concentrations) during layer formation.

[0126] The thickness of the silicon nitride hard mask layer 806 is variable depending on the specific stage of processing. Typically, the silicon nitride hard mask layer 806 has a thickness of about 200 Å to about 1,000 Å.

[0127] Referring to FIG. 8e, after the silicon nitride hard mask layer 806 is patterned, a second dielectric layer 808 is deposited thereover. The second dielectric layer 808 may be an oxide (e.g., silicon dioxide, fluorosilicate glass (FSG)). The thickness of the second dielectric layer 808 is variable depending on the specific stage of processing. Typically, the second dielectric layer 812 has a thickness of about 5,000 Å to about 10,000 Å.

[0128] The second dielectric layer 808 is then patterned to define interconnect lines 810, as illustrated in FIG. 8f, preferably using conventional lithography processes described above. The interconnect lines 810 formed in the second dielectric layer 808 are positioned over the via openings 806H formed in the silicon nitride hard mask layer 806. Thereafter, as shown in FIG. 8g, the vias 806H are transferred through the first dielectric layer 804 and the silicon nitride barrier layer 804 by etching them using reactive ion etching or other anisotropic etching techniques.

[0129] The interconnect lines 810 and the vias 806H are filled with a conductive material 814 such as aluminum (Al), copper (Cu), tungsten (W), or combinations thereof. Preferably copper (Cu) is used to fill the interconnect lines 810 and the vias 806H due to its low resistivity (resistivity of about 1.7 μΩ-cm). The conductive material 814 may be deposited using chemical vapor deposition (CVD) techniques, physical vapor deposition (PVD) techniques, electroplating techniques, or combinations thereof, to form the damascene structure.

[0130] Additionally, a barrier layer 816 such as tantalum (Ta), tantalum nitride (TaN), or other suitable barrier material may be deposited conformably on the sidewalls of the interconnect lines 810 and the vias 806H, before filling them with the conductive material 814, to prevent metal migration into the surrounding first and second dielectric layers 805, 808, as well as the silicon nitride barrier layer 804 and the silicon nitride hard mask layer 806.

[0131] FIGS. 9a-9gillustrate schematic cross-sectional views of a substrate 900 at different stages of a dual damascene structure fabrication sequence incorporating organosilicate layers as low dielectric constant insulating layers. Dual damascene structures are typically used to form multi-layer metal interconnects on integrated circuits. Depending on the specific stage of processing, substrate 900 may correspond to a silicon wafer, or other material layer that has been formed on the substrate 900. FIG. 9a, for example, illustrates a cross-sectional view of a substrate 900 having a metal layer 902 (e.g., copper (Cu), aluminum (Al), tungsten (W)) formed thereon.

[0132] FIG. 9aillustrates one embodiment in which the substrate 900 is silicon having a copper (Cu) layer formed thereon. The copper layer 902 has a thickness of about 5,000 Å to about 5 microns, depending on the size of the structure to be fabricated.

[0133] Referring to FIG. 9b, a barrier layer 904 is formed on the copper layer 902. The barrier layer 904 may be a silicon carbide layer, or a silicon nitride layer, among others. The thickness of the barrier layer 904 is variable depending on the specific stage of processing. Typically, the barrier layer 904 has a thickness of about 200 Å to about 1,000 Å.

[0134] A first organosilicate layer 905 is formed on the barrier layer 904, as illustrated in FIG. 9c. The first organosilicate layer 905 is formed on the barrier layer 904 according to the process parameters described above. The organosilicate layer 905 has a dielectric constant less than about 3.5. The dielectric constant can be varied as a function of the gas composition (e.g., carbon source concentration and/or fluorine source concentration) during layer formation. The first organosilicate layer 905 has a thickness of about 5,000 Å to about 10,000 Å.

[0135] Referring to FIG. 9d, a hard mask layer 906 is formed on the first organosilicate layer 905, patterned and etched to defined vias therein. The hard mask layer 906 may be a silicon carbide layer, or a silicon nitride layer, among others. The thickness of the hard mask layer 906 is variable depending on the specific stage of processing. Typically, the hard mask layer 906 has a thickness of about 200 Å to about 1,000 Å.

[0136] Referring to FIG. 9e, after the hard mask layer 906 is patterned, a second organosilicate layer 908 is deposited thereover. The second organosilicate layer 908 is deposited according to the process parameters described above. The thickness of the second organosilicate layer 908 is variable depending on the specific stage of processing. Typically, the second organosilicate layer 908 has a thickness of about 5,000 Å to about 10,000 Å.

[0137] The second organosilicate layer 908 is then patterned to define interconnect lines 910, as illustrated in FIG. 9f, preferably using conventional lithography processes described above. The interconnect lines 910 formed in the second organosilicate layer 908 are positioned over the via openings 906H formed in the hard mask layer 906. Thereafter, as shown in FIG. 9g, the vias 906H are transferred through the first organosilicate layer 905 and the barrier layer 904 by etching them using reactive ion etching or other anisotropic etching techniques.

[0138] The interconnect lines 910 and the vias 906H are filled with a conductive material 914 such as aluminum (Al), copper (Cu), tungsten (W), or combinations thereof. Preferably copper (Cu) is used to fill the interconnect lines 910 and the vias 906H due to its low resistivity (resistivity of about 1.7 μΩ-cm). The conductive material 914 may be deposited using chemical vapor deposition (CVD) techniques, physical vapor deposition (PVD) techniques, electroplating techniques, or combinations thereof, to form the damascene structure.

[0139] Additionally, a barrier layer 916 such as tantalum (Ta), tantalum nitride (TaN), or other suitable barrier material may be deposited conformably on the sidewalls of the interconnect lines 910 and the vias 906H, before filling them with the conductive material 914, to prevent metal migration into the surrounding first and second organosilicate layers 905, 908, as well as the barrier layer 904 and the hard mask layer 906.

[0140] Although several preferred embodiments which incorporate the teachings of the present invention have been shown and described in detail, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.