Semiconductor chip module

[0002] 1. Field of the Invention

[0003] The invention relates to a semiconductor chip module, more particularly to semiconductor chip modules that can be stacked one on top of the other in a fully automated manner.

[0004] 2. Description of the Related Art

[0005] In this age of computer technology, there is an ever-growing need to increase the speed and functionality of computers, thereby resulting in a corresponding need to increase the memory capacity. However, due to limitations in the size of a computer main board, the number of on-board memory devices that can be installed is severely limited. There is thus a need to develop a memory device having a capacity that can be expanded without incurring a substantial increase in board penalty.

[0006] In U.S. Pat. No. 4,996,587, there is disclosed an integrated semiconductor chip package that includes a plurality of chip carriers arranged in a stack, and a plurality of semiconductor chips mounted on the chip carriers. However, due to the need for S-shaped connector clips mounted on the chip carriers to establish electrical connection among the semiconductor chips, the integrated semiconductor chip package according to the aforesaid U.S. patent cannot be manufactured in a fully automated manner, thereby resulting in increased production costs.

[0007] Therefore, the object of the present invention is to provide semiconductor chip modules that can be stacked one on top of the other in a fully automated manner.

[0008] According to one aspect of the invention, a semiconductor chip module comprises:

[0009] a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces;

[0010] a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;

[0011] a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member;

[0012] a conductor unit for connecting electrically the contact pads of the semiconductor chip and the circuit traces; and

[0013] a plurality of solder balls disposed on one of the first and second surfaces of the chip-mounting member, each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member.

[0014] According to another aspect of the invention, a semiconductor chip module stack comprises upper and lower semiconductor chip modules, each including:

[0015] a chip-mounting member having upper and lower surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the upper and lower surfaces and that are connected to the circuit traces;

[0016] a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;

[0017] a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member;

[0018] a conductor unit for connecting electrically the contact pads of the semiconductor chip and the circuit traces; and

[0019] a plurality of solder balls disposed on the lower surface of the chip-mounting member, each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member.

[0020] The solder balls of the upper semiconductor chip module are aligned with and are connected to the plated through holes in the chip-mounting member of the lower semiconductor chip module at the upper surface of the latter.

[0021] Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:

[0022] FIG. 1 is a fragmentary schematic partly sectional view of the first preferred embodiment of a semiconductor chip module according to the present invention;

[0023] FIG. 2 is a fragmentary perspective view of a chip-mounting member of the first preferred embodiment;

[0024] FIG. 3 is a perspective view illustrating a semiconductor chip of the first preferred embodiment;

[0025] FIG. 4 is a perspective view illustrating a dielectric tape member of the first preferred embodiment;

[0026] FIG. 5 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the first preferred embodiment can be interconnected to form a stack;

[0027] FIG. 6 is a fragmentary schematic partly sectional view of the second preferred embodiment of a semiconductor chip module according to the present invention;

[0028] FIG. 7 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the second preferred embodiment can be interconnected to form a stack;

[0029] FIG. 8 is a fragmentary schematic partly sectional view of the third preferred embodiment of a semiconductor chip module according to the present invention;

[0030] FIG. 9 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the third preferred embodiment can be interconnected to form a stack;

[0031] FIG. 10 is a fragmentary schematic partly sectional view of the fourth preferred embodiment of a semiconductor chip module according to the present invention;

[0032] FIG. 11 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a stack; and

[0033] FIG. 12 is a fragmentary schematic partly sectional view of the fifth preferred embodiment of a semiconductor chip module according to the present invention.

[0034] Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure.

[0035] Referring to FIG. 1, the first preferred embodiment of a semiconductor chip module according to the present invention is shown to comprise a chip-mounting member 1, at least two semiconductor chips 2, and a plurality of solder balls 3.

[0036] In this embodiment, the chip-mounting member 1 is a board body having opposite first and second chip mounting surfaces 10, 11 that are respectively formed with circuit traces 12 (see FIG. 2). The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10, 11 and that are connected electrically to the circuit traces 12 on the surfaces 10, 11.

[0037] Each of the semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon (see FIG. 3). The pad mounting surface 20 of each of the semiconductor chips 2 is bonded adhesively on one of the first and second chip mounting surfaces 10, 11 via a dielectric tape member 4. Particularly, the dielectric tape member 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2, and an opposite second adhesive surface adhered onto the first or second chip mounting surface 10, 11. The dielectric tape member 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2 (see FIG. 4). Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2 and the circuit traces 12 on the first or second chip mounting surface 10, 11. Preferably, each semiconductor chip 2 has a peripheral portion that is provided with an epoxy resin layer 23 to strengthen bonding of the semiconductor chip 2 with the first or second chip mounting surface 10, 11. Moreover, each semiconductor chip 2 has a heat dissipating surface that is opposite to the pad mounting surface and that has a heat dissipating plate 24 secured thereon for heat dissipating and chip protection purposes.

[0038] Each of the solder balls 3 (only two are shown in FIG. 1) is made from tin and is disposed on the second chip mounting surface 11 of the chip-mounting member 1. Each of the solder balls 3 is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the circuit traces 12 on the surfaces 10, 11 of the chip-mounting member 1.

[0039] While FIG. 1 shows only one semiconductor chip 2 mounted on each of the surfaces 10, 11 of the chip-mounting member 1, it should be clear to one skilled in the art that two or more semiconductor chips 2 may be mounted on each of the surfaces 10, 11.

[0040] Referring to FIG. 5, two or more semiconductor chip modules of the first preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.

[0041] FIG. 6 illustrates the second preferred embodiment of a semiconductor chip module according to the present invention. As shown, the chip-mounting member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10, 11 that are respectively formed with circuit traces similar to those shown in FIG. 2. The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10, 12 and that are connected electrically to the circuit traces on the surfaces 10, 11. Each of the surfaces 10, 11 is formed with at least one chip receiving cavity 13 having an open end and a closed end opposite to the open end. Each of the semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface. Each of the semiconductor chips 2 is received in a respective one of the chip receiving cavities 13 in the chip-mounting member 1 with the pad mounting surface 20 being accessible from the first or second chip mounting surface 10, 11 via the open end of the respective one of the chip receiving cavities 13. The chip fixing surface of each of the semiconductor chips 2 is bonded adhesively on the closed end of the respective one of the chip receiving cavities 13 via a dielectric tape member 4a. Particularly, the dielectric tape member 4ahas a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2, and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13. In addition, wires 22 interconnect the contact pads 21 of the semiconductor chip 2 and the circuit traces on the first or second chip mounting surface 10, 11. Preferably, an encapsulation layer 6, made of epoxy resin, is provided on each of the first and second chip mounting surfaces 10, 11 to enclose the pad mounting surface 20 of each semiconductor chip 2 and the wires 22 that are connected to the semiconductor chip 2 for protection purposes. Like the previous embodiment, each of the solder balls 3 is disposed on the second chip mounting surface 11 of the chip-mounting member 1, and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the wires 22 and the circuit traces on the surfaces 10, 11 of the chip-mounting member 1. Referring to FIG. 7, two or more semiconductor chip modules of the second preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.

[0042] FIG. 8 illustrates the third preferred embodiment of a semiconductor chip module according to the present invention. As shown, the chip-mounting member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10, 11 formed with at least one chip receiving cavity 13ahaving an open end and a closed end opposite to the open end. The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the surfaces 10, 12. The first and second chip mounting surfaces 10, 11 and the closed end of each chip receiving cavity 13aare respectively formed with circuit traces similar to those shown in FIG. 2 and connected electrically to the plated through holes 14. Each of the chip receiving cavities 13 receives two semiconductor chips 2a, 2btherein. Each of the semiconductor chips 2a, 2bhas a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface. The pad mounting surface 20 of each of the semiconductor chips 2ais bonded adhesively on the closed end of the respective one of the chip receiving cavities 13avia a dielectric tape layer 4. Particularly, the dielectric tape layer 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2a, and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13a. Like the first preferred embodiment, the dielectric tape layer 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2a. Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2aand the circuit traces on the closed end of the respective one of the chip receiving cavities 13a. Each of the semiconductor chips 2bis received in the respective one of the chip receiving cavities 13awith the pad mounting surface 20 thereof being accessible from the first or second chip mounting surface 10, 11 via the open end of the respective one of the chip receiving cavities 13a. The chip fixing surface of each of the semiconductor chips 2bis bonded adhesively on the chip fixing surface of the semiconductor chip 2athat is disposed in the same one of the chip receiving cavities 13avia another dielectric tape layer 4a. Particularly, the dielectric tape layer 4ahas a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2b, and an opposite second adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2a. In addition, like the second preferred embodiment, wires 22 interconnect the contact pads 21 of the semiconductor chip 2band the circuit traces on the first or second chip mounting surface 10, 11. Moreover, an encapsulation layer 6, made of epoxy resin, is provided on each of the surfaces 10, 11 of the chip-mounting member 1 to enclose the pad mounting surface 20 of each semiconductor chip 2band the wires 22 that are connected to the semiconductor chip 2bfor protection purposes. As with the previous embodiments, each of the solder balls 3 is disposed on the second chip mounting surface 11, and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2acan be established via the circuit traces on the closed ends of the chip receiving cavities 13a, while electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2bcan be established via the wires 22 and the circuit traces on the surfaces 10, 11 of the chip-mounting member 1.

[0043] Referring to FIG. 9, two or more semiconductor chip modules of the third preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.

[0044] Referring to FIG. 10, the fourth preferred embodiment of a semiconductor chip module according to the present invention is shown to comprise first and second chip-mounting members 1a, 1b, a first semiconductor chip 2a, a second semiconductor chip 2b, a plurality of first solder balls 3a, and a plurality of second solder balls 3b.

[0045] In this embodiment, the first chip-mounting member 1ais a board body having an upper chip mounting surface 15aand a lower circuit layout surface 16aformed with circuit traces similar to those shown in FIG. 2. The first chip-mounting member 1ais further formed with an opening 17aand a plurality of plated through holes 14athat extend through the surfaces 15a, 16aand that are connected electrically to the circuit traces on the circuit layout surface 16a. The first semiconductor chip 2ahas a pad mounting surface 20awith a plurality of contact pads 21aprovided thereon. The pad mounting surface 20ais bonded adhesively on the chip mounting surface 15ausing a dielectric tape member 7. Particularly, the dielectric tape member 7 has a first adhesive surface adhered onto the pad mounting surface 20a, and an opposite second adhesive surface adhered onto the chip mounting surface 15a. The dielectric tape member 7 is formed with an opening 70 that is registered with the opening 17asuch that the contact pads 21aare accessible from the circuit layout surface 16avia the openings 17a, 70. Wires 22ainterconnect the contact pads 21aand the circuit traces on the circuit layout surface 16a. Preferably, a peripheral portion of the first semiconductor chip 2ais provided with an epoxy resin layer 23ato strengthen bonding of the first semiconductor chip 2awith the chip mounting surface 15a. Moreover, the first semiconductor chip 2ahas a heat dissipating surface that is opposite to the pad mounting surface 20aand that has a heat dissipating plate 24asecured thereon for heat dissipating and chip protections purposes. In addition, an encapsulation layer 6amade of epoxy resin is provided on the circuit layout surface 16ato enclose the pad mounting surface 20aand the wires 22afor protection purposes. Each of the first solder balls 3a(only two are shown in FIG. 10) is made from tin and is disposed on the circuit layout surface 16a. Each of the first solder balls 3ais aligned with and is connected to a respective one of the plated through holes 14ain the first chip-mounting member 1a. Thus, electrical connection between the first solder balls 3aand the contact pads 21aof the first semiconductor chip 2acan be established via the circuit traces on the circuit layout surface 16aand the wires 22a.

[0046] Unlike the first chip-mounting member 1a, the second chip-mounting member 1bis a board body having a lower chip mounting surface 15band an upper circuit layout surface 16bformed with circuit traces similar to those shown in FIG. 2. The second chip-mounting member 1bis further formed with an opening 17band a plurality of plated through holes 14bthat extend through the surfaces 15b, 16band that are connected electrically to the circuit traces on the circuit layout surface 16b. The second semiconductor chip 2bhas a pad mounting surface 20bwith a plurality of contact pads 21bprovided thereon. The pad mounting surface 20bis bonded adhesively on the chip mounting surface 15busing a dielectric tape member 8. Particularly, the dielectric tape member 8 has a first adhesive surface adhered onto the pad mounting surface 20b, and an opposite second adhesive surface adhered onto the chip mounting surface 15b. The dielectric tape member 8 is formed with an opening 80 that is registered with the opening 17bsuch that the contact pads 21bare accessible from the circuit layout surface 16bvia the openings 17b, 80. Wires 22binterconnect the contact pads 21band the circuit traces on the circuit layout surface 16b. Like the first semiconductor chip 2a, a peripheral portion of the second semiconductor chip 2bis provided with an epoxy resin layer 23bto strengthen bonding of the second semiconductor chip 2bwith the chip mounting surface 15b. Moreover, the second semiconductor chip 2bhas a heat dissipating surface that is opposite to the pad mounting surface 20band that has a heat dissipating plate 24bsecured thereon for heat dissipating and chip protection purposes. In addition, an encapsulation layer 6bmade of epoxy resin is provided on the circuit layout surface 16bto enclose the pad mounting surface 20band the wires 22bfor protection purposes. Each of the second solder balls 3b(only two are shown in FIG. 10) is made from tin and is disposed on the chip mounting surface 15b. Each of the second solder balls 3bis aligned with and is connected to a respective one of the plated through holes 14bin the second chip-mounting member 1b. Thus, electrical connection between the second solder balls 3band the contact pads 21bof the second semiconductor chip 2bcan be established via the circuit traces on the circuit layout surface 16band the wires 22b.

[0047] In this embodiment, the second chip-mounting member 1bis disposed below the first chip-mounting member 1a, and each of the first solder balls 3aon the circuit layout surface 16aof the first chip-mounting member 1ais aligned with and is connected to a respective one of the plated through holes 14bat the circuit layout surface 16aof the second chip-mounting member 1b.

[0048] Referring to FIG. 11, two or more semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the second solder balls 3bon an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14aat the chip mounting surface 15aof the first chip-mounting member 1aof a lower one of the semiconductor chip modules. The second solder balls 3bof a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.

[0049] FIG. 12 illustrates the fifth preferred embodiment of a semiconductor chip module according to the present invention. In contrast with the fourth preferred embodiment, each of the first and second chip-mounting members 1a, 1bhas at least two first and second semiconductor chips 2a, 2bmounted respectively thereon.

[0050] It has thus been shown that the semiconductor chip module of this invention does not require the use of connector clips to establish electrical connection with other semiconductor chip modules. The semiconductor chip module can be manufactured in a fully automated manner to result in lower production costs. When the semiconductor chips are memory chips, a significant increase in memory capacity is possible without incurring a significant increase in board penalty. The object of the present invention is thus met.

[0051] While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.