Retrieving I/O processor performance monitor data

[0002] 1. Field of the Invention

[0003] The present invention relates to computer system architecture. More specifically, the present invention relates to retrieving performance monitor data from an I/O processor.

[0004] 2. Background Information

[0005] Electronic products may be thought of as those products that involve the controlled conduction of electrons or other charge carriers, especially through microprocessors. Examples of electronic products may include radios, computers, work stations, and servers as well as those involved in high-end networking and storage technology. Just about all electronic products employ one or more microprocessors disposed within a chip located on a printed circuit board. These microprocessors engage a computer operating system as well as applications. The main central processing unit within the chip may include a host system. It may be this host system that runs the computer operating system and the applications.

[0006] One type of processor within the host system may be a host processor having a host memory. Another type of processor that may be within the host system may be an input-output (I/O) processor. The I/O processor or I/O Platform (IOP) may be a component of the host system that connects the host system memory to an I/O device to process I/O transactions. The I/O device may be a part of or external to the host system through at least one of a first bus and a second bus. Examples of I/O devices include storage devices such as a small computer systems interface (SCSI) controller for a disk and networking devices such as an Ethernet controller.

[0007] One main function of a host system may be to transmit data between the host memory and an I/O device via the I/O processor. Transmitted data may include application data, local area network (LAN) packets, and contents stored on a disk. To accomplish data transmission, data handling and processing units such as a core processor and a local memory may be included within the I/O processor. The core processor and the local memory may be coupled to each other through an internal bus and to a messaging unit and a direct memory access unit through that same internal bus. Ideally, the system performs within established parameters.

[0008] To measure and monitor various system parameters that contribute to the overall performance of the I/O processor, a performance monitoring unit may be integrated into the I/O processor. Under current standards, the tasks of the performance monitoring unit may include compiling performance measurements on three buses: the first bus; the second bus; and the internal bus. The measurements of the performance monitoring unit can be used to refine code for improved system level performance. However, these measurements exist in raw, binary data for which no mechanism exists that gathers and compiles this raw, I/O performance monitor data into a form that readily may be usable by a computer programmer or operator.

[0009] An embodiment includes retrieving performance monitor data from an I/O processor. A performance monitoring driver coupled to a performance monitoring unit may be registered as a private driver with a real time operating system of the I/O processor. Events within the I/O processor may be selected on which to gather data. The selected events may be sent as a message request to the real time operating system. The message request may be translated into the appropriate parameters based on a set of private group parameters that may be accessible by the real time operating system. The message request may be sent as a translated request to the performance monitoring unit. The pieces of data requested by the translated request may be returned to the performance monitoring driver. The pieces of data then may be sent to a location specified in the message request.

[0010] FIG. 1 is a functional block diagram of an I/O processor;

[0011] FIG. 2 is a block diagram of a networking system 200;

[0012] FIG. 3 illustrates a more detailed view of a host processor and an I/O processor; and

[0013] FIG. 4 is a flow diagram of a method of operation 500 of the invention.

[0014] FIG. 1 is a functional block diagram of I/O processor 10. An example of a known processor functional block diagram may be illustrated and described for the Intel® i960® RM/RP Microprocessor as set out in Intel Corporation, i960® RM/RN I/O Processor Developer's Manual, pp. 1-1 through 1-12 (1st ed. July 1998). The description regarding FIG. 1 may be based on the Intel® i960® RM/RP Microprocessor.

[0015] As show in FIG. 1, I/O processor 10 may integrate core processor 14 into as part of a Peripheral Components Interconnect (PCI) functionality so as to address the needs of intelligent input-output applications (“intelligent I/O” or “I₂O” applications). Intelligent I/O applications may be coupled to PCI bus 16 and/or PCI bus 18. Both PCI bus 16 and PCI bus 18 may be industry standard, 64-bit/32-bit, high performance, low latency system buses coupled together by PCI-to-PCI bridge 20. A specification for the PCI bus may be set forth in the document PCI Local Bus Specification, revision 2.1, October, 1994. This manual may be prepared and maintained by the PCI Special Interest Group (PCI-SIG). The PCI-SIG may be an organization that may be open for membership to all companies in the computer industry.

[0016] Along with providing a connection path between the two independent PCI buses 16 and 18, bridge 20 may provide the ability to overcome PCI electrical loading limits by allowing certain bus transactions on one PCI bus to be forwarded to the other PCI bus. Core processor 14 may be indirectly connected to PCI-to-PCI bridge 20. Bus interface unit 24 may couple core processor 14 to internal bus 26. In turn, internal bus 26 may be coupled to transfer group 28 and transfer group 30. Internal bus 26 may be a 64-bit bus. PCI-to-PCI bridge 20 may be coupled to transfer group 28 through PCI bus 16 and may be coupled to transfer group 30 through PCI bus 18, each path of which may provide a link to core processor 14. By communicatively connecting core processor 14 to bridge 20, core processor 14 may provide processor “intelligence” to bridge 20 to better address the needs of intelligent I/O applications coupled to PCI bus 16 and/or PCI bus 18.

[0017] PCI agents 100 may be coupled to either PCI bus 16 or PCI bus 18 so as to interact with one of the transfer groups, 28 and 30. PCI agents 100 may include external PCI devices or a host processor, such as host processor 240. Within PCI agent 100 may be PCI memory having PCI address spaces.

[0018] Internal bus 26 may be coupled to local memory 38 through memory controller 40. Local memory 38 may include memory systems external to I/O processor 10 that do not require external logic. Examples of local memory 38 may include Synchronous Dynamic Random Access Memory (SDRAM), Read-Only Memory (ROM), and Flash memory.

[0019] Transfer group 28 may be composed of Address Translation Unit 32, two Direct Memory Access channels 34, and messaging unit 36. Transfer group 30 may be composed of Address Translation Unit 42 and One DMA channel 44.

[0020] Address Translation Unit (ATU) 32 may allow transactions between the PCI address space within PCI agent (or “agents”) 100 and address space 46 within local memory 38. Address translation may be controlled through programmable registers (not shown) that may be accessible from both PCI agent 100 and core processor 14. ATU 42 may function similarly to ATU 32, but may work in conjunction with PCI bus 18 for PCI agents 100 coupled to PCI bus 18. Dual access to registers through ATU 32 and ATU 42 may allow flexibility in mapping the coupled address spaces.

[0021] To provide low latency and high throughput data transfers between PCI agents 100 and local memory 38, three separate DMA channels may be provided as shown in FIG. 1. Two Direct Memory Access (DMA) channels 34 may be included with transfer group 28 and one DMA channel 44 may be included with transfer group 30. The three DMA channels may operate as a DMA controller to support chaining and unaligned data transfers. This DMA controller may be programmable through core processor 14.

[0022] The I₂O Architecture Specification describes an open architecture for developing device drivers in a system environment. Conventionally, based on the I₂O Architecture Specification, messaging unit (MU) 36 provides data transfer between PCI agents 100 coupled to PCI bus 16 and core processor 14. MU 36 can be used to send and receive messages. Moreover, MU 36 may interrupt PCI bus agents 100 or core processor 14 when new data arrives and passes the data as directed.

[0023] Core processor 14 may be interfaced with internal bus 26 through bus interface unit 24. Local memory 38 may be coupled to internal bus 26 through memory controller unit 40. Microcontrollers 56 may be interfaced with internal bus 26 through the series of Inter-Integrated Circuit (I²C) serial bus 50 and I²C bus interface unit 52. Both local memory 38 and microcontrollers 56 may be external to I/O processor 10. Application accelerator unit 54 may be also coupled to internal bus 26.

[0024] Memory controller 40 may allow direct control of local memory 38. Core processor 14 may operate out of local memory 38 where this memory space may be independent of PCI agents 100. Bus interface unit (BIU) 24 may forward accesses to core processor 14 to internal bus 26 without translation. Microcontrollers 56 may perform management functions for the systems of I/O processor 10. Application accelerator unit (AAU) 54 may execute data transfers to and from local memory 38 on behalf of core processor 14 as set out for the I₂O standard.

[0025] I/O processor 10 may further include internal arbitration unit 60 to serve as arbiter for the systems of internal bus 26, PCI arbitration unit 62 to serve as arbiter for the PCI bus 18, and performance monitoring unit (PMON) 64.

[0026] As noted above, performance monitoring unit (PMON) 64 may be used to compile performance measurements on the three buses: PCI bus 16, PCI bus 18, and internal bus 26. The compiled measurements of PMON 64 can be used for performance analysis or real-time system tuning by refining code for improved system level performance.

[0027] Within the I₂O Architecture, data may be stored in parameter groups on I/O processor 10 such as in local memory 38. Data in local memory 38 may be modified or extracted by host processor 240 through a message sent by host processor 240 to I/O processor 10. However, the I₂O Architecture does not provide any mechanism for gathering performance measurements compiled by PMON 64. The below embodiments of the invention extend the I₂O Architecture to provide this capability.

[0028] FIG. 2 is a block diagram of networking system 200. Networking system 200 may include client 300 coupled to client 400 through host system 230. Host system 230 may include host processor 240 coupled to I/O processor 210 through host system or PCI bus 250. Within host system 230 may be I/O device 260 interfaced with I/O processor (IOP) 210. Network lines 402 may be coupled to I/O device 260.

[0029] Client 300 may be a computer that may include data input devices such as keyboard 302 and mouse 304 and may include visual monitor 306. Preferably, host system 230 physically may be part of client 300, but may be remote from client 300. For example, client 300 may be in one location and host system 230 may be in another location, but connected via communication channels 308, where channels 309 may include radio signals, cabling, or the Internet.

[0030] As one example of networking system 200, host system 230 may be connected to client 400 through network lines 402. Network lines 402 may be any form of communication channel over which data from host system 230 may be transmitted to client 400. Client 400 may be composed of one computer or millions of computers.

[0031] FIG. 3 illustrates a more detailed view of host processor 240 and I/O processor 210. Within host processor 240 may be an Operating System Specific Module (OSM) 300. Preferably, OSM 300 may be the host process software for the I₂O architecture. OSM 300 may be coupled to Real Time Operating System (RTOS) 302. The software of RTOS 302 may abstract a large portion of I/O processor 210 hardware from the rest of the software that runs on I/O processor 210. By permitting common commands to enable applications within I/O processor 210, RTOS 302 may permit a programmer to develop a driver for one I/O device and get the driver running on one or many different I/O processors with minimal effort.

[0032] Conventionally, drivers may be used to couple devices external to I/O processor 210. As shown in FIG. 3, Small Computer System interface (SCSI) device driver 312 may couple SCSI controller 310 to RTOS 302 as an example of a storage device. Network lines 402, as coupled to Ethernet 410, may be coupled to RTOS 302 through networking network driver 314 as an example of a networked device.

[0033] RTOS 302 may aid in message passing between the external devices and OSM 300. By conceptually treating PMON unit 64 as a device external to I/O processor 210, the invention takes advantage of the message passing features of RTOS 302 by coupling PMON unit 64 to RTOS 302 through PMON driver 320. PMON driver 320 may be a Device Driver Module (DDM) dedicated to performance (perf) monitoring resources and may be referred to as “perfDDM”. PMON driver 320 may operate by itself or work in conjunction with either a storage device or a networking device.

[0034] The system management interface of the I₂O Architecture Specification provides for developing private parameter groups. Private parameter groups may reside in the I/O processor memory. An Operating System Specific Module may be used to gather data from a driver. For example, private parameter groups of the invention may reside in the I/O processor memory and OSM 300 may be used to gather data from PMON driver 320 of FIG. 3.

[0035] Each parameter group may include a group number, a group type, a group name, a description of the group, and may include one or more parameters belonging to the group. A parameter may be identified by a field number, whether the parameter may be readable or writable, the file size of the parameter, the parameter name, and a description of the parameter. In one embodiment of the invention, three private parameter groups containing a total of thirty one fields reside as software in memory 38 of I/O processor 210.

[0036] Within performance monitoring Table 1, Table 2, and Table 3 below may be a set of parameter groups that define an embodiment of the invention. Table 1 may be the Control Group, Table 2 may be the Mode Control Group and Table 3 may be the Mode Data Group. The contents of the parameter groups may include the performance monitor data and performance monitor setup information. Software running on host processor 240 may be able to gather or modify one or more parameters stored in these parameter groups.

[0037] FIG. 4 is a flow diagram of a method of operation 500 of the invention. Method 500 may be implemented in a computer readable storage medium containing executable computer program instructions which when executed cause the networking system to perform method 500. Also, method 500 may be implemented in a distributed readable storage medium containing executable computer program instructions which when executed cause an I/O processor to perform method 500.

[0038] At initialization 502 of method 500, the software in local memory 38 of I/O processor 210 may initialize. This may create a performance monitoring (PMON) storage table in local memory 38. The PMON storage table may be able to store and keep separate the various pieces of information retrieved from PMON unit 64 and placed in that table. Additionally, initializing the software in local memory 38 also may cause PMON driver 320 to register as a private driver with RTOS 302 of I/O processor 210 since PMON driver 320 may not be a networking type driver or a storage type driver.

[0039] In operation, a user of client 300 or client 400 of FIG. 2 may initiate a performance monitor application at step 506 that may generate a selection screen at visual monitor 306. The selection screen may allow the user to select those events on PCI bus 16, PCI bus 18, or internal bus 26 for which the user desires to compile data. The user may also specify the time periods that the user desires to see the compiled data at visual monitor 306. In regards to the events on PCI bus 16, PCI bus 18, or internal bus 26, the I₂O Architecture divides monitorable events into occurrence events and duration events. Occurrence events may be counted each time the event occurs. For a duration event, a counter may count the number of clocks during which a particular condition or set of conditions may be true. A total of ninety-eight events may be monitored, subject to the availability of event counters.

[0040] At step 510, the user may select at visual monitor 306 those events on PCI bus 16, PCI bus 18, or internal bus 26 for which the user desires to compile data by entering their selection in the selection screen. After selecting those events the user desired monitored, the information entered into the selection screen at visual monitor 306 may be sent at step 514 to OSM 300 of host processor 240 as a message request. This message request may specify specific pieces of data from PMON unit 64. OSM 300 may relay this message request to RTOS 302 at step 518 without an understanding of whether the message request is for a networking type driver, a storage type driver, or a private driver. However, RTOS 302 may recognize this message request as a request for the PMON driver 320, previously registered as a private driver with RTOS 302.

[0041] Using the fields of the three private parameter groups residing in local memory 38 of I/O processor 210, RTOS 302 may translate the message request at step 522 into the appropriate parameter of the private group parameters of the invention. Parameters of the private group parameters may be set out in Table 1, Table 2, and Table 3 above.

[0042] At step 526, RTOS 302 send this translated request to PMON driver 320. In response to receiving the translated request, PMON driver 320 may query PMON unit 64 at step 530 for the specific pieces of data requested by the user. The query to PMON unit 64 may result in the requested pieces of data being sent to PMON driver 320 at step 534. PMON driver 320, in turn, may send this data to the PMON storage table in local memory 38 at step 538 where the data may be compiled and stored for dispatch to the user at the time periods specified by the user at visual monitor 306 in the selection screen. The data may be saved in such a way that another application may be written that would take this data and present it to client 300, for example, in a meaningful fashion.

[0043] At the time periods specified by the user in the selection screen, I/O processor 210 may send the compiled performance monitoring data back to the user through RTOS 302 and OSM 300 at step 542. The compiled performance monitoring data may also be directed to other locations within networking system 200 for purposes such as to cause an effect. For example, the data may be sent to an interpreting device that determines whether the server of host system 230 is too hot based on the compiled performance monitoring data. If so, the interpreting device may generate a message that causes an internal fan to turn on.

[0044] The exemplary embodiments described herein are provided merely to illustrate the principles of the invention and should not be construed as limiting the scope of the subject matter of the terms of the claimed invention. The principles of the invention may be applied toward a wide range of systems to achieve the advantages described herein and to achieve other advantages or to satisfy other objectives, as well.