Clock synchronization circuit

[0002] 1. Technical Field

[0003] The present invention relates to a clock synchronization circuit that is able to compensate for a skew between an external clock signal and an internal clock signal and, in particular, to a clock synchronization circuit that can precisely synchronize clock signals regardless of noise generated due to shift in delay lines by using two delay lines and a phase mixer.

[0004] 2. Description of the Background Art

[0005] In general, a clock synchronization circuit such as a delay locked loop (DLL), or a phase locked loop (PLL) is used as a clock generating device for compensating for a skew between an external clock signal and an internal clock signal.

[0006] Referring to FIG. 1, a conventional clock synchronization circuit includes: a variable delay line 1 for delaying an external clock signal EXCLK for a predetermined time and for generating an internal clock signal INCLK; a delay monitor 2 for monitoring a delay time of the internal clock signal INCLK from the variable delay line 1; a phase detector 3 for comparing a phase difference between the external clock signal EXCLK and the internal clock signal INCLK, and outputting shift signals SHL and SHR for adjusting the phase difference; and a shift register 4 for controlling the delay time of the variable delay line 1 according to the shift signals SHL and SHR from the phase detector 3.

[0007] The variable delay line 1 delays the external clock signal EXCLK for a predetermined time, and outputs the internal clock signal INCLK. Here, the internal clock signal INCLK is inputted to the phase detector 3 through the delay monitor 2, so that the phase detector 3 judges whether the internal clock signal INCLK has a faster or slower phase than the external clock signal EXCLK.

[0008] The phase detector 3 controls the shift register 4 according to the shift signals SHL and SHR, so that the external clock signal EXCLK and the internal clock signal INCLK have the same phase.

[0009] The shift register 4 outputs control signals SL1-SLN according to the shift signals SHL and SHR. The variable delay line 1 controls a delay time of the external clock signal EXCLK so that a phase of the external clock signal EXCLK can be synchronized with a phase of the internal clock signal INCLK.

[0010] As shown in FIG. 2, the variable delay line 1 includes: NAND gates ND1-NDN for selectively outputting the external clock signal EXCLK according to the output signals SL1-SLN from the shift register 4; unit delay cells DEL1-DELN connected in series for delaying the external clock signal EXCLK selectively outputted by the NAND gates ND1-NDN; and a NAND gate NDA for NANDing a power voltage VCC and the output signal from the last unit delay cell DELN and for outputting the internal clock signal INCLK.

[0011] Here, the unit delay cell DELi includes: a NAND gate ND1ifor NANDing the output signal from the previous unit delay cell DEL(i−1) and the output signal from the NAND gate NDi; a NAND gate ND2ifor NANDing the power voltage VCC and the output signal from the NAND gate ND1i.

[0012] The operation of the conventional clock synchronization circuit will now be explained.

[0013] When it is presumed that the second signal of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(N−2) and SLN have a low level in an early stage, the external clock signal EXCLK is delayed through a delay path from the second delay cell DEL(N−1) to the last delay cell DELN, and outputted as the internal clock signal INCLK.

[0014] Here, the phase detector 3 compares the phase of the external clock signal EXCLK with the phase of the internal clock signal INCLK. When the phase of the external clock signal EXCLK is faster than that of the internal clock signal INCLK, the phase detector 3 outputs the control signal SHL to shift left the shift register 4.

[0015] Because the second signal SL(N−1) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(N−2) and SLN have a low level in an early stage, the third signal SL(N−2) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(N−3), SL(N−1) and SLN have a low level according to the control signal SHL from the phase detector 3. Accordingly, the external clock signal EXCLK is delayed through a delay path from the third delay cell DEL(N−2) to the last delay cell DELN, and outputted as the internal clock signal INCLK.

[0016] Conversely, when the phase detector 3 compares the phase of the external clock signal EXCLK with the phase of the internal clock signal INCLK, if the phase of the external clock signal EXCLK is slower than that of the internal clock signal INCLK, the phase detector 3 outputs the control signal SHR to shift right the shift register 4. Because the second signal SL(N−1) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(N−2) and SLN have a low level in an early stage, the first signal SLN of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(N−1) have a low level according to the control signal SHR from the phase detector 3. Therefore, the external clock signal EXCLK is delayed through a delay path of the last delay cell DELN, and outputted as the internal clock signal INCLK.

[0017] In the conventional clock synchronization circuit for the semiconductor memory device, the variable delay line 1 includes the unit delay cells DEL1-DELN connected in series and each respectively having two serially-connected NAND gates.

[0018] Accordingly, a number of the unit delay cells DELi increases or decreases to adjust a delay time. Here, the shift right or left is performed in unit delay cell units according to the output signals SL1-SLN from the shift register 4 to increase or decrease the number of the unit delay cells DELi.

[0019] However, the phase is suddenly changed for a time period as long as the delay time of the unit delay cell DELi. As shown in FIG. 3, when the shift is generated in time point ‘A,’ the internal clock signal INCLK has a jitter. In addition, a pulse width of the clock varies, and thus a clock period is changed.

[0020] A clock synchronization circuit may include at least two variable delay lines for respectively delaying an external clock signal for a different delay time and at least two shift registers for respectively controlling the delay time of the variable delay lines. The circuit may also include a phase mixer for mixing phases of the clock signals delayed by the variable delay lines, and outputting an internal clock signal having a phase between the phases of the delayed clock signals; a phase detecting unit for comparing the phase of the external clock signal with the phase of the internal clock signal, and outputting the result; and a control unit for outputting a first control signal for determining the phase of the internal clock signal from the phase mixer, and a second control signal for controlling a shift operation of at least one shift register among the shift registers according to the comparison result of the phase detecting unit.

[0021] A second clock synchronization circuit may include a normal internal clock signal generator for generating a normal internal clock signal to be synchronized with an external clock signal and an inverted internal clock signal generator for outputting an inverted internal clock signal to be synchronized with a phase-shifted clock signal of the external clock signal. In such an arrangement, the normal internal clock signal is transmitted to circuits operated on a rising edge of the internal clock signal and the inverted internal clock signal is transmitted to circuits operated on a falling edge of the clock signal.

[0022] FIG. 1 is a block diagram illustrating a conventional clock synchronization circuit;

[0023] FIG. 2 is a detailed circuit diagram illustrating a variable delay line of FIG. 1;

[0024] FIG. 3 is a simulation result diagram illustrating a timing of an internal clock signal in FIG. 1;

[0025] FIG. 4 is a block diagram illustrating a first clock synchronization circuit;

[0026] FIGS. 5aand 5bare detailed circuit diagrams respectively illustrating two variable delay lines of FIG. 4;

[0027] FIG. 6 is a simulation result diagram illustrating a timing of clock signals from the two variable delay lines and an internal clock signal of FIG. 4;

[0028] FIG. 7 is a block diagram illustrating a second clock synchronization circuit having a duty cycle control unit for controlling a duty cycle and a duty driving unit; and

[0029] FIG. 8 is a block diagram illustrating third clock synchronization circuits outputting a normal internal clock signal and an inverted internal clock signal.

[0030] Turning now to FIG. 4, the clock synchronization circuit includes a variable delay unit 10 having two variable delay lines 11 and 12 for respectively delaying an external clock signal EXCLK for a different delay time, a shift register unit 20 having two shift registers 21 and 22 for respectively controlling the two variable delay lines 11 and 12 of the variable delay unit 10 and a delay monitor 30. The circuit also includes a phase detecting unit 40 for comparing a phase of the external clock signal EXCLK with a phase of an internal clock signal INCLK, as well as a phase mixer 50 for mixing phases of two delay clock signals DCLKO and DCLKE from the two variable delay lines 11 and 12 of the variable delay unit 10. The circuit also includes a control unit 60 for controlling a phase mixing operation of the phase mixer 50 and a shift operation of the two shift registers 21 and 22 of the shift register unit 20.

[0031] Each of the two variable delay lines 11 and 12 of the variable delay unit 10 respectively delays the external clock signal EXCLK for a different delay time. The two variable delay lines 11, 12 output two delay clock signals DCLKO and DCLKE. The first variable delay line 11 delays the external clock signal EXCLK through a delay path of an odd number (2N-1) of unit delay cells DELOi, and outputs the delay clock signal DCLKO. The second variable delay line 12 delays the external clock signal EXCLK through a delay path of an even number (2N) of unit delay cells DELEi, and outputs the delay clock signal DCLKE. Accordingly, when all of the unit delay cells DELOi and DELEi have the same constitution, a phase difference between the two delay clock signals DCLKO and DCLKE from the two variable delay lines 11 and 12 is a delay time of one unit delay cell DELOi or DELEi.

[0032] The shift register unit 20 includes a shift control unit 23 for outputting control signals SHLO, SHRO, SHLE and SHRE for indicating which of the shift registers 21 and 22 must perform the shift operation using the output signals SHL and SHR from the phase detector 40 according to an output signal CON from the control unit 60.

[0033] The phase mixer 50 mixes the phase of the delay clock signal DCLKO from the first variable delay line 11 and the phase of the delay clock signal DCLKE from the second variable delay line 12, and outputs the internal clock signal having a phase between the phases of the two clock signals DCLKO and DCLKE.

[0034] The control unit 60 controls the operation of the phase mixer 50 by outputting a control signal PMC. Here, the control unit 60 sets up the control signals PMC so that the internal clock signal INCLK from the phase mixer 50 has a phase between the phases of the two delay clock signals DCLKE and DCLKO from the two variable delay lines 11 and 12. In addition, the control unit 60 controls the operation of the shift register unit 20 by outputting the control signal CON. When the phase difference between the internal clock signal INCLK from the phase mixer 50 and the external clock signal EXCLK is over the delay time of one unit delay cell DELOi or DELEi, one of the shift registers 21 and 22 of the shift register unit 20 performs the shift operation according to the control signal CON.

[0035] FIGS. 5aand 5bare detailed circuit diagrams respectively illustrating the two variable delay lines 11 and 12 of the variable delay unit 10 in the clock synchronization circuit of FIG. 4.

[0036] Referring to FIG. 5a, the first variable delay line 11 delays the external clock signal EXCLK through the delay path of the odd number of unit delay cells DELOi according to shift signals SHO1-SHON from the first shift register 21 of the shift register unit 20. That is, the two unit delay cells DELOi are shifted at a time according to the shift signals SHO1-SHON.

[0037] The first variable delay line 11 includes NAND gates NDO1-NDON for selectively outputting the external clock signal EXCLK according to the shift signals SHO1-SHON from the first shift register 21 of the shift register unit 20. The first variable delay line 11 also includes unit delay cells DELO1-DELO2N connected in series for delaying the external clock signal EXCLK selectively outputted by the NAND gates NDO1-NDON.

[0038] The odd unit delay cell DELO(2N−1) includes a NAND gate NDO1N for NANDing the output signal from the previous unit delay cell DELO(2N−2) and the output signal from the NAND gate NDON, as well as a NAND gate NDO2N for NANDing the power voltage VCC and the output signal from the NAND gate NDO1N.

[0039] The even unit delay cell DELO(2N−2) includes a NAND gate NDO3N for NANDing the output signal from the previous unit delay cell DELO(2N−3) and the power voltage VCC. The even unit delay cell DELO (2N−2) also includes a NAND gate NDO4N for NANDing the power voltage VCC and the output signal from the NAND gate NDO3N.

[0040] As depicted in FIG. 5b, the second variable delay line 12 delays the external clock signal EXCLK through the even number of unit delay cells DELEi according to shift signals SHE1-SHEN from the second shift register 22 of the shift register unit 20. That is, the two unit delay cells DELEi are shifted at a time according to the shift signals SHE1-SHEN.

[0041] The second variable delay line 12 includes NAND gates NDE1-NDEN for selectively outputting the external clock signal EXCLK according to the shift signals SHE1-SHEN from the second shift register 22 of the shift register unit 20. The second variable delay line 12 also includes unit delay cells DELE1-DELE2N connected in series for delaying the external clock signal EXCLK selectively outputted by the NAND gates NDE1-NDEN.

[0042] Here, the even unit delay cell DELE(2N−1) includes a NAND gate NDE1N for NANDing the output signal from the previous unit delay cell DELE(2N−2) and the output signal from the NAND gate NDEN, as well as a NAND gate NDE2N for NANDing the power voltage VCC and the output signal from the NAND gate NDE1N.

[0043] The odd unit delay cell DELE2N includes a NAND gate NDE3N for NANDing the output signal from the previous unit delay cell DELO(2N−1) and the power voltage VCC and a NAND gate NDE4N for NANDing the power voltage VCC and the output signal from the NAND gate NDE3N.

[0044] In operation, when it is presumed that the second signal SHO(N−1) of the output signals SHO1-SHON from the first shift register 21 of the shift register unit 20 has a high level and the other signals SHO1-SHO(N−2) and SHON have a low level in an early stage, the external clock signal EXCLK is delayed through a delay path from the third delay cell DELO(2N−3) to the last delay cell DELO(2N−1) to output the delay clock signal DCLKO to the phase mixer 50. When it is presumed that the second signal SHE(N−1) of the output signals SHE1-SHEN from the second shift register 22 of the shift register unit 20 has a high level and the other signals SHE1-SHE(N−2) and SHEN have a low level, the external clock signal EXCLK is delayed through a delay path from the fourth delay cell DELO(2N−3) to the last delay cell DELO2N to output the delay clock signal DCLKE to the phase mixer 50.

[0045] According to the control signal PMC from the control unit 60, the phase mixer 50 outputs the internal clock signal INCLK having a phase between the phases of the two delay clock signals DCLKO and DCLKE. Here, the phase difference between the two delay clock signals DCLKO and DCLKE transmitted to the phase mixer 50 is a delay time of the unit delay cell.

[0046] Therefore, the control unit 60 outputs the internal clock signal INCLK having a phase between the phases of the two input signals DCLKO and DCLKE according to the control signal PMC for determining the phase of the internal clock signal INCLK to be approximate to the phase of the first delay clock signal DCLKO or the phase of the second delay clock signal DCLKE.

[0047] The operation of the phase mixer 50 is defined by following Formula 1:

[0048] INCLK=DCLKO*(1−α)+DCLKE*α  Formula 1

[0049] Here, ‘α’ is determined by the control signal PMC from the control unit 60. When ‘α’ is increased, the internal clock signal INCLK has a phase approximately equal to the phase of the second delay clock signal DCLKE. When ‘α’ is decreased, the internal clock signal INCLK has a phase approximately equal to the phase of the first delay clock signal DCLKO.

[0050] The operation of the clock synchronization circuit when the phase of the external clock signal EXCLK is faster than that of the internal clock signal INCLK will now be explained.

[0051] First, when ‘α’ is set up to be zero (0) in Formula 1, the phase mixer 50 outputs the internal clock signal INCLK having the same phase as the first delay clock signal DCLKO. This condition is maintained until the phase of the internal clock signal INCLK is approximately equal to the phase of the external clock signal EXCLK to some extent.

[0052] Thereafter, when the phase of the internal clock signal INCLK is approximately equal to the phase of the external clock signal EXCLK to some extent, ‘α’ is gradually increased in Formula 1, so that the phase of the internal clock signal INCLK can be approximately equal to the phase of the second delay clock signal DCLKE. That is, the phase of the internal clock signal INCLK is minutely increased. Such a procedure is repeated until the phase of the internal clock signal INCLK is identical to the phase of the external clock signal EXCLK. Here, a value of ‘α’ is determined according to constitution of the phase mixer 50.

[0053] When the phase of the internal clock signal INCLK from the phase mixer 50 is increased to the phase of the second delay clock signal DCLKE by the control signal PMC from the control unit 60, namely when ‘α’ is one (1), if the phase of the internal clock signal INCLK is still faster than that of the external clock signal EXCLK, the control unit 60 outputs the control signal CON to shift left the first shift register 21 by the shift control unit 23 of the shift register unit 20. Therefore, the third control signal SHO(N−2) has a high level and the other control signals SHO1-SHO(N−3), SHO(N−1) and SHON have a low level to form a delay path from the fifth unit delay cell DELO(2N−5) to the last unit delay cell DELO(2N−1), thereby newly outputting the first delay clock signal DELCO. Here, the second delay clock signal DCLKE is delayed through the delay path of the second variable delay line 12 to output the second delay clock signal DCLKE.

[0054] Thereafter, the phase of the internal clock signal INCLK is minutely controlled according to the control signal PMC from the control unit 60. That is, ‘α’ is gradually decreased from ‘1’ so that the phase of the internal clock signal INCLK can be approximately the same as the phase of the first delay clock signal DCLKO. Accordingly, the internal clock signal INCLK is outputted with the minutely-increased phase. Such a procedure is repeated until the phase of the internal clock signal INCLK is identical to the phase of the external clock signal EXCLK.

[0055] Conversely, when the phase of the external clock signal EXCLK is slower than that of the internal clock signal INCLK, ‘α’ is set up to be one (1) in Formula 1 in an early stage, and thus the internal clock signal INCLK has the same phase as the second delay clock signal DCLKE. This condition is maintained until the phase of the internal clock signal INCLK is approximately equal to the phase of the external clock signal EXCLK to some extent.

[0056] When the phase of the internal clock signal INCLK is approximately the same as the phase of the external clock signal EXCLK to some extent, ‘α’ is gradually decreased in Formula 1 so that the phase of the internal clock signal INCLK can be approximately equal to the phase of the first delay clock signal DCLKO. That is, the internal clock signal INCLK is outputted with the minutely-decreased phase according to the control signal PMC from the control unit 60. This procedure is repeated until the phase of the internal clock signal INCLK is identical to the phase of the external clock signal EXCLK.

[0057] When the phase of the internal clock signal INCLK from the phase mixer 50 is identical to the phase of the first delay clock signal DCLKO according to the control signal PMC from the control unit 60, namely when ‘α’ is zero (0), if the phase of the internal clock signal INCLK is still slower than that of the external clock signal EXCLK, the control unit 60 outputs the control signal CON to shift right the second shift register 22 of the shift register unit 20 by the shift control unit 23 of the shift register unit 20. Therefore, the first control signal SHEN has a high level and the other control signals SHE1-SHE(N−1) have a low level to form a delay path from the second unit delay cell DELE(2N−1) to the last unit delay cell DELE2N, thereby newly outputting the second delay clock signal DCLKE.

[0058] Thereafter, the phase of the internal clock signal INCLK is minutely controlled according to the control signal PMC from the control unit 60. That is, ‘α’ is gradually increased from ‘0’ so that the phase of the internal clock signal INCLK can be approximately equal to the phase of the first delay clock signal DCLKO. Accordingly, the internal clock signal INCLK is outputted with the minutely-decreased phase. Such a procedure is repeated until the phase of the internal clock signal INCLK is identical to the phase of the external clock signal EXCLK.

[0059] When ‘α’ is one or zero in Formula 1 and the internal clock signal INCLK having the same phase as one of the delay clock signals DCLKO and DCLKE is outputted, the shift right or left is generated not in the variable delay line 11 or 12 outputting the delay clock signal DCLKO or DCLKE having the same phase as the internal clock signal INCLK but in the other variable delay line 11 or 12. As a result, jitter elements do not influence the internal clock signal INCLK having the same phase as the delay clock signal DCLKO or DCLKE.

[0060] FIG. 6 is a simulation result diagram illustrating timing of the two delay clock signals DCLKO and DCLKE and the internal clock signal INCLK. When the internal clock signal INCLK having the same phase as the second delay clock signal DCLKE is outputted, the shift is generated in time point ‘A’ in the first variable delay line 11.

[0061] As illustrated in FIG. 6, the shift is generated in the first variable delay line 11, and thus a jitter seriously affecting a period, phase and pulse width is shown in the waveform of the first delay clock signal DCLKO. However, the phase mixer 50 receives the second delay clock signal DCLKE, and outputs the internal clock signal INCLK. Therefore, a period, phase and pulse width of the internal clock signal INCLK are not influenced by jitter elements of the first delay clock signal DCLKO.

[0062] As shown in FIG. 7, a second clock synchronization circuit includes a variable delay unit 10 having two variable delay lines 11 and 12, a shift register unit 20 having two shift registers 21 and 22 and a delay monitor 30. The second clock synchronization circuit also includes a phase detecting unit 40, a phase mixer 50 and a control unit 60 as in the first clock synchronization circuit. The second clock synchronization circuit further includes the duty driving unit 70 for setting up a level ratio of the clock signal INCLK from the phase mixer 50 and a duty cycle control unit 80 for controlling a ratio of a duty driving unit 70.

[0063] The duty driving unit 70 sets up an identical time duration ratio in a high level period and a low level period of the clock signal INCLK from the phase mixer 50 according to a control signal DSC from the duty cycle control unit 80. That is, the duty driving unit 70 is driven so that a duty of the duty cycle of the internal clock signal INCLK can be 50%.

[0064] For example, when the internal clock signal INCLK has a frequency of 500 megahertz (MHz), if a period of one clock is 2 nanoseconds (ns) and the duty of the duty cycle is exactly 50%, the high level period and the low level period of the internal clock signal INCLK are each Ins.

[0065] The duty cycle is adjusted because the DDR SDRAM is operated both on a rising edge and a falling edge of the clock signal.

[0066] Except for the above-described operation, the second clock synchronization circuit operates in the same manner as the first clock synchronization circuit, and thus detailed explanations thereof will be omitted.

[0067] FIG. 8 is a block diagram illustrating third clock synchronization circuits 100 and 200 outputting a normal internal clock signal INCLK and an inverted internal clock signal/INCLK. As shown in FIG. 8, the normal internal clock generator 100 outputting the normal internal clock signal INCLK includes a variable delay unit having two variable delay lines, a shift register unit having two shift registers, a delay monitor; a phase detecting unit, a phase mixer and a control unit as in the first clock synchronization circuit. The inverted internal clock generator 200 outputting the inverted internal clock signal/INCLK includes a variable delay unit having two variable delay lines, a shift register unit having two shift registers, a delay monitor, a phase detecting unit, a phase mixer, and a control unit as in the first clock synchronization circuit. The inverted clock signal/EXCLK having the opposite phase to the external clock signal EXCLK is inputted to the variable delay unit of the inverted internal clock generator 200, and thus the inverted internal clock generator 200 outputs the inverted internal clock signal/INCLK having the opposite phase to the internal clock signal INCLK from the normal internal clock generator 100.

[0068] For example, when the DDR SDRAM is operated in a rising edge of the operation clock signal, the DDR SDRAM is enabled and driven in every rising edge according to the normal internal clock signal INCLK. When the DDR SDRAM is operated in a falling edge of the operation clock signal, the DDR SDRAM is enabled and driven in every rising edge according to the inverted internal clock signal /INCLK. Here, because the normal internal clock signal INCLK has the opposite phase to the inverted internal clock signal/INCLK, a clock signal can be enabled in the same manner as a clock signal having a duty ratio of 50% in a high level period and a low level period.

[0069] The normal internal clock generator 100 and the inverted internal clock generator 200 perform the identical operation to the clock synchronization circuit described above, and thus detailed operation explanations thereof will be omitted.

[0070] As noted earlier, the disclosed clock synchronization circuit generates the internal clock signal having a phase between the phases of the two clock signals generated in the two variable delay lines with a predetermined phase difference by using the phase mixer to precisely synchronize the clock signal. When the shift register for controlling the variable delay lines performs the shift operation, the output clock signal from the variable delay line where the shift operation is performed is not inputted to the phase mixer, but the output clock signal from the other variable delay line is inputted to the phase mixer. Accordingly, the jitter elements generated due to the shift operation do not influence the internal clock signal.

[0071] Moreover, the driving unit and the control unit for adjusting the duty cycle are provided to set up a duty cycle of 50%, thereby improving the operation performance. In addition, the internal clock signals for the rising edge timing and the falling edge timing are respectively generated to improve the operation performance. The disclosed apparatus precisely synchronizes a phase of an external clock signal with a phase of an internal clock signal, regardless of noise generated due to shift in delay lines of a clock synchronization circuit.

[0072] Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all embodiments of the teachings of the invention fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.