Structures with improved adhesion to Si and C containing dielectrics and method for preparing the same

[0002] 1. Field of the Invention

[0003] The present invention generally relates to a semiconductor electronic device structure comprising dielectric layers having improved adhesion to other dielectric or conducting layers. More particularly, the present invention relates to using a layer of amorphous silicon (a-Si) or amorphous Germanium (a-Ge) (or alloys thereof) as an adhesion enhancing interfacial layer. Furthermore, the present invention relates to a method for improving the adhesion between different dielectric or conductive layers including those that include Si or C.

[0004] 2. Description of the Prior Art

[0005] The continuous shrinking in dimensions of electronic devices utilized in ULSI circuits in recent years has resulted in increasing the resistance of the BEOL metallization as well as increasing the capacitance of the intralayer and interlayer dielectric. This combined effect increases signal delays in ULSI electronic devices. In order to improve the switching performance of future ULSI circuits, low dielectric constant (k) insulators and particularly those with k significantly lower than silicon oxide are being introduced to reduce the capacitances.

[0006] The low-k materials that have been considered for applications in ULSI devices include polymers containing Si, C, O and H, such as methylsiloxane, methylsilsesquioxanes, and other organic and inorganic polymers which are fabricated by spin-on techniques or, Si, C, O and H containing materials (SiCOH, SiOCH, carbon-doped oxides (CDO), silicon-oxicarbides, organosilicate glasses (OSG)) deposited by plasma enhanced chemical vapor deposition (CVD) techniques. The incorporation of the low-k dielectrics in the interconnect structures of integrated circuits (IC) often requires the use of other dielectric materials as diffusion barrier caps or etch-stop and chemo-mechanical polishing (CMP) hardmasks. The adhesion between the different layers in the complex structures of an IC device is often too low, resulting in delaminations during the processing of the device. This is especially true for adhesion of dielectric or metallic layers to SiO₂. Furthermore, an intermediate layer of refractory metal nitride is generally needed to provide suitable adhesion between the metallic Cu-diffusion barrier and the dielectric insulator of the interconnect structure. The conductive nitride layer, typically of lower conductivity than the metallization layers occupies a significant thickness of the shrinking metallization and increases its resistivity. The elimination of this conductive nitride layer by substituting it with a very thin adhesion layer can improve the performance of ULSI devices.

[0007] It would thus be highly desirable to provide a semiconductor device comprising an insulating structure including comprising a multitude of dielectric and conductive layers with good adhesion between the different layers, and a method for manufacturing said semiconductor device.

[0008] As described in U.S. Pat. No. 4,647,494, amorphous Silicon (a-Si) of tens of Angstroms thick has been recognized for improving adhesion of wear resistant carbon coatings to metallic magnetic recording layers in recording tapes and disks. That is, in U.S. Pat. No. 4,647,494, a-Si is described as improving adhesion between amorphous hydrogenated carbon (or diamondlike carbon) and silicide forming metals. The use of thin a-Si bonding layer has not been utilized in semiconductor ULSI manufacturing processes to enhance adhesion between dielectric layers of a semiconductor BEOL wiring structure.

[0009] It would thus be further highly desirable to provide a semiconductor device structure and method for manufacturing an insulating structure comprising a multitude of dielectric and conductive layers that includes thin a-Si, a-Ge or alloys thereof, bonding layers used to enhance adhesion between the different layers.

[0010] It is therefore an object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers with good adhesion between the different layers.

[0011] It is a further object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin bonding layer comprising amorphous Si (a-Si), amorphous Ge (a-Ge) or alloys thereof, wherein the thin a-Si (a-Ge or alloys thereof) may be hydrogenated or non-hydrogenated.

[0012] It is another object of the present invention to provide an insulating structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin amorphous bonding layer comprising amorphous Si (a-Si), amorphous Ge (a-Ge) or alloys thereof, wherein the thin a-Si (a-Ge or alloys thereof) may be at least partially oxidized.

[0013] It is another object of the present invention to provide an insulating structure including a thin intermediate a-Si (a-Ge or alloys thereof) bonding layer adhesion layer for enhancing adhesion between an oxide layer, e.g., from the group comprising SiO₂, phosphorus silicate glass (“PSG”) or boron phosphorus silicate glass (“BPSG”), and a layer from the group comprising SiCOH, SiC, SiCN, SiCH, or SiCNH.

[0014] It is yet another object of the present invention to provide an electronic device structure incorporating layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the adhesion between different dielectrics is enhanced by a thin intermediate a-Si bonding layer, or a bonding layer of a-Ge or alloys thereof.

[0015] It is still another object of the present invention to provide an electronic device structure incorporating layers of insulating and conductive materials as intralevel or interlevel dielectrics in a BEOL wiring structure in which the adhesion between the conductive layers and the different dielectric layers is enhanced by a thin intermediate a-Si bonding layer, or a bonding layer of a-Ge or alloys thereof.

[0016] It is still yet a further object of the present invention to provide a method for fabricating an a-Si adhesion layer (or a layer of a-Ge or alloys thereof) either in a parallel plate plasma enhanced chemical vapor deposition (“PECVD”) reactor or, in a sputtering reactor.

[0017] It is yet another object of the present invention to provide an electronic device structure, which comprises at least one a-Si bonding layer (or a layer of a-Ge or alloys thereof) between a dielectric layer and a liner/barrier layer for a Cu metallization structure.

[0018] It is another object of the present invention to provide an insulating semiconductor structure comprising a multitude of dielectric and conductive layers wherein the adhesion between different layers is enhanced by a thin amorphous Si (a-Si) bonding layer (or a layer of a-Ge or alloys thereof) which may be at least partially oxidized.

[0019] According to the principles of the invention, there is provided a method for fabricating a BEOL interconnect structure with improved adhesion between the layers of the structure. The present invention further provides an electronic device structure that incorporates a-Si layers (or layers of a-Ge or alloys thereof) between dissimilar layers in the structure to improve the adhesion between them. In one embodiment, a thin a-Si layer, 1-100 nm, preferably 2-6 nm thick, is interposed between a silicon oxide layer and a SiCOH layer, enhancing the adhesion between the two layers. In another preferred embodiment, the 1-100 nm, preferably 2-6 nm thick a-Si layer is interposed between a SiCOH dielectric layer and a layer of SiN, SiC, SiCH, or SiCHN, to enhance the adhesion between the layers. In yet another embodiment, the 1-100 nm, preferably 2-6 nm thick a-Si layer is interposed between a dielectric layer and a Ta layer, to enhance the adhesion between the two layers.

[0020] In yet another embodiment, the a-Si layer (or a layer of a-Ge or alloys thereof) is incorporated between any two layers from the group comprising SiO₂, PSG, BPSG, SiN, SiC, SiCH, SiCHN, or SiCOH, Ta, Ti, and any other silicide forming metal, to improve the adhesion between the layers.

[0021] In an embodiment, the a-Si layer (or a layer of a-Ge or alloys thereof) is deposited after the hardmask layer which may be comprised of SiO₂, PSG, BPSG, SiN, SiC, SiCH or SiCHN which is then followed by the liner material such as Ta, Ti, W or their nitrides or silicides. The a-Si layer allows for the pure form of the metal to be deposited without concern for delamination on the metal/hardmask interface during CMP. The further benefit of depositing the pure metal is found at the via/line interface where pure metallic bonding is created which guarantees good adhesion and improves device reliability especially for thermal excursions and also has the added benefit of reducing contact resistance.

[0022] In another aspect of the invention, there is provided a method for fabricating a multilayered structure with strong adhesion between the different layers comprising the steps of: providing a plasma enhanced chemical vapor deposition (“PECVD”) reactor: positioning an electronic device structure (i.e., substrate) having an upper layer of first dielectric in the reactor; flowing SiH₄or SiH₄diluted in an inert gas into the reactor; depositing a layer of a-Si on top of said substrate; flowing precursors into the reactor for depositing a second dielectric or conductive layer on top of the a-Si bonding layer. The second dielectric layer is preferably a SiCOH type dielectric of low dielectric constant (k<3.2) or ultralow dielectric constant (k<2.4) or a metal such as Ta, Ti, W, combinations of the previous, their silicides and/or nitrides.

[0023] In another embodiment, the step of depositing the a-Si adhesion layer (or a layer of a-Ge or alloys thereof) is repeated after the deposition of said second layer.

[0024] In yet another embodiment the a-Si layer (or a layer of a-Ge or alloys thereof) is at least partially oxidized by exposing it to an oxygen plasma after its deposition.

[0025] In a different embodiment, the substrate is removed from the PECVD reactor after the deposition of the a-Si layer and a said second dielectric layer from the group comprising organic polymers, silicon based polymers, organic glasses, hybrid Si and C containing polymers, oxides, or porous modifications of same materials is deposited by a spin-on method.

[0026] In yet a different embodiment, the substrate is removed from the PECVD reactor after the deposition of the a-Si layer and after exposing the a-Si layer to an oxygen plasma and a second dielectric layer from the group comprising organic polymers, silicon based polymers, organic glasses, hybrid Si and C containing polymers, oxides, is deposited by a spin-on method.

[0027] Dielectric layers such as ones aforementioned, or layers of metals that form silicides have good adhesion to the a-Si interlayer, therefore the a-Si intermediate layer enhances the adhesion between such layers. The a-Si can be deposited by any radiation assisted techniques, such as PECVD, high density plasma, sputtering, ion beam sputtering, ion beam deposition.

[0028] The adhesion enhancing a-Si layer can be used in the back end of the line (BEOL) structure of a CMOS device to improve the adhesion between a low-k dielectric, e.g. SiCOH, and SiO₂or between a metal layer, e.g. Ta, and a dielectric.

[0029] The present invention is further directed to an electronic device structure which has layers of insulating materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) interconnect structure which includes a pre-processed semiconducting substrate that has a first region of metal embedded in a first layer of insulating material, a first region of conductor embedded in a second layer of insulating material, an adhesion layer of a-Si (or a layer of a-Ge or alloys thereof) between the second layer of insulating material and first layer of insulating material, the first region of conductor being in electrical contact with the first region of metal, and a second region of conductor being in electrical contact with the first region of conductor and being embedded in a third layer of insulating material, the third layer of insulating material contacting with the second layer of insulating material. The electronic device structure may further comprise a dielectric cap layer situated in between the second layer of insulating material and the third layer of insulating material and including a-Si adhesion layers between the cap layer and the second and optionally the third insulating layers.

[0030] The electronic device structure may further comprise a first dielectric cap layer between the second layer of insulating material and the third layer of insulating material, and a second dielectric cap layer on top of the third layer of insulating material and containing a-Si adhesion layers between the cap layers and the insulating layers.

[0031] The dielectric cap material can be selected from silicon oxide, silicon nitride, silicon oxynitride, a refractory metal silicon nitride (wherein the refractory metal is selected from the group consisting of Ta, Zr, Hf and W) silicon carbide, carbon doped oxide or SiCOH and their hydrogenated compounds. The first and the second dielectric cap layers may be selected from the same group of dielectric materials. The first layer of insulating material may be silicon oxide or silicon nitride or doped varieties of these materials, such as phosphorus silicate glass (“PSG”) or boron phosphorus silicate glass (“BPSG”), SiC, SiCN, SiCH, or SiCNH. The second and subsequent dielectric layers may be PECVD deposited SiCOH or spin-on deposited dielectrics.

[0032] The electronic device structure may further include a diffusion barrier layer of a dielectric material deposited on at least one of the second and third layers of insulating material with an a-Si intermediate adhesion layer (or an adhesion layer of a-Ge or alloys thereof). The electronic device structure may further comprise a dielectric on top of the second layer of insulating material, which acts as a reactive ion etch (“RIE”) hard mask and polish stop layer and a dielectric diffusion barrier layer on top of the dielectric RIE hard mask and polish stop layer, with an a-Si intermediate adhesion layer between said top dielectric and said second layer of insulating material. The electronic device structure may further comprise a first dielectric RIE hard mask/polish-stop layer on top of the second layer of insulating material, a first dielectric RIE hard mask/diffusion barrier layer on top of the first dielectric polish-stop layer, a second dielectric RIE hard mask/polish-stop layer on top of the third layer of insulating material, and a second dielectric diffusion barrier layer on top of the second dielectric polish-stop layer with a-Si adhesion layers between two layers of different materials. The electronic device structure may further comprise a dielectric cap layer of same materials as mentioned above, between an interlevel dielectric and an intralevel dielectric.

[0033] Advantageously, the method for improving the adhesion between the different layers of an electronic device structure using the a-Si adhesion layer is implemented in a back-end-of-the-line (“BEOL”) wiring process. Thus, the electronic device structure comprises at least one a-Si bonding layer between the dielectric and conductive layers of a back-end-of-the-line (“BEOL”) wiring structure.

[0034] The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which:

[0035] FIG. 1 depicts an enlarged, cross-sectional view of an electronic device having two layers of metallization in the BEOL according to the current state of the art.

[0036] FIG. 2 depicts the structure of FIG. 1 with an additional a-Si adhesion layers between the dielectrics of the two mettalization levels according to the present invention.

[0037] FIG. 3 depicts an enlarged, cross-sectional view of the electronic device structure of FIG. 2 having an additional diffusion barrier dielectric cap layer on top of the intralevel dielectric and a-Si adhesion layers between the diffusion barrier and the intralevel and interlevel dielectrics according to the present invention.

[0038] FIG. 4 depicts an enlarged, cross-sectional view of the electronic device structure of FIG. 3 having an additional RIE hard mask/polish-stop dielectric cap layer and dielectric cap diffusion barrier on top of the polish-stop layer with a-Si adhesion layers between the different dielectric layers according to the present invention.

[0039] FIG. 5 depicts an enlarged, cross-sectional view of the electronic device structure of FIG. 4 having additional RIE hard mask/polish-stop dielectric layers on top of the interlevel dielectric material film with a-Si adhesion layers between the different dielectric layers according to the present invention.

[0040] FIG. 6 depicts an enlarged, cross-sectional view an electronic device structure having a-Si adhesion layers between the hard mask/polish-stop and barrier metal layer according to the present invention.

[0041] The present invention discloses a structure with improved adhesion between different layers of insulating or conductive materials, with thin a-Si adhesion layers disposed between the different layers, or alternately thin layers of amorphous Germanium (a-Ge) or alloys thereof. For purposes of discussion, a-Si will be described, however it is understood that the adhesion layer material may comprise a-Si, a-Ge or alloys thereof.

[0042] The present invention provides a method for improving the adhesion between different layers of insulating or conductive materials using thin a-Si bonding layers between each of the different layers.

[0043] The thin amorphous Si (a-Si) bonding layer may be used to improve the adhesion between an organic dielectric and a Si-based dielectric such as silicon oxide, silicon nitride, SiCOH, SiCH, SiCNH, or between any two dielectric layers from the group comprising the aforementioned organic and Si based dielectrics. The dielectric layers may be the main interconnect dielectric, a cap, or a hard mask layer in the back end of the line interconnect structure of an integrated circuit. While a-Si is not a low-k material, it is formed as a very thin layer as compared to the thickness of the dielectric layers, therefore its contribution to the effective dielctric constant is negligible. Furthermore, a large fraction of the a-Si layer is intermixed with the layers which it is bonding and thus converted into layers of dielectric constants smaller than a-Si. The a-Si bonding layer may also be used to improve the adhesion between a metal or metal nitride and any dielectric layer from the aforementioned group.

[0044] The electronic devices formed according to the present invention are shown in FIGS. 2-6. It should be noted that the devices shown in FIGS. 2-6, are merely illustrated as examples according to the present invention, while countless other devices can also be formed according to the present invention.

[0045] FIG. 1 depicts electronic device 30 that is built on a silicon substrate 32 according to the current state of the art. On top of silicon substrate 32, insulating material layer 34 is formed with a first region of metal 36 embedded therein. After a chemical mechanical polishing (“CMP”) process is conducted on first region of metal 36, a film such as a dielectric film 38, having preferably a dielectric constant smaller than SiO₂, is deposited on top of first layer of insulating material 34 and first region of metal 36.

[0046] First layer of insulating material 34 may be suitably formed of silicon oxide, silicon nitride, doped varieties of these materials, or any other suitable insulating materials. Dielectric film 38 is patterned by a photolithography process and conductor layer 40 is deposited therein. After a CMP process on first conductor layer 40 is carried out, second layer of dielectric film 44 is formed overlying first dielectric film 38 and first conductor layer 40. Conductor layer 40 may be deposited of a metallic conductive material or a non-metallic conductive material. For instance, a metallic conductive material of aluminum or copper, or a non-metallic material such as nitride or polysilicon may be utilized. The first conductor 40 is in electrical communication with the first region of metal 36.

[0047] As further depicted in FIG. 1, a second region of conductor 50 is formed after a photolithographic process in the second dielectric film layer 44, followed by a process for depositing the second conductor material. Second conductor 50 may also be deposited of either a metallic material or a non-metallic material, similar to that used in depositing the first conductor layer 40. The second region of conductor 50 is in electrical communication with the first region of conductor 40 and is embedded in the second layer of dielectric insulator 44. The second layer of dielectric film 44 is in intimate contact with the first layer of insulating material 38. In this specific example, the first layer of insulating material 38, which is a dielectric material according to the present invention, serves as an intralevel dielectric material, while the second layer of insulating material, i.e., the dielectric film 44, serves as both an intralevel and an interlevel dielectric. Based on the low dielectric constant of the dielectric film, superior insulating property can be achieved by first insulating layer 38 and second insulating layer 44.

[0048] FIG. 2 depicts electronic device 130 that is built on a silicon substrate 32 according to the present invention. After the formation of insulating material layer 34 with the embedded first region of metal 36, a thin layer 100 of a-Si, 1-100 nm thick, preferably 2-6 nm thick, is formed on top of layers 34 and 36. The process then continues as described with reference to FIG. 1.

[0049] FIG. 3 depicts electronic device 60 according to the present invention, similar to that of electronic device 130 shown in FIG. 2, but with additional dielectric cap layer 62 deposited between first insulating material layer 38 and second insulating material layer 44. Dielectric cap layer 62 can be suitably formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-oxide (SiCO), modified SiCOH and their hydrogenated compounds, as well as refractory metal silicon nitride, wherein the refractory metal is selected the group consisting of: Ta, Zr, Hf, and W. Additional dielectric cap layer 62 functions as a diffusion barrier layer for preventing diffusion of first conductor layer 40 into second insulating material layer 44. In one embodiment of the present invention, the adhesion between cap layer 62 and dielectric layer 38 is enhanced by the a-Si layer 102. In another embodiment, the adhesion between dielectric layer 44 and cap layer 62 is enhanced by the a-Si layer 104. In yet another embodiment the adhesion between cap layer 62 and dielectric layer 38 is enhanced by the a-Si layer 102 and the adhesion between dielectric layer 44 and cap layer 62 is enhanced by the a-Si layer 104.

[0050] FIG. 4 depicts another alternate embodiment of electronic device 70 according to the present invention. In electronic device 70, two additional dielectric cap layers 72 and 74 that act as an RIE mask and CMP (chemical-mechanical polishing) polish stop layer are used. First dielectric cap layer 72 is deposited on top of first insulating material layer 38. The function of dielectric layer 72 is to provide an end point for the CMP process utilized in planarizing first conductor layer 40. Polish stop layer 72 can be deposited of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-oxide (SiCO), modified SiCOH and their hydrogenated compounds, as well as refractory metal silicon nitride, wherein the refractory metal is selected from the group consisting of: Ta, Zr, Hf, Ti and W. The top surface of dielectric layer 72 is at the same level as first conductor layer 40. In one embodiment, the adhesion between cap layer 72 and dielectric layer 38 is enhanced by the a-Si layer 106. In another embodiment, the adhesion between dielectric layer 62 and cap layer 72 is enhanced by the a-Si layer 102. In yet another embodiment the adhesion between cap layer 72 and dielectric layer 38 is enhanced by the a-Si layer 106 and the adhesion between dielectric layer 62 and layer 72 is enhanced by the a-Si layer 102.

[0051] A second dielectric layer 74 can be added on top of second insulating material layer 44 for the same purposes. In one embodiment, the adhesion between layer 74 and dielectric layer 44 is enhanced by the a-Si layer 108.

[0052] FIG. 5 depicts still another alternate embodiment of electronic device 80 according to the present invention. In this alternate embodiment, an additional layer of dielectric 82 is deposited and thus divides second insulating material layer 44 into two separate layers 84 and 86. Intralevel and interlevel dielectric layer 44, as depicted in FIG. 3, is therefore divided into interlayer dielectric layer 84 and intralevel dielectric layer 86 at the boundary between interconnect 92 and interconnect 94, as depicted in FIG. 5. An additional diffusion barrier layer 96 is further deposited on top of the upper dielectric layer 74. The additional benefits provided by this alternate embodiment of the electronic structure 80 is that the dielectric layer 82 acts as a RIE etch stop providing superior interconnect depth control. In one embodiment, the adhesion between layer 82 and dielectric layer 84 is enhanced by the a-Si layer 110. In another embodiment, the adhesion between layer 86 and layer 82 is enhanced by the a-Si layer 112. In yet another embodiment the adhesion between cap layer 82 and dielectric layer 84 is enhanced by the a-Si layer 110 and the adhesion between dielectric layer 86 and layer 82 is enhanced by the a-Si layer 112. In another embodiment the adhesion between the diffusion layer 96 and dielectric layer 74 is enhanced by the a-Si layer 114. In yet another embodiment the adhesion between dielectric 74 and intralevel dielectric 86 is enhanced by the a-Si layer 108.

[0053] FIG. 6 depicts still another alternate embodiment of electronic device 90 according to the present invention. In this alternate embodiment, an a-Si layer 240 is deposited and thus separates dielectric layer 44 from metal barrier layer 206. The additional benefits provided by this alternate embodiment of the electronic structure 90 is that the barrier layer 206 may be a pure metal such as Ta, W or Ti rather than a nitrided form of the metal. This allows for reduced contact resistance between the via 225 and underlying line 210 at the contact area 245 and provides increased adhesion between dielectric layer 34 and metal cap layer 220 via the remaining a-Si layer 215 present after CMP of the metal barrier layer 216.

[0054] In any of said embodiments the a-Si layer may be at least partially oxidized, for example by a short exposure to an oxygen plasma.

[0055] According to the invention, there is provided a method for fabricating the multilayered structures with strong adhesion between the different layers such as shown and described with respect to FIGS. 2-6. A preferred method comprises the steps of: providing a plasma enhanced chemical vapor deposition (“PECVD”) reactor: positioning an electronic structure (e.g., semiconductor substrate) having an upper layer of first dielectric in the reactor; flowing SiH₄or SiH₄diluted in an inert gas into the reactor; depositing a layer of a-Si on top of said substrate; flowing precursors into the reactor for depositing a second dielectric or conductive layer on top of the a-Si bonding layer. It is understood that GeH₄or GeH₄diluted in an inert gas may be flown into the reactor, or alternatively, mixtures of SiH₄or diluted SiH₄with GeH₄or diluted GeH₄may be flown into the reactor. The second dielectric layer is preferably a SiCOH type dielectric of low dielectric constant (k<3.2) or ultralow dielectric constant (k<2.4), or a metal such as Ta, Ti, W, and combinations of the aforementioned, their nitrides and silicides.

[0056] The following examples are presented to illustrate the fabrication of the dielectric film including the a-Si bonding layer in accordance with the present invention as well as to demonstrate advantages that can be obtained therefrom:

[0057] In this example, a wafer containing an electronic structure (i.e., substrate) having an upper layer of first dielectric with metal structures embedded in it is inserted in a plasma enhanced chemical vapor deposition (“PECVD”) reactor. The wafer is then heated to a temperature between room temperature and 450° C. In typical conditions, the wafer is heated to 180° C. SiH₄or SiH₄diluted in inert gas is then flown into the reactor. In one example SiH₄diluted to 2% in Ar is flown into the reactor at a rate of 30 sccm to achieve a pressure of 100 mtorr. It is understood that GeH₄or GeH₄diluted in an inert gas may be alternately flown into the reactor, or alternatively, mixtures of SiH₄or diluted SiH₄with GeH₄or diluted GeH₄may be flown into the reactor. An RF power source is then turned on to about 60.0 W for 0.5 to 2 minutes. In a different example, the RF power generated is operated under bias control and the a-Si layer (a-Ge or alloy thereof) is deposited at the same conditions as mentioned above but at −200 V instead of 60 W. The RF power and the gas flow are then turned off. The substrate temperature may optionally be adjusted, and the precursors used for the deposition of the next dielectric layer flown into the reactor so that the next film may be deposited.

[0058] In a different example, the wafer is removed from the reactor after the deposition of the a-Si layer and the wafer is further processed by depositing a spin-on dielectric layer.

[0059] In yet another example, after the deposition of the a-Si layer, oxygen gas is flown into the reactor and the RF power is turned on for 3 to 15 seconds to oxidize the a-Si layer at least partially.

[0060] Qualitatively, the adhesion provided by the thin a-Si bonding layer is strong enough to prevent delamination of the interconnect structure during fabrication and reliability testing. In one example, as determined in a four-point bending test known amongst skilled artisans, adhesion between two layers has been demonstrated to increase by a factor of three (3), from about 6.0 joule/m²to about 20.0 joule/m².

[0061] The method and electronic structures formed according to the present invention have therefore been thoroughly demonstrated in the above descriptions and in the drawings of FIGS. 1-6. It should be emphasized that the examples of the electronic structures shown in FIGS. 1-6 are merely used to illustrate the inventive method that can be applied in the fabrication of countless electronic devices.

[0062] While several embodiments of the invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.