Magnetic disc device and error correction method therefor

[0002] The invention relates to a magnetic disc device for use as an auxiliary storage or memory means for computers and to a method of correcting erroneous data pertinent to such disc device.

[0003] Automated electronic apparatuses including personal computers (PC) and office computers have been down sized and functionally enhanced very quickly supported by a recent progress in technology, which has in turn prompted development of compact yet fast and large-capacity memory devices or file systems such as a 5.2 inch, 3.5 inch, and 2.5 inch hard disc drives.

[0004] An effort has been paid to improve the density of data recorded on a magnetic disc and to increase the rotational speed of the spindle of the magnetic disc, to thereby improve the data transfer rate to and from a magnetic disc device. It is known that the level of the data which is reproduced or read from the magnetic disc by a magnetoresistive (MR) head does not depend on the linear speed or the rotational speed of the disc, so that the MR head can maintain a high signal level while reading data. Therefore, the MR head has become increasingly more important in this field.

[0005] It should be noted, however, that the MR head is maintained afloat while it is reading data only 30-50 nm above the magnetic medium due to a negative pressure acting on the MR head. Prior to read operation, the magnetic head is at rest on the surface of the magnetic disc, which is also at rest. If the magnetic disc has a very flat surface like a mirror, the head would stick to the surface of the disc and would remain captured by the magnetic disc even after the magnetic disc had started its rotation. In order to prevent such capture, the magnetic disc is provided on the surface thereof with minute protrusions formed by an appropriate surface roughening or texturing technique.

[0006] However, such roughening process can form a small number of unexpectedly large protrusions on some tracks on the magnetic disc. The magnetic head will then bump on such large protrusions every time the head passes over the tracks. Collisions of the head with the magnetic disc can also take place when the magnetic disc is heated during read/write operations and the surface of the disc gets deformed, or when the head is thermally deformed, or when the entire magnetic device is subjected to a strong mechanical shock during the operations.

[0007] When such a collision takes place, the MR head is temporarily heated for a few microseconds. The resistance of the heated MR head is changed accordingly.

[0008] During a read operation the MR head undergoes a relative motion over the magnetic disc while passing a constant electric current through the magnetoresistive element thereof. The magnetoresistive element changes its resistance if a magnetic field externally applied thereto is changed. Hence, the MR head can read magnetically recorded information on the disc in the form of the voltage change across the magnetoresistive element by detecting the change in resistance of the magnetoresistive element. Therefore, if the head collides with a bump or protrusion formed on the disc, the head is temporarily heated and its resistance is changed. This results in a corresponding change in voltage and errors in the information reproduced (i.e. read) from the magnetic disc. Such transient voltage change (which lasts for a few microseconds) can result in erroneous data as much as several tens of bytes.

[0009] When such a transient thermal event as mentioned above occurs, there will be a transient waveform or a DC bias in the output of the head, which smears the data read from the disc, and makes the data unrecoverable in a subsequent decoding stage, thereby resulting in unrecoverable read errors. This type of errors observed in MR heads is called TA or thermal asperity.

[0010] A strategy well known in the art to avoid thermal asperity is to use a high pass filter (HPF) in a data decoding circuit to cut off low-frequency components of the signal reproduced so as to suppress generation of a transient waveform and promote quick convergence of the disturbed signal. An alternative approach known in the art to hold the reproduced signal is to provide either an automatic gain control (AGC) circuit which causes the data decoding circuit to hold the amplitude of the reproduced signal for a moment or a phase locked loop (PLL) circuit which temporarily prohibits the reproduced signal to follow the DC bias and become out of phase with a clock.

[0011] A further technique is known to deal with errors that cannot be corrected by the circuits as mentioned above, which is adapted to recover correct data by means of a circuit, called ECC circuit, provided in the decoding circuit for executing so-called error correction codes (ECC) on the fly.

[0012] However, most recent magnetic disc devices have much higher data transfer rates than conventional ones that the amount of data that will be lost due to thermal asperity if it occurs often exceeds the data length that can be corrected by the ECC circuit.

[0013] For example, the data length correctable by an ECC circuit is estimated to be at most about 9 bytes for an average magnetic disc device, and at most 20 bytes for a most advanced magnetic disc device. The duration of a thermal asperity is of order of a few microseconds, which corresponds to a loss of data of about several tens bytes, which exceeds the error correction ability of the today's ECC circuit, and hence the ECC circuit cannot deal with such errors.

[0014] It is, therefore, an object of the invention to provide an erroneous data correction device which may determine the location and the length of errors in the data reproduced or read from a magnetic recording medium.

[0015] It is another object of the invention to provide a method which may determine the location and the length of errors in the data read from a magnetic recording medium.

[0016] It is a further object of the invention to provide a magnetic disc device including an MR head having an MR element for reading data from the magnetic recording disc, the magnetic disc device equipped with means for detecting read errors introduced in the data by a sudden change in electric resistance of the MR element caused by a short collision of the MR head with the magnetic recording disc.

[0017] It is a still further object of the invention to provide a magnetic disc device which is equipped, in addition to means for detecting read errors mentioned above, with data recovery means for recovering the data lost by the errors.

[0018] It is a still further object of the invention to provide a method for detecting erroneous data involved in the foregoing magnetic disc device.

[0019] It is a still further object of the invention to provide a method for detecting and correcting erroneous data involved in the foregoing magnetic disc device.

[0020] In accordance with one aspect of the invention there is provide an erroneous data correction device, comprising:

[0021] a comparator which compares a first signal indicative of data read from a magnetic recording medium (referred to as data or data signal) and input thereto with a second signal having a predetermined threshold level (referred to as threshold signal) input thereto, for generates an output when the level of the data signal exceeds the threshold signal; and

[0022] an error signal generation circuit for generating an error signal using the output of the comparator and the data signal.

[0023] This error signal generation circuit device may include means for determining the location of erroneous data included in the data signal, using the error signal.

[0024] The erroneous data includes a transient waveform generated mainly by thermal asperity.

[0025] In the erroneous data correction device, the error signal generation circuit is adapted to select either one of the output of the comparator circuit, the data signal obtained from the magnetic recording medium, or a logical sum of the data signal and the comparator output, and outputs the selected signal as the error signal.

[0026] The erroneous data correction device may further include a counter circuit which has input ends for receiving the error signal and a read clock signal. The counter counts up read clock from the beginning of the data. The location of an erroneous data in the data may be obtained from the count up to the occurrence of an error signal. In addition, the erroneous data correction device may further include a register circuit connected with the counter circuit.

[0027] The erroneous data correction device may determine the length of the erroneous data included in the data based on the error signal.

[0028] The erroneous data correction device may have a further counter which receives the error signal from the error signal generation circuit and a read clock signal from a clock and counts the read clock over the period that the error signal is generated. Thus, the length of the erroneous data may be determined from the count.

[0029] An alternative error signal may be generated by another means of the invention which includes

[0030] a data reproduction circuit for reproducing data read from the magnetic recording disc; and

[0031] a decoder for use in the data reproduction circuit for performing a data format transformation on the bits of the reproduced data in accordance with a given set of run length rules to generate an error signal.

[0032] In this case the decoder may employ zero run-length rules in the form of 8/9 (0, n/m) data format.

[0033] In accordance with another aspect of the invention, there is provide an data error correction device, comprising:

[0034] a comparator which compares a first signal indicative of data read from a magnetic recording medium (data signal) and input thereto with a second signal having a predetermined threshold level (threshold signal) input thereto, for generating an output when the level of the data signal exceeds the level of the threshold signal; and

[0035] an error signal generation circuit for generating a first error signal using the output of said comparator and said data signal;

[0036] a decoder for use in the data reproduction circuit for performing a data format transformation on the bits of the reproduced data;

[0037] means for generating a second error signal based on the run-length rules imposed on said reproduced data; and

[0038] means for selecting either one of the first and the second error signals.

[0039] A magnetic disc device may include any of the erroneous data correction devices as described above.

[0040] In a still further aspect of the invention, there is provided a magnetic disc device, comprising:

[0041] a decoding circuit for decoding signals using partial response maximum likelihood technique;

[0042] a comparator for generating an output signal when the level of the data signal reproduced from the magnetic disc exceeds a predetermined threshold level;

[0043] means for determining the location and the length of erroneous data included in the data decoded by the decoder using the output of the comparator and decoded data;

[0044] hardware means for executing hardware ECC on-the-fly on the erroneous data; and

[0045] software means for executing software ECC on the erroneous data; and

[0046] means for choosing the hardware ECC correction means when the length of the erroneous data is longer than the length correctable by the hardware means, but otherwise choosing the software means.

[0047] In a still further aspect of the invention, there is provided a magnetic disc device, comprising:

[0048] a decoding circuit for decoding signals using partial response maximum likelihood technique;

[0049] a decoder for use in the data reproduction circuit for performing a data format transformation on the bits of the reproduced data;

[0050] means for generating an error signal based on the run-length rules imposed on said reproduced data;

[0051] means for determining the location and the length of the erroneous data based on the error signal output from the error signal generation means and the data decoded by the decoding circuit using partial response maximum likelihood technique;

[0052] hardware means for executing hardware ECC on-the-fly on the erroneous data; and

[0053] software means for executing software ECC on the erroneous data; and

[0054] means for choosing the hardware ECC correction means when the length of the erroneous data is longer than the length correctable by the hardware means, but otherwise choosing the software means.

[0055] In a still further aspect of the invention, there is provided an error correction method comprising steps of:

[0056] comparing a data signal reproduced from a magnetic disc with a predetermined threshold signal to generate an output signal when the level of the data signal exceeds the level of the threshold signal;

[0057] generating an error signal associated with the erroneous data included in the data signal based on the output signal and the data signal; and

[0058] determining the location and the length of the erroneous data based on the error signal.

[0059] In a still further aspect of the invention, there is provided an error correction method of the invention, comprising steps of:

[0060] determining the location and the length of erroneous data included in data signal reproduced from a magnetic disc;

[0061] determining whether said erroneous data has a length correctable by ECC on the fly;

[0062] executing ECC on the fly on the erroneous data when ECC on the fly is applicable; and

[0063] otherwise executing software ECC on the erroneous data.

[0064] FIG. 1 is a block diagram representation of a magnetic disc device according to the invention.

[0065] FIG. 2 is a block diagram of an error signal generation circuit of the magnetic disc device shown FIG. 1, for generating an error signal indicative of thermal asperity.

[0066] FIGS. 3A-D show formats of data recorded on the magnetic disc and a timing chart for signals appearing at various nodes of the data reproducing circuitry of FIG. 1, in which: FIG. 3A is a format of data on the magnetic disc 24; FIG. 3B a reproduced NRZ data, FIG. 3C a read clock RCLK, and FIG. 3D a read gate signal RG.

[0067] FIGS. 4A-B are a flow-chart showing a procedure for determining the starting location and the length of the erroneous data, and determining which of the error correction means be used.

[0068] FIG. 5 shows waveforms relevant in the detection and correction of the erroneous data caused by thermal asperity (TA), in which: FIG. 5A is a format of data on the magnetic disc; FIG. 5B shows a threshold signal Th and an analogue signal received from AGC amplifier and fed to a TA level comparator, FIG. 5B showing a transient component in the analogue signal subsequent to a TA event; FIG. 5C shows an output signal of the TA level comparator; FIG. 5D shows an NRZ data received from a 8/9 decoder and de-scrambler; FIG. 5E is a timing chart of read clock RCLK received from a PLL circuit; FIG. 5F shows a read gate signal RG; FIG. 5G shows an error signal output from an error signal generation circuit; and FIG. 5H shows an signal output from a counter circuit.

[0069] FIG. 6 shows the terminal arrangement of the counter circuit and a register circuit provided in a hard disc controller shown in FIG. 1.

[0070] FIG. 7A shows the format of data on the magnetic disc, FIG. 7B shows an NRZ data section of the reproduced data containing a multiplicity of errors, FIG. 7C shows rounding up of two errors 1 and 2 of FIG. 7B; FIG. 7D shows rounding up of three errors 1, 2, and 3 shown in FIG. 7B; and FIG. 7E indicates an error signal.

[0071] FIG. 8A is an example of data sequence having 8/9 (0, 4/4) format; FIG. 8B shows an even part of the sequence shown in FIG. 8A; FIG. 8C shows an odd part of the data shown in FIG. 8A; FIG. 8D shows a latch error signal; and FIG. 8E shows an output of a four-stage shift register.

[0072] An error correction method for correcting errors in data which is reproduced from a magnetic disc device and an apparatus therefor embodying the invention will now be described by way of example with reference to accompanying drawings, in which like reference numerals indicates like components throughout the drawings.

[0073] [Structure of the Magnetic Disc Device]

[0074] FIG. 1 shows in block diagram of an overall arrangement of a magnetic disc device according to the invention. The disc device shown herein is of type normally referred to as 3.5 inch hard disc drive, which is used as a server peripheral or auxiliary storage or memory for a personal computer (PC).

[0075] The magnetic disc device as shown in block diagram comprises:

[0076] a hard disc controller (HDC) 2 connected with a host computer (not shown) via an interface 1, for controlling a hard disc 24;

[0077] a micro controller unit (MCU) 7 for controlling mechanical motions of the magnetic disc device in performing read from/write operations to the magnetic disc 24; and

[0078] a disc enclosure (DE) 16 including in a closed casing thereof a magnetic disc 24 and a built-in read/write head 18. The disc enclosure 16 has connections for exchange of data with the hard disc controller 2 via read/write controller 14 and with MCU 7 via a VCM (voice coil motor)/spindle controller 15. All these components other than the disc enclosure 16 are each made up of a few LSIs mounted on a printed circuit board. In order to keep the components in a clean condition, the entire device is encased in a housing having a dust removing mechanism.

[0079] The data stored in the magnetic disc device may be transferred between the host computer (not shown) and the hard disc controller 2 by means of the 16-bit bus interface 1, which data is transformed into an 8 bit NRZ bus signal 22, which is further transformed by the read/write controller 14 into a 9-bit data which is appropriate for recording on the magnetic disc 24. The interface 1 may be a well known SCSI (Small Computer System Interface).

[0080] Each of the components shown in FIG. 1 will now be described below.

[0081] The hard disc controller (HDC) 2 has a data format controller 3, a host bus interface controller 4, and a data buffer controller 5, and an ECC controller 6.

[0082] The data formatting controller 3 receives data from the host computer (not shown) via the interface 1 and encodes the data in a form suitable to be recorded on magnetic disc 24. It also decodes the data read from the magnetic disc 24 into a form suitable for transferring it to the host computer via the interface 1. Although not shown in the FIG. 1, the data formatting controller 3 has a counter circuit 45 and a register circuit 46 which will be described shortly in connection with FIG. 3.

[0083] The host bus interface controller 4 controls the interface between the host computer and the magnetic disc device.

[0084] The data buffer controller 5 is connected with a RAM (random Access memory) 12 serving as a data buffer for temporarily storing the data sent from the magnetic disc 24 to the hard disc controller 2 before it is transferred to the host computer via the interface 1 at a proper time, or temporarily stores data received from the host computer via the interface 1 and directed to the hard disc controller 2 before it is sent to the disc enclosure 16 at an appropriate time later.

[0085] The ECC controller 6 is a conventional hardware error correction circuit, which is capable of correcting errors of at most 9-12 bytes (a newer type of advanced correction circuits can deal with much greater errors as much as 20 bytes). Therefore, magnetic disc devices using such error correction circuits cannot deal with errors that exceed 20 bytes.

[0086] In the error correction procedure carried out in the ECC controller 6, data generally are read in sequence from a magnetic disc and the errors found in the data are corrected on the fly by a hardware means. It is said that in such on-the-fly-error correction means if the total length of the data obtained in one read is “2X bytes”, the maximum error length correctable or the correction ability of the circuit is “X bytes”, so that errors that exceed “X bytes” in length cannot be corrected on the fly by the hardware means.

[0087] There is also a software correction means, called “software ECC”, which corrects errors by storing all the data of length “2X bytes” read from the magnetic disc 24 once in a RAM (not shown) and then performing error correction operation on the entire data using a software. The correction ability of the software ECC is 2X bytes.

[0088] Such software ECC can be advantageously performed if the location of the error (i.e. the number of the sectors up to the error in reference to the beginning of the data) and the length of the error(s) itself are known. However, during the ECC correction by the software, the hard disc must be idling (not usable) and withhold read operations, which can cause an overhead.

[0089] The microcontroller unit (MCU) 7 includes a signal control logic 9, a DC converter 10, an A/D converter 11, and a CPU 8 for controlling the entire magnetic disc device, all mounted on one LSI chip.

[0090] The CPU 8 also controls such components as the entire magnetic disc device a VCM drive 19 via the VCM/spindle controller 15, a spindle motor 20, as well as a multi-task operation and data correction operation as will be described in connection with FIG. 4. The CPU 8 is connected with a ROM (read only memory) 13 which stores a program for the CPU. The signal control logic 9 is provided to handle logical operations for the CPU 8.

[0091] The disc enclosure (DE) 16 has a base and a cover (not shown) for housing therein the magnetic disc 24 for magnetically recording information, a read/write head 18 for reading/writing information from/to the magnetic disc 24, a read/write pre-amplifier 17 for properly amplifying the signal exchanged between the disc 24 and the head 18 to a predetermined level, the spindle motor 20 for rotating a spindle on which the magnetic disc 24 is mounted, and a voice coil motor (VCM) 19 for positioning at a desired position (cylinder) on the magnetic disc 24 the head 18.

[0092] The magnetic disc 24 in the example shown herein includes 10 aluminum alloy discs each having thin magnetic layers formed on the opposite sides thereof and may store information up to 18 GB (giga-bytes). The read/write head 18 is a composite head which consists of a magnetoresistive (MR) head for read and an induction head for write. The pre-amplification stage 17 may amplify signals read by the read/write head 18 to a predetermined level. The spindle motor 20 is a DC brushless motor, which has a long life. The voice coil motor (VCM) 19 has a low inertial moment and a high torque characteristic so that it may quickly move the read/write head 18 to a desired position of the magnetic disc 24.

[0093] [Circuit Blocks for Generating Error Signal for TA]

[0094] FIG. 2 shows a block diagram of a circuit for generating an error signal when TA has occurred in the magnetic disc device. Blocks in the upper section of the circuit are related to a data reproducing circuit system and blocks in the lower section are related to a data reading circuit system. As shown in FIG. 1, the error signal generation circuit is associated with the magnetic disc (shown by a shaded block in FIG. 2) 24, the read/write head 18, the pre-amplification stage 17, and the read/write controller 14.

[0095] The read/write head 18 has an MR head 25 for reading or reproducing information from the magnetic disc 24.

[0096] The pre-amplification stage 17 has a preamplifier 27 for amplifying the read data received from the MR head 25.

[0097] The read/write controller 14 includes:

[0098] an automatic gain control (AGC) amplifier 29 for controlling the amplitude of a reproduced analogue signal received from the preamplifier 27;

[0099] a (1+D) filter 30;

[0100] a sampler and equalizer 31 for sampling analogue signal received from the (1+D) filter 30 and for correcting waveforms of the signal;

[0101] a Viterbi detection circuit 32 for making correction on the digital read data from the sampler and equalizer 31,

[0102] an 8/9 decoder and de-scrambler circuit 33 for decoding and de-scrambling the data received from the Viterbi detection circuit 32 to generate at its output end a non-return zero (NRZ) data 22;

[0103] a phase locked loop (PLL) 34 for providing read clock RCLK 41 to the AGC amplifier 29, the sampler and equalizer 31, the 8/9 decoder and de-scrambler 33 upon receipt of the digital read data received from the sampler and equalizer 31;

[0104] a thermal asperity level comparator 40 which receives an analogue signal from the AGC amplifier 29 and a predetermined threshold signal Th, and is turned ON to output a signal only when the absolute level of the read data exceeds the threshold;

[0105] an error signal generation circuit 35 for generating an error signal 23 in response to the output signal of the TA level comparator 40 and the NRZ data 22 received from the 8/9 decoder and de-scrambler 33.

[0106] A decoding circuit consisting of the (1+D) filter 30, the sampler and equalizer 31, and the Viterbi detection circuit 32 uses a class-4 PRML (partial response maximum likelihood) method, which is known as a procedure for detecting nontrivial data from read data. This PRML method employs a partial response method which can restore desired read data embedded in interfering signals, and a Viterbi decoding method which generates the most likely data from signals disturbed by noise.

[0107] The AGC amplifier 29 is a demodulation circuit for amplifying analogue signals received from the preamplifier 27 to a substantially constant level. The AGC amplifier 29 prevents the disturbance in amplitude of the amplified read data if thermal asperity should occur.

[0108] The (1+D) filter 30 consists of a low pass filter (LPF) and a booster circuit. The filter 30 receives the reproduced signal from the AGC amplifier 29 and feeds the reproduced signal back to the reproduced signal after it is delayed by 1 bit.

[0109] The sampler and equalizer 31 samples analogue signals reproduced from the magnetic disc 24 and casts the sampled data into either 1 or 0 to thereby generating digital read data.

[0110] The Viterbi detection circuit 32 performs the Viterbi decoding processing, which is a set of operations to find the most likely bits. The Viterbi detection circuit 32 can generally correct an error if the length the error is a few bit.

[0111] The 8/9 decoder and de-scrambler 33 transforms or converts 9 bit data generated by the sampler and equalizer 31 to 8 bit NRZ data and further de-scrambles the data scramblingly processed by the 8/9 encoder and scrambler 36.

[0112] The PLL circuit 34 generates a VCO clock which is in phase with the reproduced data received from the sampler and equalizer 31, and sends the clock signal to the AGC amplifier 29, the sampler and equalizer 31, the Viterbi detection circuit 32 and the 8/9 decoder and de-scrambler 33. The sampler and equalizer 31 uses this VCO clock signal as the sampling clock (which is also referred to as read clock). The 8/9 decoder and de-scrambler 33 uses both the PLL data synchronized with the VCO clock and the read gate signal RG 42 which rises within the sink region (which corresponds to the PLO of the data as shown in FIG. 3A) to decode the reproduced data. The 8/9 decoder and de-scrambler 33 transmits the decoded data as NRZ data to hard disc controller (HDC) 2 in synchronism with the read clock RCLK 41. The read gate signal RG 42 is indicative of the execution of a read operation, so that the read operation is detected when the hard disc controller 2 transmits a read gate signal RG 42.

[0113] In addition, in order to prevent asynchronization of the reproduced data with the clock due to thermal asperity, the PLL circuit 34 may temporarily hold synchronization of the data with the clock when thermal asperity has occurred.

[0114] Upon receipt of analogue read data from the AGC amplifier 29 and a threshold signal Th, the TA level comparator circuit 40 is turned ON, generating a TA level signal at its output end.

[0115] The error signal generation circuit 35 receives the output of the TA level comparator circuit 40 and the NRZ data from 8/9 decoder and de-scrambler 33 and then the error signal generation circuit 35 is activated (to ON state) to feed an error signal 23 to the counter circuit 45 of the hard disc controller (HDC) 2 for a period of time in which thermal asperity is appreciable.

[0116] In the example shown herein, an error signal 33 as shown in FIG. 5G is generated such that the error signal corresponds to either the signal output from the TA level comparator circuit 40 shown in FIG. 5C, an NRZ data which is partially destroyed due to thermal asperity as shown in FIG. 5D, or a logical sum (OR) of these signals. The error signal 33 thus formed is fed to the counter circuit 45 built in the hard disc controller 2.

[0117] Next, operations of the error signal generation circuit in write mode will now be described. In the write mode, the read/write controller 14 incorporates:

[0118] an 8/9 encoder and scrambler 36 which receives from a hard disc controller 2 an NRZ data 22, write gate signal WG, and a write clock WCLK to encode and scramble the NRZ data 22;

[0119] a precoder 37 for performing 1/(1+D) transformation on the signal received from the 8/9 encoder and scrambler 36;

[0120] a write compensation circuit 38 for compensating a write pulse received from the precoder 37, and

[0121] a write flip flop circuit 39 for receiving signal from the write compensation circuit 38 and for transmitting the signal to a write driver 28 of the pre-amplification stage 17.

[0122] In write mode the pre-amplification stage 17 incorporates a The write driver 28 provides an induction type write head 26 of the read/write head 18 with an electric current to write on the magnetic disc 24 data received from the write flip-flop circuit 39.

[0123] The 8/9 encoder and the scrambler 36 of the data recording circuit performs an operation which is the inverse of the operation of the 8/9 decoder and de-scrambler 33 in the recording circuit. That is, the 8/9 encoder and the scrambler 36 receives an NRZ data 22 to be written on the magnetic disc 24 from hard disc controller 2, a write gate signal WG and a write clock signal WCLK, and converts the 8 bit write data into 9 bit data and scrambles the 9 bit data.

[0124] The precoder 37 performs a 1/(1+D) transformation which is the inverse of the operation performed by the (1+D) filter 30 of the recording circuit.

[0125] The write compensation circuit 38 provides write compensation in which the write signal is delayed in write timing in order to compensate slow response of the magnetic disc which cannot keep up with the frequency of the write signal in reading the recorded data. This compensation may be attained by delaying the write timing by an amount of a few percent to several tens of percents. As a result, the write characteristic of the magnetic disc is modified to reduce the bit error rate.

[0126] Operation of the Magnetic Disc Device

[0127] Referring to FIG. 3, the read operation of the error signal generation circuit 35 associated with TA will now be described.

[0128] FIG. 3 shows a data format on the magnetic disc and a timing chart for various signals appearing in the data reproducing circuit: FIG. 3A shows the data format of a data recorded on the magnetic disc 24; FIG. 3B shows the data format of an NRZ data reproduced from the magnetic disc 24; FIG. 3C shows a read clock RCLK; and FIG. 3D shows timing of the read gate signal RG.

[0129] The magnetic disc 24 is formatted such that it is divided into a multiplicity of concentric regions (referred to as tracks) which are further divided into a multiplicity of subregions called sectors. Each of such sectors has a data format as shown in FIG. 3A. The sector has

[0130] a region PLO for drawing in the read clock;

[0131] a region TR for adjustment of the equalizer 31;

[0132] a Syc Bytes region SB indicating the completion of the drawing in the clock;

[0133] a data region DATA having data which was recorded via a write driver 28 on the magnetic disc 24,

[0134] an error correction code region ECC for detecting and correcting errors in the DATA region;

[0135] a cyclic redundancy check region CRC having a check code, belonging to the ID of sector, for use in error detection by the ECC, and

[0136] a gap region GAP provided between the end of sector and the next sector, which is adapted to absorb such fluctuations as the starting position of write on the disc, the rotational speed of the disc, and the length of the data written in the sector.

[0137] The magnetic disc 24 (FIG. 1) thus formatted and rotating at a constant speed generates signals in the form of varying magnetic field, which are detected by the MR head 25 of the read/write head 18. A signal indicative of data reproduced from the magnetic disc 24 is amplified by the preamplifier 27, with its amplitude adjusted by the AGC amplifier. The amplified analogue signal is then transformed into digital NRZ data 22 as shown in FIG. 3B by a class-4 PRML decoding circuit which consists of the (1+D) filter 30, the sampler and equalizer 31 and the Viterbi detection circuit 32. The digital NRZ data 22 is then fed to the hard disc 2.

[0138] In the PLL circuit 34, a read clock RCLK, which is in phase with the output of the sampler and equalizer 31, is generated from the reproduced data output from the sampler and equalizer 31 as shown in FIG. 5C. The read gate signal RG 42 has a rise within the same time domain as the PLO portion (FIG. 3A) for drawing in the clock and falls simultaneously with the NRZ data.

[0139] [Error Detection and Correction when TA has Occurred]

[0140] Referring now to a flow-chart shown in FIG. 4 and a timing chart for relevant signals shown in FIG. 5, error detection and correction operations of the circuit shown in FIG. 2 executed when a thermal asperity has occurred due to collision of the magnetic head with protrusions on the magnetic disc 24 will be described.

[0141] FIG. 4 shows in detail a procedure for locating the erroneous data, finding the length of the error, and determining steps to correct the error.

[0142] FIGS. 5A-5H show the formats of data and an exemplary waveform that would appear when thermal asperity takes place. The Figures together show how an error associated with thermal asperity can be detected from the waveform. FIG. 5A is the format of data recorded on the magnetic disc 24, which is the same data format as FIG. 3A. FIG. 5B indicates the waveform of the reproduced analogue signal when thermal asperity has occurred. This signal is fed by the AGC amplifier 29 to the TA level comparator circuit 40. It is shown in the Figure that the signal has a transient component due to thermal asperity. The Figure also shows a relationship between the reproduced signal and a threshold signal Th. FIG. 5C shows a signal output from the TA level comparator circuit 40. FIG. 5D shows the same NRZ data 22 output from the 8/9 decoder and de-scrambler 33 as shown in FIG. 3B. FIG. 5E shows a read clock signal RCLK 41 output from the PLL circuit 34, which is the same as the clock signal RCLK shown in FIG. 3C. FIG. 5F shows a read gate signal RG 42 which is the same as the signal RG 42 shown in FIG. 3D. FIG. 5G shows an error signal 23 output from the error signal generation circuit 35. FIG. 5H shows the output of the counter circuit 45 (FIG. 6).

[0143] There are two major error correction methods as describe below, which are: (1) Error correction on the fly (referred to as ECC on the fly); and (2) Software error correction (referred to as software ECC). In addition, in order to prevent repeated occurrence of thermal asperity caused by the same protrusion subsequent to an error correction process, a third method (3), known as “automatic sector substitution process”, is available, which permits a jump of the head from the sector of the magnetic disc 24 having a protrusion to cause thermal asperity to an alternative sector having no protrusion.

[0144] (1) Error Correction On the Fly (ECC on the Fly)

[0145] This is a typical error correction method known in the art, in which errors are corrected using a hardware such as an ECC controller 6 shown in FIG. 1. In most magnetic hard disc devices, errors up to 9 bytes or 12 bytes can be corrected on the fly using such error correction circuit, and about 20 bytes of errors can be dealt with using some recent error correction circuit. However, errors exceeding 20 bytes cannot be dealt with by a hardware correction method.

[0146] Generally, in correcting errors by means of ECC on the fly method, an error if any in the data is corrected on the fly by the ECC controller 6 while sequentially reading data from the magnetic disc 24. Given that the reproduced data has a length of 2X bytes, it is said that in such error correction the maximum length of errors correctable (correction ability) on the fly is X bytes. That is, errors exceeding X bytes cannot be corrected.

[0147] (2) Software ECC

[0148] This is a typical software error correction method known in the art, in which errors are corrected using, for example, a software ECC installed in a hard disc controller SH7600 available from CIRRUS LOGIC Corporation and a software ECC installed in a hard disc controller, model ATEC available from Q LOGIC Corporation. This type of software ECC retrieves all the data having length 2X on the magnetic disc 24 and stores the data once in a RAM (not shown) and perform correction thereafter using the software. The correction ability for 2X byte data is 2X.

[0149] The software ECC has an advantage that error correction may be performed if the location of the error (i.e. the total length of data from the beginning thereof in unit of sector to the beginning of the error), and the length of the errors themselves are known. On the other hand, it has a disadvantage in that the magnetic head must be idling during the correction procedure, so that read operation is momentarily interrupted, thereby resulting in an overhead.

[0150] It should be appreciated that the software ECC of the invention as described below requires a shorter correction time as compared with the above mentioned prior art methods, because the location and the length of erroneous data can be determined beforehand according to the invention in a manner as described below.

[0151] (3) Automatic Sector Substitution Process

[0152] In a typical initialization of a magnetic disc, a defective sector found in the initialization process is registered as invalid so as to avoid write and read of data in the sector, and a substituting sector is provided for the data that would have been otherwise recorded in the invalid sector. Therefore, the data is read from the substituting sector.

[0153] This approach may be used to avoid repeated software ECC error correction for thermal asperity caused by the same protrusion on the magnetic disc. In accordance with the invention defective sectors causing thermal asperity are registered so that they can be automatically substituted for by normal sectors by a firmware, in the same manner as described above for ordinary defective sectors.

[0154] The invention utilizes hardware ECC on the fly, software ECC, and an automatic sector substitution process in accordance with the type and/or the size of errors, in combination.

[0155] As shown in FIGS. 4 A-B, the correction procedure of the invention begins with step 100 in which the CPU 8 makes a query to the host computer (not shown) via the interface 1 if the host computer has been issued a read command. If the answer is NO, the procedure proceeds to Step S105 where operations irrelevant to error correction are carried out, but otherwise the procedure proceeds to Step S120.

[0156] In Step S120, the error counter circuit 45 and the register circuit 46 (FIG. 3) are reset to the respective initial values. The procedure goes to Step S130.

[0157] The counter circuit 45 and the register circuit 46 as shown in FIG. 6 are provided in the hard disc controller 2 of FIG. 1, preferably in the disc format controller 3. The counter circuit 45 receives read clock RCLK 41 at terminal CLK, an error signal 23 from the error signal generation circuit 35 of the read/write controller 14 (FIG. 2) at terminal LD, and read gate signal RG 42 at terminal CLR. The read gate signal RG 42 is cut off (FIG. 3C) when all the data associated with one sector has been read, and accordingly the counter circuit 45 and the register circuit 46 are reset. The procedure then goes to Step S130.

[0158] In Step S130, a read gate signal RG 42 is supplied to read the next data sector (which is referred to as target sector).

[0159] In the next Step S140, the counter circuit 45 starts counting the number of sectors read out (FIGS. 5D and 5H), until the sector having errors due to thermal asperity is found, so as to find the location of the erroneous sector in the subsequent steps.

[0160] The procedure then proceeds to Step S150, where the CPU 8 makes a query whether an error signal 23 has been generated. If the answer is NO, the procedure proceeds to Step S152, but goes to Step S160 if the error has been detected.

[0161] In step S152, the CPU 8 continues to execute the read command as instructed by the host computer (not shown), asking whether all the data in the target sector has been read out (Step S154). When all the data has been read out, the procedure goes to Step S156, where a query is made as to whether the read command is finished. If it is finished, the procedure proceeds to Step S157, but otherwise the procedure is ended.

[0162] In Step S157, the CPU 8 increments the sector number for the target sector. That is, the target sector is set to next data sector, and loops back to Step 130 to repeat the read operation for the next target sector.

[0163] Coming back to Step S150, when an error signal is detected, an error correction process is started in the next Step 160. The error signal may be generated in the first method as follows and applied in Step 160. In this method error signal 23 is generated by the error signal generation circuit 35 in collaboration with the TA level comparator circuit 40 when thermal asperity has occurred. In an event when thermal asperity has occurred, the reproduced data, output from the AGC amplifier 29, contains a transient signal having a waveform as shown in FIG. 5B. The reproduced data is fed to the TA level comparator circuit 40 (FIG. 2) together with the predetermined threshold signal Th. The TA level comparator circuit 40 is adapted to compare the absolute value of the reproduced data with the absolute value of the threshold signal Th and generate an ON signal only if the former value exceeds the latter value, as shown in FIGS. 5B and 5C. The ON signal generated by the TA level comparator is fed to the error signal generation circuit 35.

[0164] From the number of the bytes in the sector as counted up in Step S140, the CPU 8 obtains the length of non-erroneous data in byte, “A-bytes”, indicating also the location of the erroneous data. The value of the A-bytes is stored in the register circuit 46 (FIG. 3) in Step S160. The A-bytes representing the location of the erroneous sector is determined from the number of the read clock signals RCLK 41 shown in FIG. 5E counted for the period of time during which the read gate signal RG is ON to read data from the magnetic disc 24 as shown in FIG. 5F and until the error signal 23 shown in FIG. 5G occurs.

[0165] The value of the A-bytes is fed to the register circuit 46 for temporary storage thereof. The register circuit 46 transmits the value of A-bytes to CPU 8 for use as a bus control signal 21. The procedure then proceeds to the next step S170.

[0166] In step S170, counting of the length the erroneous data itself is started using the counter circuit 45.

[0167] In the next step S180, CPU 8 makes a query as to whether or not the error signal (FIG. 5G) has ended. If the error signal has ended, the procedure proceeds to step S190 for the next process, but otherwise the procedure loops back to itself making the same query.

[0168] The error signal 33 shown in FIG. 5G is generated to indicate the length of the erroneous data. This error signal can be generated by the error signal generation circuit 35 by selecting one of the three signals: (a) signal output from the TA level comparator circuit 40 shown in FIG. 5C; (2) NRZ data including errors due to thermal asperity; and (3) signal indicative of the logical sum (OR) of these two signals. The error signal 33 is in phase with the reference clock RCLK, and is fed by the error signal generation circuit 35 to the counter circuit 45 built in the hard disc controller (HDC) 2. The counter circuit 45 counts up the read clock 41 during ON period of the error signal 33, yielding B-bytes for the length of the erroneous data as shown in FIG. 5H.

[0169] In Step S190, CPU 8 causes the register circuit 46 (FIG. 6) to store the value of B-bytes indicative of the erroneous data as counted in step S170. The register circuit 46 then transmits this value to CPU 8 for use as a bus signal 21.

[0170] In the next step S200, CPU 8 makes a determination whether the length of the B-bytes stored in the register circuit 46 (FIG. 3) in step S190 is longer than the length of data correctable by the ECC on the fly. If so, the procedure proceeds to Step S210, but otherwise proceeds to Step S202.

[0171] In Step S202, CPU 8 activates the ECC controller 6 (FIG. 1) to execute the ECC on the fly and goes to step S204.

[0172] In Step S204, CPU 8 makes a determination if the error correction process has ended successfully. If so, the procedure goes to Step S205, or otherwise goes to Step S206.

[0173] In Step S205, CPU 8 provides a retry instruction to read again a sector to be error-corrected, so that the procedure loops back to step S120 to go over the correction process. If the software ECC fails to remove errors after a predetermined number of retries, the CPU 8 displays a message to the operator that there is(are) error(s) not correctable in the data.

[0174] In Step S206, it is determined if the read instruction from the host computer has ended. If it is not, the procedure loops back to Step S157 for shifting the target sector to the next data sector. If the read instruction has ended, the procedure goes to step S240.

[0175] Coming back to Step S210, CPU 8 executes the software ECC, since the errors cannot be corrected by the ECC on the fly due to the fact that the length of the current erroneous data, B-byte, is longer than the length of errors that can be corrected by the ECC on the fly. Then the procedure goes to the next Step S220.

[0176] In step S220, a determination is made if the correction of the errors done in step S210 is proper. If it is found that the correction is improper, the procedure goes back to Step S205, where read operation is retried. On the other hand, if the correction is proper, the procedure proceeds to Step S230.

[0177] In Step S230, CPU 8 makes a query if the read instruction from the host computer has ended. If the answer is NO, then the procedure loops back to Step S157. If the answer is YES, then Step S240 follows.

[0178] In step S240, in order to prevent repetitive thermal asperity caused by the same protrusion on the magnetic disc 24, a determination is made if the automatic sector substitution process is usable or not. If the automatic sector substitution process is usable, Step S242 follows. Otherwise, the procedure is ended.

[0179] In Step S242, the procedure provides a process in which a substituting sector is established on the magnetic disc 24 for the defective sector(s). The procedure is then ended.

[0180] The ECC on the fly, the software ECC, and the automatic sector substitution process may be employed in combination as described above in correcting erroneous data on the magnetic disc. Next, a round off procedure and a second error signal generation method for correcting multiple errors will now be described below.

[0181] [Round Off Procedure]

[0182] FIGS. 7A-7E together show a scheme in which a multiplicity of errors occurring in one sector may be detected using a round off procedure which rounds off multiple errors within a length of bytes correctable by the hardware ECC on the fly or the software ECC. FIG. 7A shows a data format on the magnetic disc 24. FIG. 7B shows NRZ data portion of the data shown in FIG. 7A in a case where the data includes therein multiple errors (such as errors 1, 2, and 3 in the example shown in FIG. 7B). FIG. 7C shows data obtained by rounding off the erroneous data 1 and 2. FIG. 7D shows data obtained by rounding off the erroneous data 1 and 2, and 3. FIG. 7E shows the error signal of FIG. 5G.

[0183] When the erroneous data 1 and 2 are the only erroneous data in the DATE sector, and if the rounded erroneous data therefor is smaller in byte than the maximum bytes, 9 bytes say, correctable by the hardware ECC as shown in FIG. 7C, these errors may be corrected by the hardware ECC on the fly, as described above.

[0184] If, on the other hand, a further erroneous data 3 exists in the sector such that the rounded erroneous data has a data length greater than the maximum correctable bytes by the hardware ECC on the fly, then the errors can be corrected by the software ECC as described previously, provided that the rounded erroneous data is smaller in size than the maximum data length correctable by the software ECC method. In any event, the errors may be corrected appropriately by one of the two correction methods selected in accordance with the invention.

[0185] [Alternative Method of Generating Error Signal]

[0186] In the first error signal generation method described above, the error signal 23 is generated by the error signal generation circuit 35 upon receipt of signals from the TA level comparator circuit 40 and from the 8/9 decoder and de-scrambler 33, as described in connection with FIG. 2. An alternative error signal may be generated by a second method as shown in FIG. 8, which is based on the digital nature of the decoded NRZ data.

[0187] FIG. 8A illustrates a sequence of bits representing the reproduced data having 8/9 (0, 4/4) format. FIG. 8B shows the even part of the sequence shown in FIG. 8A (i.e. the sequence of bits of even order in the original sequence), while FIG. 8C the odd part of the sequence of FIG. 8A. FIG. 8D shows a latch error signal and FIG. 8E an output of a 4-stage shift register.

[0188] The 8/9 decoder and de-scrambler 33 shown in FIG. 2 employs a 8/9 transform coding wherein an 8/9 (0, n/m) transformation format is generally used. This transformation format is based on “n/m run-length rules” in which the number of zeros between two neighboring “1”s is not more than n and the number of “0”s in the even and the odd parts of the digital data is not more than m (zero rules).

[0189] Accordingly, in the case of 8/9 (0, 4/4) encoding format for example, a correct data sequence includes at most 4 consecutive zeros, and the even and the odd parts the data each also include at most 4 consecutive zeros. As an another example, data encoded by 8/9 (0, 3/5) encoding format has at most 3 consecutive zeros and each of the odd and the even parts thereof includes at most 5 consecutive zeros.

[0190] To be specific, suppose that a digital data has a sequence of “11010100000001000000100001110010010010”, as shown in FIG. 8A. The even part of the sequence is “11100010000011001” as shown in FIG. 8B, and the odd part is “100000000010010100” as shown in FIG. 8C. Applying the zero rules to the data sequence, the maximum number of consecutive zeros in the data as well as in the even and odd parts thereof must be equal to or less than 4. However, in actuality the data shown in FIG. 8A contains two underlined sections having 7 zeros and 6 zeros, respectively, which are against the zero rules imposed on the data. The even part and the odd part contains a section having 5 consecutive zeros and a section having 9 consecutive zeros, respectively. These zeros may be detected when the data fails to converge even after the data is passed through a 4-stage shift register (not shown) with “0” latched.

[0191] Consequently, if a latch error signal is defined associated with the portions of the data which are not in accord with the zero-rules, one may obtain a 24-byte error signal 23 as shown in FIG. 8D in the case shown herein. FIG. 8E shows a latch error signal obtained from this data through the 4-stage shift register.

[0192] In place of a combination of the TA level comparator circuit 40 and the error signal generation circuit 35 for generating an error signal, it is possible to provide a hardware error detection means for generating such error signal 23 for a decoded NRZ digital data, based on the zero-rules as defined by 8/9 (0, n/m) format.

[0193] It would be apparent to those skilled in the art that either one of the first and the second error signal generation methods as described above may be arbitrarily chosen. It is also possible to employ the two methods simultaneously to generate two kinds of error signals and choose either one of them using an appropriate selector circuit (not shown).

[0194] Advantages observed in the embodiments are as follows.

[0195] (1) In one embodiment of the invention, erroneous data caused by thermal asperity may be located.

[0196] (2) In another embodiment of the invention, the length of the errors itself may be determined.

[0197] (3) In still another embodiment of the invention, an error signal may be generated by a combination of a comparator and an error signal generation circuit, as well as by a run length rules imposed on the data.

[0198] (4) In a further embodiment of the invention, a software ECC may be executed even in a case where hardware ECC on the fly is inapplicable, based on the fact that both the location of errors, caused by thermal asperity for example, and the length of the errors may be determined.

[0199] (5) In a still further embodiment of the invention, since the precise location and the length of erroneous data due to thermal asperity can be determined from an error signal, the data sector associated with the erroneous data may be registered as an invalid sector and may be substituted for by a new sector defined for the invalid sector.

[0200] (6) The invention thus provides an improvement in error correction ability of a magnetic disc device, thereby reducing the error rate and enhancing the reliability thereof.

[0201] [Advantages of the Invention]

[0202] The invention provide a data correction device which may determine the location and the length of the error contained in the data read from a magnetic recording medium.

[0203] The invention provides a method which may determine the location and the length of the error contained in the data read from a magnetic recording medium.

[0204] The invention provides a magnetic disc device which is equipped with means for detecting erroneous data caused by thermal asperity due to a sudden change in electric resistance of an MR element of an MR head caused by a temporary collision of the head with the magnetic disc.

[0205] The invention provides a magnetic disc device which is equipped with means for detecting and correcting erroneous data due to thermal asperity.

[0206] The invention provides a method for detecting erroneous data for use with a magnetic disc device.

[0207] The invention provides a method for detecting and correcting erroneous data for use with a magnetic disc device.

[0208] The invention further provides a magnetic disc device equipped with means for detecting an error in the data read from a magnetic disc caused by thermal asperity a sudden change in electric resistance of an MR element of an MR head caused by a temporary collision of the MR head with the magnetic disc.

[0209] The invention further provides a magnetic disc device equipped with means for detecting and correcting errors caused by thermal asperity and contained in the data read from the magnetic disc.

[0210] [Other Embodiments]

[0211] The present invention may be realized as the following embodiments, corresponding to the respective claims.

[0212] (1) The erroneous data correction device according to claim 14, wherein said decoder performs 8/9 format transformation.

[0213] (2) The erroneous data correction device according to claim 14, wherein said given set of run length rules is in accord with 8/9 (0, n/m) zero run length format.

[0214] (3) The erroneous data correction device according to claim 14, wherein said zero run-length rules is in accord with 8/9 (0, 4/4) zero run length format.

[0215] (4) The erroneous data correction device according to claim 14, wherein said zero run-length rules is in accord with 8/9 (0, 3/5) zero run length format.

[0216] (5) A magnetic disc recording device, comprising an erroneous data correction device according to any one of claim 1 through claim 15.

[0217] (6) The magnetic disc device according to claim 15,

[0218] wherein said magnetic recording medium is a magnetic disc.

[0219] (7) The error correction method according to claim 20, further comprising a step of determining the length of said erroneous data based on said error signal.

[0220] (8) The error correction method according to claim 21, further comprising

[0221] an automatic sector substitution process to be executed subsequent to said software ECC.