Semiconductor device

[0002] The present invention relates to a semiconductor device and, more particularly, to a technique effectively applied to the improvement of electric properties of a semiconductor device in which a multilayer circuit board is used.

[0003] There is, for example, a FC-BGA (Flip Chip-Ball Grid Array) as a chip for high-speed and multi-pin semiconductor. As a substrate for this package, a ceramic substrate and an organic substrate, etc. are used. The organic substrate is, however, more efficient in terms of the cost reduction. In order to deal with the multi-pin semiconductor chip, a build-up process, in which micro wirings are formed by the photolithography on the front and rear of a core layer having through holes formed by a drill, has recently been employed in the organic substrate.

[0004] In such a package for high-speed and multi-pin semiconductor chip, there are required good electric properties and, for example, is need for reducing a variation in the characteristic impedance values of all signal wirings in the package.

[0005] Note that a technique for solving noise problems without changing the characteristic impedance of the multilayer circuit board (wiring board) is disclosed in Japanese Patent Laid-open No. 2001-77541. The above technique is one for separating the signal wirings from a ground conductor layer in order to adjust the impedance relative to the ground conductor layer.

[0006] Meanwhile, Japanese Patent Laid-Open No. 2001-77541 discloses that the characteristic impedance changes depending on the thickness of an insulating layer arranged between the ground conductor layer and the signal wiring. However, it does not have any descriptions of the influence of the characteristic impedance, which is exerted on the signal wirings from a plurality of through-hole wirings formed on a core layer, the signal wirings being formed just above it via an insulating layer, in the case where a package board is, for example, a build-up board.

[0007] More specifically, in the actual package board, the plurality of through-hole wirings are formed in the core layer, and a large number of signal wirings are arranged also on the through-hole wirings via the insulating layer. Therefore, it is difficult to achieve the arrangement in which no signal wirings are formed above the through-hole wirings.

[0008] Accordingly, it is insufficient in the design of the package board to consider simply the change in the characteristic impedance depending on the thickness of the insulating layer arranged between the ground conductor layer and the signal wiring. Thereby, the problem occurs such that variation in impedances of the signal wirings on the through-hole wirings and the signal wirings on no through-hole wirings is beyond control.

[0009] An object of the present invention is to provide a semiconductor device capable of reducing the variation in the characteristic impedance of the wirings with high accuracy.

[0010] The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011] The typical ones of the inventions disclosed in this application will be briefly described as follows.

[0012] That is, the present invention comprises: a multilayer circuit board having an insulating base member, a first wiring layer arranged on a surface of the base member and provided with a power plane, a third wiring layer arranged on said first wiring layer via an insulating layer in a direction further away from said base member and provided with a power plane, and a second wiring layer arranged between said first and third wiring layers and provided with a signal wiring; and a semiconductor chip arranged on a main surface of said multilayer circuit board, wherein the gap between said first and second wiring layers is larger than that between said second and third wiring layers, and an area of the power plane of said third wiring layer is larger than that of the power plane of said first wiring layer.

[0013] FIG. 1 is a plan view showing an example of a structure of a semiconductor device (BGA) according to a first embodiment of the present invention.

[0014] FIG. 2 is a cross-sectional view showing the structure of the BGA shown in FIG. 1.

[0015] FIG. 3 is a bottom plan view showing the structure of the BGA shown in FIG. 1.

[0016] FIG. 4 is a partially enlarged sectional view showing an example of a structure of a multilayer circuit board incorporated in the BGA shown in FIG. 1.

[0017] FIG. 5 is a partially enlarged sectional view showing a detailed structure of the region A shown in FIG. 4.

[0018] FIG. 6 is a partially enlarged sectional view showing an example of a positional relationship between the via wiring of a core layer and wirings just above the via wiring, in the board structure shown in FIG. 5.

[0019] FIG. 7 is a partially enlarged plan view showing an example of a structure of a fifth wiring layer, in the board structure shown in FIG. 4.

[0020] FIG. 8 is a partially enlarged plan view showing an example of a structure of a fourth wiring layer, in the board structure shown in FIG. 4.

[0021] FIG. 9 is a partially enlarged plan view showing an example of a structure of a third wiring layer, in the board structure shown in FIG. 4.

[0022] FIG. 10 is a partially enlarged plan view showing an example of a structure of a second wiring layer, in the board structure shown in FIG. 4.

[0023] FIG. 11 is a partially enlarged plan view showing an example of a structure of a first wiring layer, in the board structure shown in FIG. 4.

[0024] FIG. 12 is a partially enlarged plan view showing an example of a structure of a first wiring layer on the ball side, in the board structure shown in FIG. 4.

[0025] FIG. 13 is an enlarged sectional view and an enlarged plan view showing an example of the structure of the via wiring shown in FIG. 11.

[0026] FIG. 14 is partially enlarged sectional view showing an example of a detailed structure of a multilayer circuit board in a semiconductor device (BGA) according to a second embodiment of the present invention.

[0027] Hereinafter, embodiments of the present invention will be described based on the drawings.

[0028] The following embodiments will be divided into a plurality of sections or other embodiments and be described when required as a matter of convenience. However, these sections or other embodiments are not irrelevant to each other unless otherwise stated, and one of them relates to a part or the entire of the other as a modification example, details, a supplementary explanation thereof, or the like.

[0029] Also, in the following embodiments, when the number of elements or the like (including number of pieces, values, amount, range, or the like) is mentioned, it is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle, and may be the number larger or smaller than the specific number.

[0030] Furthermore, needless to say, components (including element steps or the like) mentioned in the following embodiments are not always indispensable unless otherwise stated and except the case where it is understood that they are apparently indispensable in principle.

[0031] Similarly, in the following embodiments, when the shapes of the components, the positional relation thereof, and the like are mentioned, ones substantially approximate and similar to the shapes or the like are included therein unless otherwise stated or except the case where it can be understood that they are apparently excluded in principle. This condition is also applicable to the numerical value and the range described above.

[0032] Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

[0033] (First Embodiment)

[0034] FIG. 1 is a plan view showing an example of a structure of a semiconductor device (BGA) according to a first embodiment of the present invention; FIG. 2 is a cross-sectional view showing the structure of the BGA shown in FIG. 1; FIG. 3 is a bottom plan view showing the structure of the BGA shown in FIG. 1; FIG. 4 is a partially enlarged sectional view showing an example of a structure of a multilayer circuit board incorporated in the BGA shown in FIG. 1; FIG. 5 is a partially enlarged sectional view showing a detailed structure of the region A shown in FIG. 4; FIG. 6 is a partially enlarged sectional view showing an example of a positional relationship between the via wiring of a core layer and wirings just above the via wiring, in the board structure shown in FIG. 5; FIG. 7 is a partially enlarged plan view showing an example of a structure of a fifth wiring layer, in the board structure shown in FIG. 4; FIG. 8 is a partially enlarged plan view showing an example of a structure of a fourth wiring layer, in the board structure shown in FIG. 4; FIG. 9 is a partially enlarged plan view showing an example of a structure of a third wiring layer, in the board structure shown in FIG. 4; FIG. 10 is a partially enlarged plan view showing an example of a structure of a second wiring layer, in the board structure shown in FIG. 4; FIG. 11 is a partially enlarged plan view showing an example of a structure of a first wiring layer, in the board structure shown in FIG. 4; FIG. 12 is a partially enlarged plan view showing an example of a structure of a first wiring layer on the ball side, in the board structure shown in FIG. 4; and FIG. 13 is an enlarged sectional view and an enlarged plan view showing an example of the structure of the via wiring shown in FIG. 11.

[0035] Note that FIGS. 7 to 12 are drawings showing wiring patterns of each wiring layer in a package board 4. However, each of the drawings shows only a certain one-fourth area of the wiring layer-in the package board 4 shown in FIG. 1, and equivalent wiring patterns thereto are formed also on the remaining three-fourths area of the respective wiring layers.

[0036] A semiconductor device according to a first embodiment shown in FIGS. 1 to 3 is a multi-pin semiconductor package and is a BGA (Ball Grid Array) 1 in which: a semiconductor chip 2 is mounted by a flip-chip bonding on a main surface 4aof the package board 4 which is a multilayer circuit board; and a plurality of ball electrodes 3, which are external connection terminals, are arranged in an array on a rear surface 4bopposite to the main surface 4aof the package board 4 as shown in FIG. 3.

[0037] Note that the flip-chip bonding is performed via solder bump electrodes 5. More specifically, the main surface 2aof the semiconductor chip 2 and the main surface 4aof the package board 4 are faced to put therebetween the solder bump electrodes 5, and the semiconductor chip 2 and the package board 4 are electrically connected to each other via the solder bump electrodes 5. Furthermore, connection portions brought with the flip-chip bonding are protected by an underfill resin 6 formed of, for example, an insulating resin or the like.

[0038] Also, chip capacitors 7, which are chip parts, are mounted on the periphery of the semiconductor chip 2 and on the side of the main surface 4aof the package board 4.

[0039] Further, the ball electrodes 3, which are arranged on the side of the rear surface 4bof the package board 4, are formed of, for example, solder.

[0040] Also, as shown in FIG. 4, the package board 4 is a multilayer circuit board, and is a build-up board, in which wiring layers and insulating layers are laminated by a build-up process on both of the chip side and ball electrode (external connection terminal) side of a core layer 4cthat is a base member.

[0041] Therefore, the build-up layer 4zcomposed of the wiring layers and the insulating layers is symmetrically formed on each of the chip side and the ball electrode side of the surfaces of the core layer 4c, whereby micro-wirings can be formed therein.

[0042] Note that the package board 4 of the BGA 1 according to the first embodiment exemplifies the case where the build-up layer 4zon one side has five wiring layers and four insulating layers each provided between the wiring layers.

[0043] More specifically, toward the semiconductor chip 2 and the ball electrodes 3 from the core layer 4c, a first wiring layer 4d, a second wiring layer 4e, a third wiring layer 4f, a fourth wiring layer 4g, and a fifth wiring layer 4hare respectively formed, and a first insulating layer 4i, a second insulating layer 4j, a third insulating layer 4k, and a fourth insulating layer 4lare formed between the respective wiring layers. Also, an insulating film 8esuch as a resist film etc. is formed on the surface of the fifth wiring layer 4h.

[0044] In the package 4 as shown in FIG. 6, relative to a first wiring 4mof the second wiring layer 4earranged above a through hole 4rof the core layer 4c, the thickness (D) of the first insulating layer 4ibetween the first wiring layer 4dthat is a plane layer on the surface of the core layer 4cand the second wiring layer 4eis made large, and that of the second insulating layer 4j(C) between the third wiring layer 4fthat is a plane layer on the opposite side thereto and the second wiring layer 4eis made small. Therefore, the BGA 1 according to the first embodiment reduces the impedance coupling between a power plane 8a, as shown in FIG. 11, of the first wiring layer 4dthat is a plane layer on the surface of the core layer 4cand the first and second wirings 4mand 4n, and increases the impedance coupling between the power plane 8a, as shown in FIG. 9, of the third wiring layer 4fthat is a plane layer on the opposite side thereto and the first and second wirings 4mand 4n.

[0045] Due to this, it becomes possible to control the characteristic impedance of the wirings with high accuracy, and to achieve the reduction of the difference in the characteristic impedance between the first wiring 4marranged above the through hole 4rand the second wiring 4narranged away from above the through hole 4r.

[0046] Next, the detailed structure of the build-up layer 4zof the package board 4 will be described. Note that the constitution of the core layer 4cand that of the build-up layer 4zon the chip side will be described here. However, the build-up layer 4zon the ball electrode side has almost the same structure.

[0047] First, as shown in FIG. 5, a plurality of first via wirings 4p, serving as first through-hole wirings that electrically connect the surface on the chip side and the surface on the ball electrode side, are provided in the core layer 4c.

[0048] More specifically, wirings shown in FIG. 11, which are provided on the first wiring layer 4dthat is the surface of the core layer 4con the chip side, and wirings shown in FIG. 12, which are provided on the first wiring layer 4dthat is the surface corresponding thereto on the ball electrode side, are electrically connected to one another through the first via wiring 4pshown in FIG. 5.

[0049] For example, as shown in FIG. 11, the power plane 8a, that is, a conductor pattern for supplying electric power is formed in the first wiring layer 4dthat is the surface of the core layer 4con the chip side. Correspondingly, power wirings 4s, each having the shape combining a half circle and a triangle as shown in FIG. 12, are formed in the first wiring layer 4dthat is the surface of the core layer 4con the ball electrode side. The power plane 8aof the first wiring layer 4don the chip side and the power wirings 4sof the first wiring layer 4don the ball electrode side are electrically connected to each other via the first via wiring 4p.

[0050] Similarly, a ground plane 8b, that is, a ground conductor pattern is formed in the first wiring layer 4don the ball electrode side. Correspondingly, ground wirings 4u, each having the shape combining a half circle and a triangle, are formed in the first wiring layer 4don the chip side.

[0051] Note that each power wiring is one for supplying a predetermined electric power, and the ground wiring is one for supplying electric power having a reference potential such as 0 V etc. Therefore, the ground plane 8bcan be regarded as a kind of the power plane 8a.

[0052] Also, a plurality of signal wirings 4t, each having the shape combining a half circle and a triangle, are formed in each first wiring layer 4don the chip side and the ball electrode side. The signal wirings 4ton the chip side and the signal wirings 4ton the ball electrode side are electrically connected to each other via the first via wiring 4p.

[0053] Therefore, each wiring escape 4v, which avoids being electrically connected to the power wiring 4s, the ground wiring 4u, and the signal wiring 4tthat have the shape combining a half circle and a triangle, is formed in the power plane 8aand the ground plane 8bof the first wiring layers 4don the chip side and the ball electrode side.

[0054] Furthermore, since the plurality of through holes 4rare also formed, a large number of wiring escapes 4vare formed in the power plane 8aand the ground plane 8b, whereby a region, in which respective conductive portions are not formed, is widely extended therein. Therefore, the respective areas of conductive portions in the power plane 8aof the first wiring layer 4don the chip side and in the ground plane 8bof the first wiring layer 4don the ball electrode side are extremely smaller in comparison to the area of the power plane 8aof the third wiring layer 4fof the package board 4.

[0055] Next, the structure of the second wiring layer 4ein the build-up layer 4zon the chip side of the core layer 4cwill be described with reference to FIG. 10.

[0056] A plurality of first signal wirings 8care formed in the second wiring layer 4eshown in FIG. 10, and the wirings are led from a signal terminal 4xwithin a region located below the chip, to a signal terminal 4xwithin a region located outside the chip.

[0057] Also, other signal wirings 4tfor connecting the upper second via wiring 4qand the lower second via wiring 4q, and the wiring escapes 4vfor avoiding these are arranged on the periphery of the plurality of first signal wirings 8c, whereby the ground plane 8bthat is a plane-tight wiring is formed on the periphery thereof.

[0058] More specifically, in the second wiring layer 4e, the plurality of first signal wirings 8care surrounded by the ground plane 8b.

[0059] Next, the structure of the third wiring layer 4fin the build-up layer 4zon the chip side of the core layer 4cwill be described with reference to FIG. 9.

[0060] In the third wiring layer 4fshown in FIG. 9, the power plane 8athat is a plane-tight wiring is formed.

[0061] Furthermore, the plurality of signal wirings 4tand ground wirings 4ufor connecting the upper second via wiring 4qand the lower second via wiring 4qare formed, respectively, and the power plane 8a, in which the wiring escapes 4vfor avoiding these are formed, is formed.

[0062] Note that the signal wirings 4tand the ground wirings 4uof the third wiring layer 4fare wirings having an extremely small area, so that the power plane 8aof the third wiring layer 4f, which is arranged to avoid these, becomes plane with an area much larger than the power plane 8aof the first wiring layer 4d.

[0063] Next, the structure of the fourth wiring layer 4gin the build-up layer 4zon the chip side of the core layer 4cwill be described with reference to FIG. 8.

[0064] In the fourth wiring layer 4gshown in FIG. 8, a plurality of second signal wirings 8dare formed, and, similarly to the first signal wirings 8cof the second wiring layer 4e, wirings are led from the signal terminal 4xwithin a region located below the chip, to the signal terminal 4xwithin a region located outside the chip.

[0065] Also, the ground plane 8bis formed on the periphery of the plurality of second signal wirings 8dso as to avoid these. Accordingly, also in the fourth wiring layer 4g, the plurality of second signal wirings 8dare surrounded by the ground plane 8b.

[0066] Next, the structure of the fifth wiring layer 4hthat is the uppermost plane layer in the build-up layer 4zon the chip side of the core layer 4cwill be described with reference to FIG. 7.

[0067] In the fifth wiring layer 4hshown in FIG. 7, a plurality of signal terminals 4x, power terminals 4wand ground terminals 4yfor the flip-chip bonding are formed at the positions, which correspond to the arrangement of the solder bump electrodes 5 mounted on the main surface 2aof the semiconductor chip 2, and the ground plane 8bis formed on the outside thereof.

[0068] Furthermore, the power terminals 4ware electrically connected to each other via the power wiring 4s, and ground terminals 4yare electrically connected to the ground plane 8boutside them via the ground wiring 4u.

[0069] Therefore, the plurality of signal terminals 4xare surrounded by the ground plane 8bin the fifth wiring layer 4h, whereby terminals and wirings of the signal system are respectively surrounded by the ground plane 8bin the second wiring layer 4e, the fourth wiring layer 4g, and the fifth wiring layer 4hin which the plurality of signal terminals 4x, first signal wirings 8cand second signal wirings 8dare formed.

[0070] Additionally, the first signal wiring 8cof the second wiring layer 4eis sandwiched between the power plane 8aof the first wiring layer 4dand the power plane 8aof the third wiring layer 4f. Also, the second signal wiring 8dof the fourth wiring layer 4gis sandwiched between the power plane 8aof the third wiring layer 4fand the ground plane 8bof the fifth wiring layer 4h.

[0071] Therefore, each of the terminals and wirings of the signal system in addition to the tops and bottoms of them is covered with the power plane 8aand the ground plane 8b. For this reason, a board structure is obtained which is capable of preventing the occurrence of noises on the terminals and the wirings of the signal system, or the deterioration in frequency characteristics, or the like.

[0072] Also, the signal terminals 4xof the fifth wiring layer 4hand the signal terminals 4xof the fourth wiring layer 4gcorresponding thereto, and the signal terminals 4xof the second wiring layer 4eand the signal terminals 4xof the fourth wiring layer 4gcorresponding thereto are electrically connected, as shown in FIG. 5, via the second via wirings 4qthat are second through-hole wirings.

[0073] Note that, with respect to the first via wiring 4pand the second via wiring 4q, the diameter of the first via wiring 4pis much larger than that of the second via wiring 4q. For example, when the thickness (T) of the core layer 4cis about 800 μm, the wiring diameter (H) equivalent to the via diameter of the first via wiring 4pis, for example, 250 to 300 μm as shown in FIG. 13. However, the wiring diameter (F) equivalent to the via diameter of the second via wiring 4qis, for example, 100 μm or smaller as shown in FIG. 5.

[0074] This causes a difference between the hole diameters of the above-mentioned through holes because the methods of processing the underlying through hole are different depending on each thickness of the layers.

[0075] More specifically, since the thickness (T) of the core layer 4cis about 800 μm, the underlying through hole is formed using a drill. At this time, if the drill having a small diameter is used, it may be broken. Therefore, a drill having a relatively large diameter is used.

[0076] In contrast, since the underlying through hole of the second via wiring 4qhas a thickness of several tens μm, it is formed by a lithography technique or a laser process.

[0077] Therefore, the above-mentioned underlying through hole, having a diameter much smaller than the underlying through hole of the first via wiring 4p, can be formed.

[0078] As a result, also with respect to the wiring escape 4v, the size (E) of the wiring escape 4vis equivalent to a width of about 400 μm in the case of the second via wiring 4qshown in FIG. 5. In contrast, the size (G) of the wiring escape 4vis equivalent to a diameter of about 800 to about 900 μm in the case of the first via wiring 4pas shown in FIG. 13. That is, the wiring escape 4vformed in the first wiring layer 4dshown in FIG. 11 is much larger than the wiring escape 4vformed in the third wiring layer 4fshown in FIG. 9.

[0079] Also, since the diameter (G) of the wiring escape 4v, as shown in FIG. 13, of the first via wiring 4pformed in the core layer 4cis about 800 to about 900 μm, it is much larger than any of the thicknesses of the first insulating layer 4i, the second insulating layer 4j, the third insulating layer 4k, and the fourth insulating layer 41 (e.g., about 30 to about 50 μm).

[0080] In the BGA 1 thus employing the package board 4 as described above, as shown in FIG. 6, there often occurs the case where the first wiring 4mis arranged just above the through hole 4rand the wiring escape 4v, in the upper second wiring layer 4eon the first wiring layer 4don the surface of the core layer 4c.

[0081] More specifically, the plurality of through holes 4rand wiring escapes 4vlarger in size than the wiring escapes 4vformed in the third wiring layer 4fas shown in FIG. 9 are formed in the first wiring layer 4don the surface of the core layer 4cas shown in FIG. 11. Accordingly, in the first signal wiring 8c(the first wiring 4mand the second wiring 4nshown in FIG. 6) of the second wiring layer 4eas shown in FIG. 10, it becomes difficult to arrange all of the first signal wirings 8caway from above the through holes 4rand the wiring escapes 4vof the first wiring layer 4d. As a result, signal wirings such as the first wirings 4mare inevitably arranged just above the through holes 4rand the wiring escapes 4vas shown in FIG. 6.

[0082] In contrast, in the second signal wirings 8din the fourth wiring layer 4gshown as shown in FIG. 8, the size of each wiring escape 4vof the lower third wiring layer 4fas shown in FIG. 9 is sufficiently smaller than each wiring escape 4vin the first wiring layer 4d. Therefore, the respective second signal wirings 8din the fourth wiring layer 4gcan be formed at positions away from the wiring escapes 4vof the third wiring layer 4f.

[0083] Consequently, in the package board 4 of the BGA 1 according to the first embodiment as shown in FIG. 6, relative to the first wiring 4mof the second wiring layer 4earranged above the through hole 4rof the core layer 4c, the thickness (D) of the first insulating layer 4ibetween the first wiring layer 4dthat is a plane layer on the surface of the core layer 4cand the second wiring layer 4eis made large, and the thickness (C) of the second insulating layer 4jbetween the third wiring layer 4fthat is a plane layer on the side opposite thereto and the second wiring layer 4eis made small.

[0084] This can reduce the impedance coupling between the power plane 8a, as shown in FIG. 11, of the first wiring layer 4dthat is a plane layer on the surface of the core layer 4cand the first and second wirings 4mand 4n, and can increase the impedance coupling between the power plane 8a, as shown in FIG. 9, of the third wiring layer 4fthat is a plane layer on the side opposite thereto and the first and second wirings 4mand 4n.

[0085] As a result, it becomes possible to control the characteristic impedance of the wirings with high accuracy, and to reduce the difference of the characteristic impedance between the first wiring 4marranged just above the through hole 4rand the second wiring 4narranged away from just above the through hole 4r.

[0086] For this reason, the improvement in the electric properties of the BGA 1 can be achieved.

[0087] Then, in attempting to reduce the variation in the characteristic impedance in the board structure shown in FIG. 6, the effect on calculation simulation will be described.

[0088] For example, in a conventional board, there is the thickness (D) of the first insulating layer 4iis equal to the thickness (C) of the second insulating layer 4j. So, if the characteristic impedance is calculated under the conditions that (D)=(C)=40 μm and each width of the first wiring 4mand the second wiring 4nis 50 μm, the characteristic impedance of the first wiring 4m(just above the through hole) is about 56.2 Ω and that of the second wiring 4n(above the power plane arranged away from the through hole 4r) is about 44.5 Ω.

[0089] This is for the reason that: when the signal is transmitted to the wirings, a feedback current flows through the plane layer opposite thereto; however, since there exist the holes formed in the course of the path of the feedback current, the inductance is increased. According to the values of the results of the above-mentioned calculation, the difference between them becomes about 12 Ω depending on patterns of the plane layer.

[0090] At this time, in view of the variations in the thickness of the insulating layer itself and in the width of the wiring from a design value, it is very difficult to control, for example, the variation in the characteristic impedance within ±15% (±7.5 Ω) relative to the characteristic impedance having a common target value of 50 Ω.

[0091] In contrast, in the package board 4 of the BGA 1 in the first embodiment, when the characteristic impedance is calculated under the conditions that, for example, the thickness (D) of the first insulating layer 4iis 50 μm and that (C) of the second insulating layer 4jis 30 μm and the respective widths of the first wiring 4mand the second wiring 4nare 40 μm, the characteristic impedance of the first wiring 4m(just above the through hole) is about 54.8 Ω and that of the second wiring 4n(above the power plane arranged away from the through hole 4r) is about 47.9 Ω.

[0092] As a result, the variation due to the wiring pattern in the plane layer is reduced to about 7 Ω, and it is possible to achieve an characteristic impedance of 50 Ω±15% even in the view of the respective variations in the thickness of the insulating layer itself and the width of the wiring.

[0093] This is because the impedance coupling of the first wiring 4mand the second wiring 4nto the power plane 8aof the third wiring layer 4fis reinforced by making the thickness of the first insulating layer 4ilarger than that of the second insulating layer 4jand making the thickness of the second insulating layer 4jsmaller than its original thickness. In this manner, the variation in the characteristic impedance can be reduced without changing the center value of the characteristic impedance between the wirings.

[0094] There are also means of: enlarging the width of only the signal wiring passing above the through-hole wiring; and reducing the difference in characteristic impedance between the signal wiring passing above it and the signal wiring not passing above it. However, it is quite effective to adjust the thickness of the insulating layer similarly to the first embodiment when the width of the wiring cannot be enlarged because of the limitation of the wiring pitch.

[0095] Note that, in the package board 4 in the first embodiment, in setting each thickness of the first insulating layer 4i, the second insulating layer 4j, the third insulating layer 4kand the fourth insulating layer 41, the thickness (A) of the fourth insulating layer 41 shown in FIG. 5 is desirably larger than that (C) of the second insulating layer 4jand smaller than that (D) of the first insulating layer 4i. Furthermore, the thickness (B) of the third insulating layer 4kis desirably larger than that (C) of the second insulating layer 4jand smaller than that (D) of the first insulating layer 4i.

[0096] More specifically, if the conditions that (D)>(A)>(C) and (D)>(B)>(C) are satisfied, the thickness (C) of the second insulating layer 4jis smaller than that (A) of the fourth insulating layer 4land that (B) of the third insulating layer 4k. Therefore, it is possible to make the characteristic impedance of the first signal wiring 8cof the second wiring layer 4enearly equal to that of the second signal wiring 8dof the fourth wiring layer 4g, and to reduce the variation in the characteristic impedance between the first signal wiring 8cand the second signal wiring 8d.

[0097] Also, the difference between the thickness (D) of the first insulating layer 4iand that (C) of the second insulating layer 4jis made larger than that of the first signal wiring 8cof the second wiring layer 4e. More specifically, each thickness of the first signal wiring 8cand the second signal wiring 8dis, for example, about 10 μm, and the difference in thickness between the first insulating layer 4iand the second insulating layer 4jis surely controlled so as to be larger than each thickness of the first signal wiring 8cand the second signal wiring 8d.

[0098] More specifically, the difference in thickness between the first insulating layer 4iand the second insulating layer 4jis not caused by the variation error of each thickness of them but is caused by the intentional control of the first insulating layer 4ito be larger in thickness than the second insulating layer 4j.

[0099] As described above, the package board 4 according to the first embodiment is more effectively applied to, for example, a semiconductor package such as the BGA 1 that performs a high-speed operation at 500 MHz.

[0100] (Second Embodiment)

[0101] FIG. 14 is a partially enlarged sectional view showing an example of a detailed structure of a multilayer circuit board in a semiconductor device (FC-BGA) according to a second embodiment of the present invention.

[0102] In a second embodiment, the case where the package board 4 of the BGA 1 has a build-up three layer wiring structure will be described.

[0103] More specifically, four insulating layers and four wiring layers are formed in the build-up layer 4zof the package board 4. First, similarly to the BGA 1 in the first embodiment, the first wiring layer 4dhaving the power plane 8aas shown in FIG. 11 is formed on the surface of the core layer 4c, and further the first insulating layer 4iis formed on the first wiring layer 4d. On this layer, the second wiring layer 4ehaving the first signal wiring 8cshown in FIG. 10, the second insulating layer 4j, the third wiring layer 4fhaving the power plane 8ashown in FIG. 9, the third insulating layer 4k, and the fourth wiring layer 4ghaving the second signal wiring 8dshown in FIG. 8 are sequentially laminated and arranged.

[0104] Additionally, the uppermost fourth wiring layer 4gis covered with an insulating film such as a resist film etc. to be the main surface 4aof the package board 4, and the semiconductor chip 2 is flip-chip bonded on the main surface 4a.

[0105] Also in the BGA 1 in the second embodiment, the gap between the first wiring layer 4dand the second wiring layer 4eis made larger than that between the second wiring layer 4eand the third wiring layer 4f, and also larger than that between the third wiring layer 4fand the fourth wiring layer 4g.

[0106] More specifically, the thickness (C) of the first insulating layer 4iis made larger than that (B) of the second insulating layer 4j, and preferably larger than that (A) of the third insulating layer 4k.

[0107] This, similarly to the first embodiment, can reduce the variation in the characteristic impedance between the wirings.

[0108] Also at this time, by making the thickness of the third insulating layer 4kequal to or smaller than that of the second insulating layer 4j, it is possible to reinforce the impedance coupling between the fourth wiring layer 4gand the third wiring layer 4fand to suppress the deviation in the center value of the characteristic impedance between the second wiring layer 4eand the fourth wiring layer 4g.

[0109] Also, similarly to the case described in the first embodiment, since the plurality of wiring escapes 4vwith a large area are formed in the power plane 8aof the first wiring layer 4d, the area of the conductive portion of the power plane 8ain the third wiring layer 4fis larger than that of the power plane 8ain the first wiring layer 4d.

[0110] Furthermore, the difference between the thickness (C) of the first insulating layer 4iand that (B) of the second insulating layer 4jis made larger than that of the first signal wiring 8cin the second wiring layer 4e. More specifically, each wiring thickness of the first signal wiring 8cand the second signal wiring 8dis, for example, about 10 μm. The difference in thickness between the first insulating layer 4iand the second insulating layer 4jis intentionally controlled to be certainly larger than each wiring thickness of the first signal wiring 8cand the second signal wiring 8d.

[0111] As described above, it is possible to obtain the same advantages as those in the first embodiment even in the case of the BGA 1 employing the package board 4 shown in the second embodiment.

[0112] More specifically, similarly to the first embodiment shown in FIG. 6, even if the first wiring 4mfor the signal is formed just above the through hole 4rand/or the wiring escape 4v, it is possible to reduce the difference of the characteristic impedance between the first wiring 4mand the second wiring 4nnot arranged above the through hole 4rand arranged away from the wiring escape 4v.

[0113] Furthermore, since the package board 4 of the second embodiment has the three insulating layers, the cost of the package board 4 can be reduced in comparison to the package board 4 in the first embodiment, whereby the cost of the BGA 1 can be also reduced.

[0114] In the foregoing, the invention made by the present inventors has been concretely described based on the embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments and can be variously modified and changed without departing from the gist thereof.

[0115] For example, the case where the BGA 1 is used as a semiconductor device has been described in the first and second embodiments. However, the above-mentioned semiconductor device may employ, for example, a PGA (Pin Grid Array), a LGA (Land Grid Array) or the like even if the semiconductor package utilizes the package board 4, which is a multilayer circuit board formed by the build-up process.

[0116] The advantages achieved by the typical ones of the inventions disclosed in this application will be briefly described as follows.

[0117] In the multilayer circuit board, the first wiring layer with the power plane is formed on the surface of the base member and the third wiring layer with the power plane is formed thereon via the insulating layer. Furthermore, the second wiring layer with the signal wiring is formed between the first and third wiring layers. In forming these layers, the gap between the first and second wiring layers is made larger than that between the second and third wiring layers, and the area of the power plane in the third wiring layer is made larger than that in the first wiring layer, thereby allowing for reducing the variation in the characteristic impedance of the wirings.