Self-aligned lateral-transistor DRAM cell structure

[0002] 1. Field of the Invention

[0003] The present invention relates generally to a lateral-transistor DRAM memory cell and its manufacturing methods and, more particularly, to a self-aligned lateral-transistor DRAM cell structure and its manufacturing methods.

[0004] 2. Description of Related Art

[0005] A dynamic random-access-memory (DRAM) cell including an access transistor and a storage capacitor has become the most important storage element in electronic system, especially in computer and communication system. The DRAM density is increased very rapidly in order to decrease the cost per bit and, therefore, an advanced photolithography is in general needed to decrease the minimum-feature-size (F) of a cell.

[0006] The output voltage of a DRAM cell is proportional to the capacitance value of the storage capacitor of the DRAM cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. Basically, the storage capacitor can be implemented in a trench-type or a stack-type. The trench-type is formed by forming a deep trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface. The stack-type is formed by implementing a capacitor structure over the access transistor and its nearby dummy-transistor structure through the conductive contact-plug over the node diffusion region of the access transistor. Basically, the cell size of the stack-type DRAM is limited by a dummy transistor being formed over the isolation region. Accordingly, the limit cell size of the stack-type DRAM is 8 F²for shallow-trench-isolation. However, the cell size of a trench-type lateral-transistor DRAM is limited by the space between nearby deep-trench capacitors and the separation between the lateral access transistor and the deep-trench capacitor. Therefore, the limit cell size of a trench-type lateral-transistor DRAM is also 8 F²if the separation between the lateral access transistor and the trench capacitor can't be minimized.

[0007] A typical example of a trench-type lateral-transistor DRAM cell is shown in FIG. 1, in which a deep trench is formed in a semiconductor substrate 100. A trench capacitor is formed in a lower portion of the deep trench, in which a lower capacitor node 101 is formed by a heavily-doped n+ diffusion region using an arsenic-silicate-glass (ASG) film as a dopant diffusion source; an upper capacitor node 103ais made of doped polycrystalline-silicon; and a capacitor-dielectric layer 102 is formed by a composite dielectric layer such as an oxide-nitride-oxide structure or a nitride-oxide structure. An oxide collar 104 is used to separate the lower capacitor node 101 from a source diffusion region 105a, 105b, and a capacitor-node connector 103bbeing made of doped polycrystalline-silicon is used to electrically connect the upper capacitor node 103ato a source conductive node 103c. The source conductive node 103cis made of heavily-doped polycrystalline-silicon to act as a dopant diffusion source for forming an n+ source diffusion region 105a. A shallow-trench-isolation (STI) region 106 is filled with a CVD-oxide layer in order to separate nearby trench capacitors. Two gate-stacks 108, 109 are formed over an upper surface, in which one gate-stack 108 is acted as a passing word-line and another gate-stack 109 is acted as an excess transistor. A common-source diffusion region 105b, 105aand a common-drain diffusion region 107 for a bit-line node are formed in an upper surface portion of the semiconductor substrate 100. From FIG.1, it is clearly seen that the limit cell size is 8 F²if the space between two nearby trench capacitors is defined to be a minimum-feature-size (F) of technology used.

[0008] Apparently, the common-source diffusion region 105bcan be removed and the gate-stack 109 shown in FIG. 1 can be formed in a self-aligned manner, then the semiconductor surface area occupied by a cell can be reduced to be 6 F².

[0009] It is, therefore, a major objective of the present invention to offer a self-aligned lateral-transistor DRAM cell structure for obtaining a cell size of 6 F²or smaller by using self-aligned techniques.

[0010] It is another objective of the present invention to easily offer different implant regions for forming punch-through stops and adjusting threshold-voltages of the lateral transistor and the parasitic collar-oxide transistor in a self-aligned manner so a deeper trench is not required.

[0011] It is a further objective of the present invention to offer a manufacturing method for forming a self-aligned lateral-transistor DRAM cell structure and its contactless DRAM arrays with less critical masking photoresist steps.

[0012] It is yet another objective of the present invention to offer two different contactless DRAM array structures for high-speed read and write operations.

[0013] A self-aligned lateral-transistor DRAM cell structure and its contactless DRAM arrays are disclosed by the present invention. The self-aligned lateral-transistor DRAM cell structure comprises a trench structure and a self-aligned lateral-transistor structure, in which the trench structure comprises a deep-trench region having a trench capacitor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and the self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, a self-aligned common-drain diffusion region, and different implant regions under the self-aligned lateral-transistor structure for forming punch-through stops of the self-aligned lateral-transistor and the parasitic collar-oxide transistor. The deep-trench region comprises a lower capacitor node made of an n+ diffusion region being formed in a lower portion of a deep trench, a capacitor-dielectric layer being formed over the lower capacitor node, an upper capacitor node being formed over the capacitor-dielectric layer, a collar-oxide layer together with a capacitor-node connector being formed over a portion of the capacitor-dielectric layer and the upper capacitor node, and a source conductive node defined by a first sidewall dielectric spacer being formed over the collar-oxide layer and the capacitor-node connector to act as a dopant diffusion source for forming a merged common-source diffusion region. The second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region comprises a second-type first raised field-oxide layer with a bottom surface level approximately equal to that of the collar-oxide layer and an n+ diffusion region being formed under the second-type first raised field-oxide layer. The self-aligned gate-stack region comprises a highly conductive-gate layer over a gate-dielectric layer being defined by a third sidewall dielectric spacer is formed outside of a second sidewall dielectric spacer. The self-aligned common-drain diffusion region of a second conductivity type comprises a lightly-doped common-drain diffusion region being formed by aligning to the self-aligned gate-stack region and a shallow heavily-doped common-drain diffusion region being formed within the lightly-doped common-drain diffusion region by aligning to a fourth sidewall dielectric spacer being formed over an outer sidewall of the self-aligned gate-stack region. The merged common-source diffusion region of the second conductivity type is formed near the source conductive node under the second sidewall dielectric spacer. The cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F²or smaller.

[0014] The self-aligned lateral-transistor DRAM cell structure of the present invention is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of self-aligned lateral transistor DRAM cells, a plurality of metal bit-lines integrated with planarized common-drain conductive islands being patterned to be aligned above a plurality of active regions, and a plurality of capping conductive-gate layers over conductive-gate layers to act as a plurality of conductive word-lines being formed transversely to the plurality of metal bit-lines. A second-type contactless DRAM array comprises a plurality of self-aligned lateral-transistor DRAM cells, a plurality of metal word-lines integrated with planarized capping conductive-gate islands over conductive-gate islands being patterned to be aligned above a plurality of active regions, and a plurality of highly conductive common-drain bus-lines acted as a plurality of conductive bit-lines being formed transversely to the plurality of metal word-lines.

[0015] FIG. 1 shows a typical schematic diagram of a trench-type lateral-transistor DRAM cell of the prior art.

[0016] FIG. 2A through FIG. 2C show the process steps and their cross-sectional views of fabricating a first-type shallow-trench-isolation structure for forming a self-aligned lateral-transistor DRAM cell structure of the present invention.

[0017] FIG. 3A through FIG. 3J show the process steps and their cross-sectional views of fabricating a common platform structure for a self-aligned lateral-transistor DRAM cell structure of the present invention.

[0018] FIG. 4A through FIG. 4E show the process steps and their cross-sectional views of fabricating a self-aligned lateral-transistor DRAM cell structure and its first-type contactless DRAM array of the present invention after FIG. 3J.

[0019] FIG. 5A through FIG. 5E show the process steps and their cross-sectional views of fabricating a self-aligned lateral-transistor DRAM cell structure and its second-type contactless DRAM array of the present invention after FIG. 3J.

[0020] FIG. 6A shows a top plan view of a first-type contactless DRAM array of the present invention.

[0021] FIG. 6B shows a top plan view of a second-type contactless DRAM array of the present invention.

[0022] Referring now to FIG. 2A through FIG. 2C, there are shown the process steps and their cross-sectional views of fabricating a first-type shallow-trench-isolation (STI-1) structure for forming a self-aligned lateral-transistor DRAM cell structure of the present invention. FIG. 2A shows that a first dielectric layer 301 is formed on a semiconductor substrate 300 of a first conductivity type, a first conductive layer 302 is formed on the first dielectric layer 301, a first masking dielectric layer 303 is formed over the first conductive layer 302, and a plurality of masking photoresist PR1 are formed over the first masking dielectric layer 303 to define a plurality of active regions (under PR1) and a plurality of first-type STI regions (STI-1) (outside of PR1). The first dielectric layer 301 is preferably a thermal-oxide layer or a nitrided thermal-oxide layer and its thickness is preferably between 50 Angstroms and 200 Angstroms. The first conductive layer 302 is preferably a doped polycrystalline-silicon or doped amorphous-silicon layer as deposited by low-pressure chemical-vapor-deposition (LPCVD) and its thickness is preferably between 200 Angstroms and 3000 Angstroms. The first masking dielectric layer 303 is preferably made of silicon-nitride as deposited by LPCVD and its thickness is preferably between 1000 Angstroms and 3000 Angstroms. It should be noted that a first anti-reflection coating (ARC) layer (not shown) can be formed over the first masking dielectric layer 303 to act as a hard masking layer for patterning the first masking dielectric layer 303. FIG. 2A shows that each of the plurality of active regions (AA) and each of the plurality of first-type STI regions (STI-1) can be defined to be a minimum-feature-size (F) of technology used.

[0023] FIG. 2B shows that the first masking dielectric layer 303, the first conductive layer 302, and the first dielectric layer 301 outside of the plurality of masking photoresist PR1 are sequentially removed by using anisotropic dry etching; the semiconductor substrate 300 is then anisotropically etched to form first-type shallow trenches, and the plurality of masking photoresist PR1 are then stripped; and subsequently, the first-type shallow trenches are refilled with first-type planarized field-oxide layers 304a. The depth of the first-type shallow trenches in the semiconductor substrate 300 is between 4000 Angstroms and 15000 Angstroms. The first-type planarized field-oxide layer 304ais preferably made of silicon-dioxide, phosphosilicate glass (p-glass), or boro-phosphosilicate glass (BP-glass) as deposited by high-density plasma (HDP) CVD or plasma-enhanced (PE) CVD, and is formed by first depositing a thick-oxide film 304 to fill up each gap formed by the first-type shallow trenches and then planarizing the deposited thick-oxide film 304 using chemical-mechanical polishing (CMP) with the first masking dielectric layer 303aas a polishing stop.

[0024] FIG. 2C shows that the first-type planarized field-oxide layers 304aare etched back to a depth equal to a thickness of the first masking dielectric layer 303ato form first-type first raised field-oxide layers 304band then the first masking dielectric layers 303aare removed by using hot-phosphoric acid or anisotropic dry etching; and subsequently, a second masking dielectric layer 305 is formed over a flat surface being alternately formed by the first conductive layer 302aand the first-type first raised field-oxide layer 304b. The second masking dielectric layer 305 is preferably made of silicon-nitride as deposited by LPCVD and its thickness is preferably between 3000 Angstroms and 10000 Angstroms. The cross-sectional view along an active region as indicated by a C-C′ line is shown in FIG. 3A.

[0025] Referring now to FIG. 3A through FIG. 3J, there are shown the process steps and their cross-sectional views of fabricating a common platform structure for a self-aligned lateral-transistor DRAM cell structure of the present invention. FIG. 3A shows that a plurality of deep trenches are formed in the semiconductor substrate 300, which includes a masking photoresist step for patterning the second masking dielectric layer 305, an anisotropic dry etching process to sequentially remove the first conductive layer 302aand the first dielectric layer 301a, and a deep-trench etching process. It should be noted that the first-type first raised field-oxide layers 304bin each of the plurality of first-type STI regions are also slightly etched during the removal of the first dielectric layers 301ato form first-type second raised field-oxide layers 304cbetween the second masking dielectric layers 305a. FIG. 3A also shows that the width of the deep trenches (DT) can be defined to be a minimum-feature-size (F) of technology used; the space between the nearby deep-trenches (DT) is a trench-isolation region, which can also be defined to be a minimum-feature-size of technology used; and a self-aligned lateral-transistor region is defined by X₁F, wherein X₁is a scale factor.

[0026] FIG. 3B shows that a lower capacitor node 306amade of a heavily-doped n+ diffusion region is formed in a lower portion of the deep trench; a capacitor-dielectric layer 307 is then formed over a formed structure surface; an upper capacitor node 308bis formed in a lower portion of the deep trench; and subsequently, an ion-implantation is performed in a self-aligned manner to heavily dope the upper capacitor nodes 308bwith a high dose of doping impurities of a second conductivity type. The lower capacitor node 306ais formed by the following steps: depositing an arsenic-silicate-glass (ASG) film over a formed structure surface shown in FIG. 3A, forming an etched-back photoresist layer in a lower portion of the deep trench, removing the arsenic-silicate-glass film over a top surface level of the etched-back photoresist layer, removing the etched-back photoresist layer, forming a capping silicon-dioxide layer over the formed structure surface, performing a drive-in process to diffuse the dopants in the remained arsenic-silicate-glass films into the semiconductor substrate 300 to form the lower capacitor nodes 306a, and removing the capping silicon-dioxide layer and the remained arsenic-silicate-glass films. The capacitor-dielectric layer 307 is preferably made of a composite dielectric layer such as an oxide-nitride-oxide (ONO) structure or a nitride-oxide (NO) structure. The upper capacitor node 308bis preferably made of doped polycrystalline-silicon as deposited by LPCVD and is formed by first forming a planarized doped polycrystalline-silicon layer 308ato fill up each gap formed over the deep trenches and then etching back the planarized doped polycrystalline-silicon layer 308bto form the upper capacitor nodes 308bin the lower portion of the deep trenches.

[0027] FIG. 3C shows that the capacitor-dielectric layer 307 above a top surface level of the upper capacitor node, 308bis removed by wet etching or isotropic dry etching; a silicon-dioxide layer 309 is deposited over a formed structure surface and is then etched back a thickness of the deposited silicon-dioxide layer 309 to form a sidewall silicon-dioxide spacer 309aover each sidewall of the deep trenches; a planarized doped polycrystalline-silicon layer 310ais formed to fill up each gap between the sidewall silicon-dioxide spacers 309aand is then etched back to form capacitor-node connector layers 310b; and subsequently, an ion-implantation is performed to heavily dope the capacitor-node connector layers 310bwith a high dose of doping impurities of the second conductivity type.

[0028] FIG. 3D shows that the sidewall silicon-dioxide spacers 309aabove a top surface level of the capacitor-node connector layer 310bare removed to form a collar-oxide layer 309bin each of the deep trenches by dipping in buffered hydrofluoric acid or dilute hydrofluoric acid solution; a source conductive layer 311bis formed over the collar-oxide layer 309band the capacitor-node connector layer 310b; a protective silicon-dioxide layer 312 is formed over a formed structure surface; and subsequently, an ion-implantation is performed to implant a high dose of doping impurities of the second conductivity type into the source conductive layers 311bin a self-aligned manner to act as the dopant diffusion sources for forming merged common-source diffusion regions 318ain a later process. The source conductive layer 311bis preferably made of doped polycrystalline-silicon or intrinsic polycrystalline-silicon as deposited by LPCVD and is formed by first depositing, then planarizing, and etching back, and the top surface level of the source conductive layer 311bis approximately equal to the top surface of the semiconductor substrate 300. The protective silicon-dioxide layer 312 is preferably deposited by LPCVD or HTO deposition and its thickness is preferably between 100 Angstroms and 500 Angstroms. It should be noted that the protective silicon-dioxide layer 312 is mainly used to prevent the trench surface from ion-implantation and also to control the depth of ion-implantation for forming a graded common-source doping profile in nearby semiconductor substrate 300.

[0029] FIG. 3E shows that a first planarized thick-oxide layer 313ais formed over the etched protective silicon-dioxide layer 312ausing CMP, a plurality of masking photoresist (PR3) are formed over the self-aligned lateral-transistor regions and a portion of nearby trench regions. The first planarized thick-oxide layer 313ais preferably made of silicon-dioxide, P-glass, or BP-glass as deposited by LPCVD, HDPCVD, or PECVD.

[0030] FIG. 3F shows that the second masking dielectric layers 305abetween the plurality of masking photoresist (PR3) are selectively removed by anisotropic dry etching; the first conductive layers 302band the first dielectric layers 301bare sequentially removed by anisotropic dry etching; and subsequently, the exposed semiconductor substrates 300 are anisotropically etched to a depth approximately equal to a bottom surface level of the collar-oxide layer 309bfor forming second-type STI regions (STI-2) and an ion-implantation process can be performed by implanting a high dose of doping impurities into the semiconductor substrate 300 in a self-aligned manner to form the heavily-implanted regions 314aof the second conductivity type in the semiconductor substrate 300 between nearby trench capacitors, and then the plurality of masking photoresist (PR3) are stripped. It should be noted that the heavily-implanted region 314ais connected with the lower capacitor nodes 306aof the nearby trench capacitors.

[0031] FIG. 3G shows that a second-type planarized field-oxide layer 315ais formed over a gap in a trench-isolation region between the nearby trench regions and various silicon-dioxide layers between the second masking dielectric layers 305aare etched back to a top surface level of the source conductive layers 311bby anisotropic dry etching or wet etching to form a flat surface between the self-aligned lateral-transistor regions; and a pair of first sidewall dielectric spacers 316aare formed over sidewalls formed by the second masking dielectric layer 305aover the first conductive layer 302band on a portion of the source conductive layers 311band the first-type fourth raised field-oxide layers 304ein each of the plurality of trench regions. The second-type first planarized field-oxide layer 315bis preferably made of silicon-dioxide, P-glass, or BP-glass as deposited by LPCVD, HDPCVD, or PECVD. The first sidewall dielectric spacer 316ais preferably made of silicon-dioxide as deposited by LPCVD and is formed by first depositing a silicon-dioxide layer 316 over a formed structure surface and then etching back a thickness of the deposited silicon-dioxide layer 316.

[0032] FIG. 3H shows that the source conductive layers 311band the capacitor-node connector layers 310bbetween the pair of first sidewall dielectric spacers 316aare sequentially removed by anisotropic dry etching to form source conductive nodes 311cand capacitor-node connectors 310c, respectively; and subsequently, a second planarized thick-oxide layer 317ais formed between the second masking dielectric layers 305ain the self-aligned lateral-transistor regions. The second planarized thick-oxide layer 317ais preferably made of silicon-oxide as deposited by LPCVD, HDPCVD, or PECVD and is formed by first depositing a thick-oxide layer 317 to fill up each gap between the pair of first sidewall dielectric spacers 316aand then planarizing the deposited thick-oxide layer 317 using CMP with the second masking dielectric layer 305aas a polishing stop. It is clearly seen that a pair of source conductive nodes 311care further separated in a self-aligned manner to reduce the coupling effect between the pair of source conductive nodes 311c.

[0033] FIG. 3I shows that the second masking dielectric layers 305aover the self-aligned lateral-transistor regions are removed by hot-phosphoric acid or anisotropic dry etching; the formed structure including various silicon-dioxide layers is then etched back anisotropically to a depth equal to a thickness of the first conductive layer 302b, and the first conductive layers 302bare removed by anisotropic dry etching to form a flat surface being alternately formed by a first dielectric layer 301band a first-type third raised field-oxide layer 304d; and subsequently, an implant region 319 can be formed in the semiconductor substrate 300 of each of the plurality of active regions in a self-aligned manner by implanting doping impurities across the first dielectric layers 301b. The implant region may comprise a deep implant region 319 of the first conductivity type being formed in the semiconductor substrate 300 near a middle portion outside of the collar-oxide layer 309bin each of the plurality of active regions. The deep implant region 319 is used to form a punch-through stop and to simultaneously adjust the threshold-voltage of the parasitic collar-oxide transistor. It is clearly seen that the separation between the merged common-source diffusion region 318aand the lower capacitor node 306acan be made to be smaller without concerning the punch-through effect. Accordingly, the depth of the deep trenches can be made to be shallower for the present invention as compared to the prior art.

[0034] FIG. 3J shows that a pair of second sidewall dielectric spacers 320aare formed over outer sidewalls of nearby etched-back first sidewall dielectric spacers 316band on a portion of the flat surface being alternately formed by the first dielectric layer 301band the first-type third raised field-oxide layer 304d; and subsequently, an ion-implantation process is performed by implanting doping impurities of the first conductivity type across the first dielectric layer 301binto the semiconductor substrate 300 in a self-aligned manner to form the implant region 321ain each of the plurality of active regions. The second sidewall dielectric spacer 320ais preferably made of silicon-dioxide as deposited by LPCVD and its spacer width is approximately equal to or slightly smaller than the width of the merged common-source diffusion region 318ato reduce the overlapping capacitance between the conductive-gate layer 323b(see FIG. 4A) and the merged common-source diffusion region 318a. The implant region 321acomprises a shallow implant region as marked by a dash line for threshold-voltage adjustment of the lateral transistor and a deep implant region as marked by the cross symbols for forming a punch-through stop of the lateral transistor.

[0035] Referring now to FIG. 4A through FIG. 4E, there are shown the process steps and their cross-sectional views for fabricating a first-type self-aligned lateral-transistor DRAM cell structure and its first-type DRAM array of the present invention after FIG. 3J.

[0036] FIG. 4A shows that the first dielectric layers 301bbetween the pair of second sidewall dielectric spacers 320aare removed by dipping in a dilute hydrofluoric acid solution or anisotropic dry etching and the first-type third raised field-oxide layers 304dare simultaneously etched to form the first-type fourth raised field-oxide layers 304e; a gate-dielectric layer 322ais then formed over the exposed semiconductor substrate 300 in each of the plurality of active regions between the pair of second sidewall dielectric spacers 320a; a conductive-gate layer 323bis formed between the pair of second sidewall dielectric spacers 320aand on the gate-dielectric layers 322aand the first-type fourth raised field-oxide layers 304e; and a capping conductive-gate layer 324bis then formed over the conductive-gate layer 323band a pair of third sidewall dielectric spacers 325aare formed over a portion of the capping conductive-gate layer 324bto define a pair of self-aligned gate-stack regions in each of the self-aligned lateral-transistor regions. The gate-dielectric layer 322ais preferably a thermal-oxide layer or a nitrided thermal-oxide layer as grown by a well-known thermal oxidation process. The conductive-gate layer 323bis preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and is formed by first depositing a thick conductive film 323 to fill up a gap between the pair of second sidewall dielectric spacers 320aand planarizing the deposited thick conductive film 323 using CMP or etching-back, and then etching back the planarized conductive-gate layers 323ato a predetermined thickness. The capping conductive-gate layer 324bis preferably made of tungsten disilicide or tungsten as deposited by LPCVD or sputtering and is formed by a similar method as described for the conductive-gate layer 323b. The third sidewall dielectric spacer 325ais preferably made of silicon-dioxide, silicon-nitride, or silicon-oxynitride as deposited by LPCVD and is formed by depositing a dielectric layer 325 and then etching back a thickness of the deposited dielectric layer 325. Therefore, the gate length of the lateral transistors can be easily controlled by the thickness of the deposited dielectric layer 325 and is scalable.

[0037] FIG. 4B shows that the capping conductive-gate layer 324band the conductive-gate layer 323bbetween the pair of third sidewall dielectric spacers 325aare sequentially removed by using anisotropic dry etching and an ion-implantation is performed by implanting doping impurities across the gate-dielectric layers 322ainto the semiconductor substrate 300 to form a lightly-doped common-drain diffusion region 326aof the second conductivity type in each of the plurality of active regions.

[0038] FIG. 4C shows that a pair of fourth sidewall dielectric spacers 327aare formed over outer sidewalls of the pair of third sidewall dielectric spacers 325aand on a portion of the gate-dielectric layers 322aand the first-type fourth raised field-oxide layers 304e, and an ion-implantation process is performed by implanting a high dose of doping impurities across the gate-dielectric layers 322ain a self aligned manner to form a shallow heavily-doped common-drain diffusion 326bregion of the second conductivity type within the lightly-doped common-drain diffusion region 326a. The fourth sidewall dielectric spacer 327ais preferably made of silicon-dioxide, silicon-nitride, or silicon-oxynitride as deposited by LPCVD.

[0039] FIG. 4D shows that the gate-dielectric layers 322abetween the pair of fourth sidewall dielectric spacers 327aare removed by dipping in a dilute hydrofluoric acid solution and the first-type fourth raised field-oxide layers 304eare simultaneously etched to form a flat bed being alternately formed by the shallow heavily-doped common-drain diffusion region 326band a first-type fifth raised field-oxide layer 304f; and subsequently, a planarized common-drain conductive layer 328ais formed over the flat bed between the pair of fourth sidewall dielectric spacers 327ain each of the common-drain regions. The planarized common-drain conductive layer 328ais preferably made of doped polycrystalline-silicon and is further heavily implanted with a high-dose of doping impurities of the second conductivity type. The planarized common-drain conductive layer 328acan be silicided with a refractory metal-silicide layer such as a titanium-disilicide (TiSi₂) or cobalt-disilicide (CoSi₂) layer. Similarly, the planarized common-drain conductive layer 328amay comprise a planarized tungsten layer being lined with a barrier-metal layer such as a-titanium-nitride (TiN) or tantalum-nitride (TaN) layer.

[0040] FIG. 4E shows that a metal layer 329 is formed over a formed structure surface shown in FIG. 4D; the metal layer 329 and the planarized common-drain conductive layers 328aare simultaneously patterned and etched by a masking photoresist step being aligned above the plurality of active regions to form a plurality of metal bit-lines 329aintegrated with planarized common-drain conductive islands 328b. The metal layer 329 comprises an aluminum or copper layer over a barrier-metal layer. The mask photoresist step comprises a plurality of masking photoresist being aligned above the plurality of active regions or a plurality of hard masking dielectric layers being aligned above the plurality of active regions and a sidewall dielectric spacer being formed over each sidewall of the plurality of hard masking dielectric layers to eliminate misalignment FIG. 4E shows a first-type self-aligned lateral-transistor DRAM cell structure and its first-type contactless DRAM array of the present invention.

[0041] Referring now to FIG. 5A through FIG. 5E, there are shown the process steps and their cross-sectional views for fabricating a first-type self-aligned lateral-transistor DARM cell structure and its second-type DRAM array of the present invention after FIG. 3J.

[0042] FIG. 5A shows that the first dielectric layers 301bbetween the pair of second sidewall dielectric spacers 3209 are removed by dipping in a dilute hydrofluoric acid solution or anisotropic dry etching and the first-type third raised field-oxide layers 304dare simultaneously etched to form the first-type fourth raised field-oxide layers 304e; a gate-dielectric layer 322ais then formed over the exposed semiconductor substrate 300 in each of the plurality of active regions between the pair of second sidewall dielectric spacers 320a; a conductive-gate layer 323bis formed between the pair of second sidewall dielectric spacers 320aand on the gate-dielectric layers 322aand the first-type fourth raised field-oxide layers 304e; and a pair of third sidewall dielectric spacers 330aare formed over a portion of the conductive-gate layer 323bto define a pair of self-aligned gate-stack regions in each of the self-aligned lateral-transistor regions. The gate-dielectric layer 322ais preferably a thermal-oxide layer or a nitrided layer as grown by a well-known thermal oxidation process. The conductive-gate layer 323bis preferably made of doped polycrystalline-silicon or doped amorphous-silicon as deposited by LPCVD and is formed by first depositing a thick conductive film 323 to fill up a gap between the pair of second sidewall dielectric spacers 320aand planarizing the deposited thick conductive film 323 using CMP or etching-back, and then etching back the planarized conductive-gate layers 323ato a predetermined thickness. The third sidewall dielectric spacer 330ais preferably made of silicon-nitride as deposited by LPCVD and is formed by depositing a dielectric layer 330 and then etching back a thickness of the deposited dielectric layer 330. Therefore, the gate length of the lateral transistors can be easily controlled by the thickness of the deposited dielectric layer 330. FIG. 5A also shows that the conductive-gate layer 323bbetween the pair of third sidewall dielectric spacers 330aare sequentially removed by using anisotropic dry etching and an ion-implantation is performed by implanting doping impurities across the gate-dielectric layers 322ainto the semiconductor substrate 300 in a self-aligned manner to form a lightly-doped common-drain diffusion region 326aof the second conductivity type in each of the plurality of active regions.

[0043] FIG. 5B shows that a pair of fourth sidewall dielectric spacers 327aare formed over outer sidewalls of the pair of third sidewall dielectric spacers 330aand on a portion of the gate-dielectric layers 322aand the first-type fourth raised field-oxide layers 304e, and an ion-implantation process is performed by implanting doping impurities across the gate-dielectric layers 322ainto the semiconductor substrate 300 in a self-aligned manner to form a shallow heavily-doped common-drain diffusion region 326bof the second conductivity type within the lightly-doped common-drain diffusion region 326a. The fourth sidewall dielectric spacer 327ais preferably made of silicon-dioxide as deposited by LPCVD.

[0044] FIG. 5C shows that the gate-dielectric layers 322abetween the pair of fourth sidewall dielectric spacers 327aare removed by dipping in a dilute hydrofluoric acid solution or anisotropic dry etching, and the first-type fourth raised field-oxide layers 304eare simultaneously etched to form a flat bed between the pair of fourth sidewall dielectric spacers 327ain each of the common-drain regions, as described in FIG. 4D; a doped polycrystalline-silicon layer 331bcapped with a tungsten-disilicide (WSi₂) or tungsten (W) layer 332bor silicided with a refractory metal-silicide layer 332bsuch as a titanium-disilicide (TiSi₂) or cobalt-disilicide (CoSi₂) layer is formed over the flat bed to act as a common-drain conductive bit-line 332b/331b; and a third planarized thick-oxide layer 333ais formed over the common-drain conductive bit-line 332b/331bin each of the common-drain regions. The third planarized thick-oxide layer 333ais preferably made of silicon-dioxide, P-glass, or BP-glass as deposited by LPCVD, HDPCVD, or PECVD. The doped polycrystalline-silicon layer 331bis preferably deposited by LPCVD and is further implanted with a high-dose of doping impurities of the second conductivity type.

[0045] FIG. 5D shows that various silicon-dioxide layers as shown in FIG. 5C are etched back to eliminate the curve portions of the pair of fourth sidewall dielectric spacers 327aand the pair of third sidewall dielectric spacers 330aare then removed by hot-phosphoric acid or anisotropic dry etching; and subsequently, the planarized capping conductive-gate layers 334aare refilled. The planarized capping conductive-gate layer 334ais preferably made of tungsten-disilicide (WSi2) or tungsten (W) as deposited by LPCVD or sputtering and is formed by first depositing a thick conductive layer 334 to fill up each gap between the etched fourth sidewall dielectric spacer 327band the etched second sidewall dielectric spacer 320band then planarizing the deposited thick conductive layer 334 using CMP or etching-back technique. It should be noted that a barrier-metal layer can be deposited before depositing the thick conductive layer 334 as a liner.

[0046] FIG. 5E shows that a metal layer 335 is formed over a formed structure surface as shown in FIG. 5D and a metal layer 335 together with the planarized capping conductive-gate layers 334aover the conductive-gate layers 323care simultaneously patterned by a masking photoresist step as described in FIG. 4E to form the plurality of metal word-lines 335aintegrated with planarized capping conductive-gate islands 334bover conductive-gate islands 323d. The metal layer 335 may comprise an aluminum or copper layer over a barrier-metal layer such as a titanium-nitride (TiN) or tantalum-nitride (TaN) layer.

[0047] FIG. 6A shows a top plan view of the first-type contactless DRAM array, in which the plurality of metal bit-lines (BL) 329aintegrated with the planarized common-drain conductive islands 328bare formed to be aligned above the plurality of active regions (AA), wherein the planarized common-drain conductive islands 328bare formed over the shallow heavily-doped common-drain diffusion regions 326bbetween the pair of fourth sidewall dielectric spacers 327a; the plurality of first-type STI regions (STI-1) and the plurality of active regions (AA) are formed alternately on said semiconductor substrate 300; the plurality of conductive word-lines (WL) 324cbeing connected with the conductive-gate layers 323care defined by a pair of third sidewall dielectric spacers 325a. The source conductive node 311cis partially formed in the deep trench (DT) and is patterned by a first sidewall dielectric spacer 316a; and the second-type STI region (STI-2) being filled with the second-type first raised field-oxide layer 315bis formed in the active region. From FIG. 6A, the unit cell size as marked by a dash square can be made to be equal to or smaller than 6 F²if the width of the self-aligned lateral-transistor region is defined to be equal to or smaller than 1.5 F.

[0048] FIG. 6B shows a top plan view of a second-type contactless DRAM array of the present invention, in which the plurality of metal word-lines (WL) 335aintegrated with the planarized capping conductive-gate islands 334bover the conductive-gate islands 323dare formed to be aligned above the plurality of active regions (AA); each of the plurality of conductive bit-lines (BL) 332bover the heavily-doped polycrystalline-silicon layer 331bbeing formed between the pair of fourth sidewall dielectric spacers 327bis formed over the flat bed being alternately formed by the shallow heavily-doped common-drain diffusion region 326band the first-type fifth raised field-oxide layer 304f; the plurality of first-type STI regions (STI-1) and the plurality of active regions (AA) are formed alternately on the semiconductor substrate 300; each of the plurality of deep trenches (DT) is partially filled with the source conductive node 311c; the second-type STI region (STI-2) is formed between the pair of deep-trenches (DT); and the pair of first sidewall dielectric spacers 316care formed over each sidewall of nearby self-aligned lateral-transistor regions to define the source conductive nodes 311c. Similarly, a cell size of the second-type self-aligned lateral-transistor DRAM cell structure as marked by a dash square can be made to be equal to 6 F²or smaller if the width of the self-aligned lateral transistor region is defined to be equal to or smaller than 1.5 F².

[0049] Accordingly, the advantages and the features of a self-aligned lateral-transistor DRAM cell structure and its contactless DARM arrays of the present invention are summarized as below:

[0050] (a) The self-aligned lateral-transistor DRAM cell structure of the present invention may offer a DRAM cell size of 6 F²or smaller through reducing the surface area occupied by the self-aligned lateral-transistor region using self-aligned techniques.

[0051] (b) The self-aligned lateral-transistor DRAM cell structure of the present invention can be fabricated with less critical masking photoresist steps to reduce the cost of manufacturing.

[0052] (c) The self-aligned lateral-transistor DRAM cell structure of the present invention can be fabricated by using a shallower depth of the deep trenches by decreasing the separation length of the collar-oxide layer through self-aligned ion-implantation.

[0053] (d) The self-aligned lateral-transistor DRAM cell structure of the present invention offers the second-type STI regions with a depth approximately equal to a bottom surface level of the collar-oxide layer for nearby DRAM capacitors to reduce the possible coupling effects between the nearby DRAM cells.

[0054] (e) The first-type contactless DRAM array of the present invention offers the plurality of metal bit-lines integrated with the planarized common-drain conductive islands and the plurality of conductive word-lines for obtaining high-speed read and write operations.

[0055] (f) The second-type contactless DRAM array of the present invention offers the plurality of metal word-lines integrated with the planarized capping conductive-gate islands over the conductive-gate islands and the plurality of conductive bit-lines for obtaining high-speed read and write operations.

[0056] While the present invention has been particularly shown and described with references to the present examples and embodiments as considered as illustrative and not restrictive. Moreover, the present invention is not to be limited to the details given herein, it will be understood by those skilled in the art that various changes in forms and details may be made without departure from the true spirit and scope of the present invention.