Recording apparatus having a pause mode in which video signals are written to memory by cyclically designating write addresses

[0002] 1. Field of the Invention

[0003] The present invention relates to recording apparatuses, and in particular, to a recording apparatus that records video signals on a recording medium.

[0004] 2. Description of the Related Art

[0005] Conventional camcorders are known as examples of the recording apparatuses.

[0006] In camcorders, a predetermined time lag is necessary from a user's instruction to start recording until recording actually starts. This causes a problem in that if the user activates recording when the user wants to record, it is often too late to record the scene, and the user may feel that the utility of the camcorder is limited.

[0007] Accordingly, it is an object of the present invention to provide a recording apparatus to solve the above problem.

[0008] It is another object of the present invention to provide a recording apparatus that securely records the desired image, no matter how recording is activated.

[0009] To these ends, according to the present invention, the foregoing objects are achieved through provision of a recording apparatus including a storage unit for holding video signals; a control unit for controlling the operation of the storage unit; a recording unit for recording the video signals read from the storage unit; and a mode-setting unit for selectively setting one of a plurality of modes including a recording mode in which the control unit stores the video signals in the storage unit, and the recording unit records the video signals read from the storage unit, and a recording pause mode in which the control unit stores the video signals in the storage unit by cycling through selecting storage addresses of the storage unit at which the video signals are stored, and the recording of the video signals is terminated.

[0010] According to a further aspect of the present invention, a recording apparatus includes a memory storing video signals of n frames where n represents an integer not less than 2. Recording means are provided for recording, on a recording medium, the video signals read from the memory. Instruction means manually instructs a start of the recording of the video signals by the recording means. Control means controls the storing operation of the memory and the recording operation of the recording means. The control means also writes the video signals into the memory by cyclically designating write addresses of the memory. The control means controls the memory and the recording, means so that, in accordance with an instruction received from the instruction means, video signals corresponding to the (n−1)th frame at the time of the instruction are read from the memory and recorded by the recording means.

[0011] According to yet another aspect of the present invention, a recording apparatus includes a memory storing video signals of n frames where n represents an integer not less than 2. Recording means are provided for recording, on a recording medium, the video signals read from the memory. Instruction means manually instructs a stop of the recording of the video signals by the recording means, and control means controls the storing operation of the memory and the recording operation of the recording means. The control means writes the video signals into the memory by cyclically designating write addresses of the memory. The control means also controls the memory and the recording means so that, in accordance with an instruction received by the instruction means, the video signals of n frames, from the time of the instruction, are read, and after that, the recording of the video signals by the recording means is stopped.

[0012] In accordance with another aspect of the present invention, a recording means comprises a memory storing video signals of n frames where n represents an integer not less than 2. Recording means are provided for recording, on a recording medium, the video signals read from the memory. A first instruction means manually instructs a start of the recording of the video signals by the recording means, while a second instruction means manually instructs a stop of the recording of the video signals by the recording means. Control means controls the storing operation of the memory and the recording operation of the recording means. The control means writes the video signals into the memory by cyclically designating write addresses of the memory. The control means controls the memory and the recording means so that, in accordance with an instruction received by the instruction means, video signals corresponding to the (n−1)th frame at the time of the instruction from the first instruction means are read from the memory and recorded on the recording means. The control means controls the memory and the recording means so that, in accordance with an instruction received by the second instruction means, the video signals for n frames from the time of the instruction of the second instruction means are read before the recording of the video signals by the recording means is terminated.

[0013] Other objects and features of the present invention will be apparent based on the following embodiments described with reference to the accompanying drawings.

[0014] FIG. 1 is a block diagram showing a recording apparatus according to an embodiment of the present invention;

[0015] FIG. 2 is a block diagram showing the video-signal processing circuit 105 shown in FIG. 1;

[0016] FIGS. 3A and 3B are drawings showing the structure of the memory 107 shown in FIG. 1;

[0017] FIG. 4 is a drawing showing bit assignment to memory addresses;

[0018] FIG. 5 is a drawing showing the storing of data to the memory 107 shown in FIG. 1, and the reading of data from the memory 107;

[0019] FIG. 6 is a block diagram showing the recording processing circuit 219 shown in FIG. 2; and

[0020] FIG. 7 is a timing chart illustrating the operation of the recording processing circuit 219 shown in FIG. 2.

[0021] An embodiment of the present invention is described below with reference to the accompanying drawings.

[0022] FIG. 1 shows a recording apparatus 100 to which the present invention is applied.

[0023] First, the operation of the recording apparatus 100 in the recording mode is described.

[0024] An image capture unit 101 includes a charge-coupled device, a sample-and-hold circuit, and an analog-to-digital converter, and outputs digital video signals to a camera-signal processing circuit 103. The camera-signal processing circuit 103 performs processes on the digital video signal from the image capture unit 101, such as separation into luminance signals and chrominance signals, aperture correction, and white-balance adjustment, and uses a video-signal processing circuit 105 to store video signals obtained from the processes in a memory 107. The storage operation of the memory 107 is described below.

[0025] The video-signal processing circuit 105 performs processes such as compression and encoding (described below) for the video signal stored in the memory 107, and outputs the processed video signals to a recording circuit 109. The video-signal processing circuit 105 also outputs the encoded video signals to a terminal 111. The recording circuit 109 performs the predetermined processing of the video signals output from the video-signal processing circuit 105 so that the video signals are converted to have a form adapted for recording, and records the processed signal on the recording medium 113. In this embodiment, a magneto-optical disk is used as the recording medium 113, and the recording circuit 109 has a mechanism for driving the magneto-optical disk 113.

[0026] Second, the operation of the recording apparatus 100 in the play mode is described.

[0027] The recording circuit 109 reproduces video signals from the magneto-optical disk 113, and outputs them to the video-signal processing circuit 105. The video-signal processing circuit 105 decodes the reproduced video signals by performing processes converse to those in the recording mode, and simultaneously decompresses and outputs the information of the reproduced video signals from a terminal 119.

[0028] A system control circuit 115 performs control (described below) of each circuit or unit. An operation unit 117 includes a main-power switch and switches for instructing various modes including recording and reproduction.

[0029] In this construction, when power is supplied by operating the main-power switch of the operation unit 117, the system control circuit 115 controls the mechanism of the recording circuit 109 to start rotation of the disk 113, whereby the recording pause mode is activated. In the recording pause mode, when a recording trigger switch in the operation unit 117 is operated, the system control circuit 115 sets the recording apparatus 100 in the recording mode and initiates recording of the video signals on the disk 113, as described above. In the recording mode, when the recording trigger switch in the operation unit 117 is operated, the system control circuit 115 sets the recording apparatus 100 in the recording mode again. Subsequently, whenever the recording trigger switch is operated, the mode of the recording apparatus 100 is switched between the recording mode and the recording pause mode. When the main-power switch is turned off, the recording apparatus 100 is in the termination mode.

[0030] Next, the operation of the video-signal processing circuit 105 is described with reference to FIG. 2.

[0031] First, the operation of the video-signal processing circuit 105 when the recording apparatus 100 is in the recording mode is as follows:

[0032] In the recording mode, a luminance signal, an R-Y chrominance signal, and a B-Y chrominance signal are input from terminals 201, 203, and 205, respectively. One signal is selected from among the input signals and is stored in the memory 107. A block forming circuit 209 reads the stored video signals in units of blocks, each of which is composed of eight vertical pixels by eight horizontal pixels, from the memory 107 in an order adapted for post-processing, and outputs the read signals to an orthogonal transformation circuit 211. The orthogonal transformation circuit 211 performs discrete cosine transform (DCT) of the read signals in the block units, and outputs the processed signals to a quantizer circuit 213. The quantizer circuit 213 uses predetermined quantization coefficients to perform the quantization of orthogonal transformation coefficients output from the orthogonal transformation circuit 211, and outputs the processed signals to a variable-length encoding circuit 215. The variable-length encoding circuit 215 performs well-known variable-length encoding of the signals output from the quantizer circuit 213, such as Huffman encoding, and stores the encoded signals in the memory 107. Based on these processes, DCT, quantization, and variable-length encoding, the information of the video signals is compressed.

[0033] An error-correction encoding circuit 217 performs error-correction encoding by adding parity data to the compressed, encoded video signals stored in the memory 107, and stores the error-correction-encoded video signals in the memory 107. A recording processing circuit 219 forms a plurality of synchronization blocks by adding synchronization signals and identification (ID) signals to the error-correction-encoded video signals stored in the memory 107, and outputs the synchronization blocks as recording data to the recording circuit 109 via an terminal

[0034] The operation of the video-signal processing circuit 105 when the recording apparatus 100 is in the reproducing mode is as follows:

[0035] The reproduced signals output from the recording circuit 109 are output to a reproducing circuit 225 via a terminal 223. The reproducing circuit 225 detects the synchronization and ID signals included in the reproduced signals, and stores the reproduced signals in the memory 107. An error-correcting circuit 227 reads the reproduced signals in the memory 107, and performs error correction of the read signals before storing the error-corrected signals in the memory 107. A variable-length decoding circuit 229 processes the video signals stored in the memory 107 so that variable length codes are decoded, and outputs the processed signals to an inverse quantization circuit 231. The inverse quantization circuit 231 performs inverse quantization based on the quantization coefficients used in the recording mode, and outputs the inversely transformed signals to an inversely orthogonal transformation circuit 233. The inversely orthogonal transformation circuit 233 converts the inversely quantized signals into the original video signals by performing inverse DCT, and stores the original video signals in the memory 107. By using the variable-length decoding circuit 229, the inverse quantization circuit 231, and the inversely orthogonal transformation circuit 233, the information of the reproduced data is increased.

[0036] A synchronization-signal adding circuit 237 adds horizontal and vertical synchronizing signals to the information-increased video signals stored in the memory 107, and outputs the obtained signals to a digital-to-analog converter (D/A) 239. The D/A 239 converts the video signals into analog video signals, and outputs them to an output terminal 119.

[0037] A digital interface 235, which is based on the IEEE 1394 standard, outputs the compressed, encoded video signals from the memory 107 to the exterior, and stores, in the memory 107, compressed, encoded video signals that are externally input.

[0038] Specifically, in the recording mode, the video signals output from the variable-length encoding circuit 215 are converted to have a predetermined format before being output, and the externally input video signals are stored in the memory 107 in accordance with a predetermined format. In the recording mode, by using the error-correction encoding circuit 217 and the recording processing circuit 219 to perform the above-described processes of the video signals input via the digital interface 235, and outputting the processed signals to the recording circuit 109, the input signals can be recorded.

[0039] In the reproducing mode, the digital interface 235 can read and output, to the exterior in a predetermined format, the video signals stored in the memory 107, whose errors were corrected by the error-correcting circuit 227.

[0040] FIGS. 3A and 3B show the structure of the memory 107 in this embodiment.

[0041] As shown in FIG. 3A, the memory 107 consists of an area 107ain which the decompressed video signals are stored, and an area 107bin which the compressed video signals are stored. The decompressed video signals for two frames are stored in the area 107a, while the compressed video signals for 30 frames are stored in the area 107b. The area 107aincludes sub-areas having frame numbers 0 and 1. The area 107bincludes sub-areas having frame numbers 0 to 29. For each sub-area of the area 107a, the storing and reading of the video signals is alternately performed frame by frame.

[0042] In this embodiment, video-signal compression is performed in accordance with the SD format proposed in the HD Digital VCR Conference. The compressed video signals for one frame have a length of 190080 bytes. Accordingly, as shown in FIG. 3B, the storage capacity of each frame of the area 107bis set at 190080 bytes.

[0043] Bit assignment for accessing the area 107bis set up such that a total of 24 bits expresses the addresses of the area 107bby using 5 bits for a frame address, and using 18 bits for an address (hereinafter referred to as a “symbol address”) representing the number of bytes in each frame, as shown in FIG. 4.

[0044] In this embodiment, in the recording pause mode, the video signals processed by performing compression and encoding, and error-correction encoding, are stored in the memory 107, and processing subsequent to the processing by the recording processing circuit 219 is not performed. In other words, in the recording pause mode, the compressed, encoded video signals are repeatedly written into the memory 107.

[0045] FIG. 5 shows the concept of the storing of the video signals to the memory 107 in the recording pause mode.

[0046] In FIG. 5, reference numerals 0 to 29 represent frame numbers. The system control circuit 115 controls the addresses of the memory 107 in the recording pause mode so that the compressed, encoded video signals are sequentially stored from the start address of frame 0, and when the storing of the video signals at the end address of frame 29 is completed, the video signals are stored at the start address of frame 0 again.

[0047] A process performed when the mode of the recording apparatus 100 has changed from the recording pause mode, in which the compressed, encoded video signals are repeatedly written into the memory 107, to the recording mode is described below.

[0048] In FIG. 5, when the system control circuit 115 receives a recording-start instruction from the operation unit 117 while the video signals are being stored at address A of frame 1 in the memory 107, the system control circuit 115 outputs a control signal representing reception of the instruction to the recording processing circuit 219 (shown in FIG. 2). The recording processing circuit 219 sets, as an address for reading, the start address (address B shown in FIG. 5) of a frame subsequent to a frame in which writing is being performed. Subsequently, the recording processing circuit 219 cycles through selecting addresses for reading, and sequentially reads the video signal from the memory 107.

[0049] The above-described sequential processes (such as the addition of ID and synchronization signals, and modulation) of the video signals read from the memory 107 are performed, and the processed signals are output to the recording circuit 109. Even after transfer to the recording mode, the storing of the video signals to the memory 107 is continuously performed, that is, the storing of the video signals to the memory 107 is continuously performed by cycling through selecting storage addresses, from an address subsequent to address A. As described above, in the recording mode, by cycling through selecting the storage addresses and the read addresses, the storing of the video signals to the memory 107, and the reading of the video signals from the memory 107 are repeatedly performed.

[0050] With reference to FIG. 5, a process performed when the mode of the recording apparatus 100 has changed from the recording mode to the recording pause mode is described below.

[0051] In FIG. 5, in the case where the system control circuit 115 receives a recording-stop instruction when reading the video signals at address D of the frame 3 in the memory 107, the system control circuit 115 outputs a control signal representing reception of the instruction to the recording processing circuit 219 (shown in FIG. 2). When the recording processing circuit 219 receives the recording-stop instruction, it reads the video signals stored in the memory 107 from the address corresponding to the recording-start instruction to end address C of the frame 2 prior to frame 3 in which the read video signals is stored. Subsequently, the recording processing circuit 219 stops the reading of the video signals from the memory 107.

[0052] At this time, the recording processing circuit 219 reads and records data to the end of frame 3 at a normal speed, and reads data at double the normal speed from the start address of frame 4 to the end address C of frame 2. The recording processing circuit 219 simultaneously controls the recording circuit 109 to perform recording by rotating the disk 113 at double a normal speed used in the recording mode. In addition, even after transfer to the recording pause mode, the storing of the video signals to the memory 107 is continuously performed.

[0053] In this embodiment, after the recording-stop instruction is received, the video signals for 30 frames, already stored in the memory 107, are recorded before the recording is terminated to activate the recording pause mode.

[0054] The operation of the recording processing circuit 219 is described below with reference to FIGS. 6 and 7.

[0055] FIG. 6 is a block diagram showing the recording processing circuit 219 (shown in FIG. 2), and FIG. 7 is a timing chart showing signals in the recording processing circuit 219.

[0056] In FIG. 6, a clock signal is input from a reference clock signal generator (not shown) to a terminal 601, and the clock signal is output from the terminal 601 to a multiplier 603 and a switch 605. The multiplier 603 doubles the frequency of the clock signal from the terminal 601, and outputs it to the switch 605. The switch 605 is changed over in accordance with a speed control signal output from a frame-number latch circuit 609, as described below, whereby the clock signal from the terminal 601 or the clock signal from the multiplier 603 is selectively output as a system clock signal in synchronization with a frame cycle. In this embodiment, the switch 605 selects and outputs the clock signal from the terminal 601, which is a normal clock signal, when the speed control signal is logically high, while the switch 605 selects and outputs the clock signal from the multiplier 603 when the speed control signal is logically low. In accordance with the system clock signal, the video-signal processing circuit 105 and the recording circuit 109 operate.

[0057] A control signal (hereinafter referred to as a “REC_Status signal”) S701 representing the recording mode, output from the system control circuit 115 (shown in FIG. 1), is input to a terminal 615. The REC_Status signal S701 is logically low in the recording mode, and is logically high in another mode. The waveform of the REC_Status signal S701 is denoted by reference mark a in FIG. 7.

[0058] The REC_Status signal S701 is output to an AND circuit 611, a delay circuit 617, AND circuits 619 and 621, and a REC_ON generating circuit 627. The delay circuit 617 delays the REC_Status signal S701 for one clock pulse, and outputs it to the AND circuit 619. The AND circuit 619 detects a rise of the REC_Status signal S701, and outputs a detection signal as a REC_Start signal S703 to the REC_ON generating circuit 627, and counters 635 and 637. The REC_Start signal S703 is denoted by reference mark b in FIG. 7.

[0059] The output of the delay circuit 617 is input to the AND circuit 621. The AND circuit 621 detects a rise of the REC_Status signal S701 by performing the logical multiplication of the REC_Status signal S701 and the output of the delay circuit 617, and outputs a detection signal as a REC_Stop signal S705 representing termination of recording, to the latch circuit 623. The REC_Stop signal S705 is denoted by reference mark c in FIG. 7.

[0060] A signal representing a writing-frame number is supplied from a terminal 631 to the latch circuit 623. The latch circuit 623 performs the latching of the writing-frame number in synchronization with the REC_Stop signal S705 from the AND circuit 621, and outputs it to a REC_Stop Address generating circuit 625. The output of the REC_Stop_Address generating circuit 625 represents an address at which reading from the memory 107 must be stopped. This address in this embodiment as shown in FIG. 5 is MSB 0001101110011001111111. This process is denoted by reference mark d in FIG. 7.

[0061] A value obtained by using an adder 633 to add 1 to the writing-frame number from the terminal 631 is input to the counter 635. The counter 635 performs the latching of the frame number in synchronization with the REC_Start signal S703 from the AND circuit 619. The counter 637 is cleared in accordance with the REC_Start signal S703. The counter 637 performs counting in accordance with a 1-byte (symbol) clock signal, and outputs the result as a symbol-number address to the memory interface 639. When the counter 637 counts to a value (190079 in this embodiment) corresponding to the video signals for one frame, the counter 637 outputs 5 a carry to the counter 635 and is self-reset. The counter 635 counts the number of carries from the counter 637, and outputs the number as a frame-number address to the memory interface 639.

[0062] The memory interface 639 uses the obtained address data from the counters 635 and 637 to output a read address to a terminal 645 and the REC_ON generating circuit 627.

[0063] As described above, the REC_ON generating circuit 627 is supplied with the REC_Start signal S703, the REC_Stop address, and the REC_Status signal S701. After receiving a recording instruction by the REC_Start signal S703, the REC_ON generation circuit 627 outputs a REC_ON signal S707 as a recording permission signal until the read address coincides with the REC_Stop address. The REC_ON signal S707 represents recording when it is logically low, and represents recording termination of recording when it is logically high. The REC_Start signal S707 is denoted by reference mark g in FIG. 7. The REC_ON generating circuit 627 internally generates the signals denoted by reference marks e and f shown in FIG. 7. An address coincidence signal denoted by reference mark e shown in FIG. 7 is output when the recording-stop address coincides with the read address and the REC_Status signal S701 is logically high. A REC_ON_TEMP signal as a temporary recording-permission signal that is logically low in synchronization with the REC_Start signal S703 and that is logically high in accordance with the address coincidence signal is denoted by reference mark f shown in FIG. 7. In this embodiment, the REC_ON signal S707 is obtained by delaying the REC_ON_TEMP signal for a predetermined time in connection with a time required for the addition of synchronization and ID signals, and digital modulation.

[0064] When the memory interface 639 is supplied with the read address from the counter 635 or 637, it outputs a data request signal to the memory 107 via the terminal 647, and outputs, to a synchronization-ID adding circuit 641, a signal representing the outputting of the data request signal. The synchronization-ID adding circuit 641 adds the synchronization and ID signals to the output data (read from the memory 107) input from the terminal 649, and outputs the obtained signal to a modulator circuit 643. The modulator 643 performs predetermined digital modulation of the output data from the synchronization-ID adding circuit 641, and outputs the modulated data to the recording circuit 109 via a terminal 651. The output data is denoted by reference mark i shown in FIG. 7. Obviously, the output data synchronizes with the REC_ON signal S707.

[0065] The REC_ON signal S707 is also output to the AND circuit 611. The output of the AND circuit 611 is logically low when the REC_ON signal S707 is logically low, and the REC_Status signal S701 is logically high. The latch circuit 609 performs the latching of the output of the AND circuit 611 when the output of the AND circuit 611 synchronizes with a frame pulse V from the terminal 607. A signal from the latch circuit 609 is output as a speed signal S709 to the recording circuit 109 via the terminal 613. Accordingly, the speed signal S709 from the latch circuit 609 becomes logically low until the REC_ON signal S707 is logically high (i.e., completion of the reading of data up to the recording-stop address of the memory 107) after the REC_Start signal S703 was logically high (i.e., the recording pause mode was instructed). In this period, the recording circuit 109 performs recording at double the normal speed. The recording circuit 109 records video signals stored in the recording-stop address before switching the rotation speed of the disk 113 to the normal speed. The speed signal is denoted by reference mark h shown in FIG. 7.

[0066] As described above, in this embodiment, also in the recording pause mode, the video signals are repeatedly stored in the memory 107 by cycling through selecting storage addresses of the memory 107, and the recording of the video signals stored in a frame subsequent to a frame from which storing is being performed at the time of an instruction to activate recording. This prevents a user from failing to record images obtained when the user activates recording. By terminating recording after reading the video signals for 30 frames already stored in the memory 107 up to a frame prior to the frame corresponding to the time of an instruction to terminate recording, information that includes video signals representing an image at the time of recording stop by the user can be securely recorded on the disk 113. Moreover, it is possible to quickly prepare the recording apparatus 100 for the next operation of recording because after the user terminates recording, the video signals already stored in the memory 107 are recorded at a speed greater than the normal speed.

[0067] In this embodiment, the video signals for 30 frames are stored in the memory 107. However, the present invention is not limited to this embodiment, but more video signals may be stored, or a memory having a capacity for at least n frames (where n represents an integer not less than 2) may be used.

[0068] Although the speed of the high-speed processing controlled by a speed signal is double that of the normal processing, recording may be performed at a greater speed.

[0069] Recently, types of large-capacity semiconductor memory are available at a low cost, and these types of large-capacity semiconductor memory can be used as a recording medium in place of the disk 113 in the above-described embodiment.

[0070] Also, a conventional magnetic tape can be used as a recording medium in place of the disk 113.

[0071] The individual components shown in outline or designated by blocks in the drawings are well-known in the image recording arts, and their specific construction and operation are not critical to the operation or best mode for carrying out the invention.

[0072] While the present invention has been described with respect to what is presently considered to be the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the independent claims. The scope of the following claims is to be accorded the broadest interpretation so as to compass all such modifications and equivalent structures and functions.