Coding sublayer for multi-channel media with error correction

[0002] This application claims the benefit under 35 U.S.C. §119(e) of provisional patent application no. 60/180,665, filed Feb. 7, 2000 and entitled CODING SUBLAYER FOR MULTI-CHANNEL MEDIA WITH ERROR CORRECTION.

[0003] Not Applicable

[0004] The present invention relates generally to data encoding and more specifically, to physical coding and decoding techniques for segregating and reliably communicating data over a plurality of serial channels.

[0005] In recent years there has been an increasing desire to produce electronic products which operate at ever increasing speeds. Of particular note in this regard are telecommunications devices such as routers, bridges and switches. While typical communication line rates for such devices were 10 megabits per second (mbps) for Ethernet transmissions less than a decade ago, 100 mbps Ethernet line rates have now become commonplace. Moreover, devices are currently being deployed which support ten gigabit per second (gbps) Ethernet line rates.

[0006] Data is typically received at an input port of a telecommunications device over a high speed serial communications link. Received data is converted to a parallel word format in accordance with a specified media access control (MAC) protocol for processing within the device. The width of the parallel data output from the MAC protocol is typically specified for the respective MAC protocol. A 10 gigabit per second Ethernet protocol has been described having a MAC output using a 64 bit wide data word. At such high data rates, the transport of data within the device can be problematic.

[0007] While data can be transported through the device as a parallel word to achieve workable clock rates, such is undesirable for a number of reasons. First, wide bus widths consume substantial space on the printed circuit boards for the numerous conductive paths which are required. Second, passing large numbers of conductive signals through backplanes requires large numbers of connector contacts as well as drivers and receivers. Often, it is undesirable to provide for the large number of connector contacts that are required to accommodate a 64 bit wide or greater width parallel bus. Additionally, it is recognized that interconnections through backplane connectors contribute to system unreliability and for this reason as well it is preferable to minimize the number of signal paths through backplanes and connectors. Finally, numerous integrated circuits are required in terms of drivers and receivers to interface to wide parallel buses.

[0008] In order to minimize the number of printed circuit board runs and backplane connections, parallel data has been segregated into narrower parallel data words and the respective words have been serialized for transmission over a plurality of serial channels. This technique can result in the introduction of near end and far end crosstalk in adjacent channels that can introduce data errors in the transmission. Furthermore, complex techniques and/or substantial overhead in terms of signal bandwidth and circuitry have typically been necessary to accomplish synchronization and/or framing in such systems.

[0009] Moreover, it is desirable to be able for the receive logic to be able to be acquire synchronization of serially transmitted data “blind”; i.e. without the use of additional synchronization signal lines since the transport of separate synchronization signals also adds to the number of printed circuit board runs and connector contacts that are needed.

[0010] It would therefore be desirable to have a data coding, decoding and transport technique which allows the transmission of data reliably through a telecommunications device without employing wide parallel buses and which permits blind acquisition of synchronization at the receiver and reassembly of the transmitted data words.

[0011] In accordance with the present invention, a method and apparatus for transporting data reliably over a plurality of serial channels is disclosed. Physical coding sublayer logic receives a parallel data word from a system interface. The parallel data word includes data of a first data channel and a monitor channel. The monitor channel is employed to convey supervisory or other information in a second data channel that is independent of the data conveyed in the first data channel. A monitor channel and the parallel data data word are applied to an error correction code generator and a error correction code (ECC) is generated. The parallel data word is divided into a plurality of lesser width data words. Selected bits of the ECC code and the monitor channel are appended to the lesser width parallel data words in a predetermined manner to form a plurality of extended lesser width parallel data words corresponding in number to the number of lesser width parallel data words. The extended lesser width parallel data words are serialized in respective serializers and transmitted over a plurality of serial data links.

[0012] Each serial channel also includes two parity bits. The first parity bit is employed for error detection and correction and additionally carries control state information. The parity bits are generated such that proper parity is indicated if the XOR sum of all bits within a channel (including the first and second parity bits) equals 1. This property is used to obtain proper word framing at receive logic within the physical coding sublayer. The second parity bit in each channel is generated such that the XOR sum of all of the second parity bits equals 0 when the channels are properly aligned. Proper word framing and alignment is verified by testing framing and alignment over a predetermined number of word samples.

[0013] The invention will be more fully understood by reference to the following Detailed Description of the Invention in conjunction with the Drawing of which:

[0014] FIG. 1 is a block diagram illustrating physical coding sublayer logic within a system operative in accordance with the present invention;

[0015] FIG. 2 is a diagram illustrating interfaces for the Physical Coding Sublayer logic and the serializer-deserializer logic depicted in FIG. 1;

[0016] FIG. 3 is a block diagram illustrating transmit logic employed in the physical coding sublayer logic depicted in FIGS. 1 and 2;

[0017] FIG. 4 is a diagram illustrating data ordering for data transmitted from the physical coding sublayer logic over respective serial channels;

[0018] FIG. 5 is a block diagram of a side scrambler for scrambling data in each channel of the transmit portion of the physical coding sublayer logic;

[0019] FIG. 6 is a block diagram depicting parity and control error correction code (ECC) encoder logic employed in the transmit portion of the physical coding sublayer logic;

[0020] FIG. 7 is a block diagram of receive logic employed within the physical coding sublayer logic;

[0021] FIG. 8 is a block diagram of word framer logic employed in the receive portion of the physical coding sublayer logic;

[0022] FIG. 9 is a block diagram illustrating inter-channel alignment logic employed within the receive portion of the physical coding sublayer logic;

[0023] FIG. 10 is a block diagram illustrating control error correction code (ECC) decoder logic employed in the receive portion of the physical coding sublayer logic;

[0024] FIGS. 11aand 11bare a flow diagram illustrating error correction code (ECC) decoder operation;

[0025] FIGS. 12 is a block diagram illustrating descrambler logic within the receive portion of the physical coding sublayer logic;

[0026] FIG. 13 is a block diagram illustrating the data error correction code (ECC) decoder logic employed within the receive portion of the physical coding sublayer logic; and

[0027] FIGS. 14aand 14bare a flow diagram depicting an exemplary method of operation of the data ECC decoder within the receive portion of the physical coding sublayer logic.

[0028] Provisional patent application no. 60/180,665, filed Feb. 7, 2000 and entitled CODING SUBLAYER FOR MULTI-CHANNEL MEDIA WITH ERROR CORRECTION is hereby incorporated by reference.

[0029] In accordance with the present invention a system is disclosed, along with a physical coding sublayer employed within the system, for communication of data presented in parallel form across multiple serial channels in short haul copper links (such as backplanes and short cable connections), parallel fiber optic links, and wave division multiplexing (WDM) applications (employing fiber optic media). An exemplary system incorporating the presently disclosed physical coding sublayer is illustrated in FIG. 1. Referring to FIG. 1, the system includes an optional system interface 10 that may include a media access control (MAC) interface 11, reconciliation logic 12, physical coding sublayer logic 14, serializers/deserializers 16 and a physical medium interface 18. The system provides for bidirectional signal transmission and includes a transmit path in which data moves from the system interface downward through the various blocks as depicted in FIG. 1 for transmission over a plurality of serial data channels (denoted as Channels A-D). The system also includes a receive path in which data moves from the serial data channels A-D upward as depicted in FIG. 1 through the respective logical blocks. In the illustrated embodiment, along the transmit path information received over a system bus 20 is converted to media access format within the system interface 10 by the Media Access Control logic MAC 11 in accordance with a known MAC protocol such as the ten gigabit Ethernet protocol. The media access control logic is coupled to the reconciliation logic 12. The reconciliation logic 12 converts the MAC output to a form that generally comports with the well known XGMII interface 24. The media access interface may be the same as the XGMII interface in which case the reconciliation logic 12 may be omitted. The XGMII interface is coupled to the physical coding sublayer logic 14. A monitor bit from a monitor channel 26 is also coupled to the physical coding sublayer logic 14. The information conveyed in the monitor channel is independent of the primary data channel. In the illustrative embodiment, the monitor channel is a 156.25 MB/s full duplex channel and can be employed for the transmission of any control information, management information or data. The physical coding sublayer logic 14 is operative to (a) receive the monitor channel bit from the monitor channel 26, (b) generate an error correction code as a function of parallel data received over the XGMII interface 24 and the monitor channel 26 bit, (c) subdivide the received parallel data word, the monitor channel bit and an ECC code generated based upon the monitor bit and the parallel data word into a plurality of lesser width parallel data words, (d) scramble the bits within each of the plurality of lesser width parallel data words using a side-stream scrambler to form cipher data words that are decorrelated in time, (e) generate a control error correction code (CECC) bit that is appended to each of the cipher data words and (f) generate a parity code that is associated with each of the cipher data words and employed in the process of interchannel alignment. The parity bit and the CECC bit together with the scrambled data form an extended width cipher data word. The extended width cipher data words are coupled to serializers within the serializers/deserializers 16 via a serializer/deserializer (SERDES) interface 28. The serializers convert the extended width cipher data words from parallel to serial form. The serialized extended width cipher data words are coupled to the physical medium interface 18 over respective serial links 30. The physical medium interface drives the respective channels in accordance with the required drive characteristics. More specifically, the physical medium interface 18 provides the appropriate electrical or electro-optical interface to copper or fiber serial data links 32, as applicable. By subdividing the wide parallel data word into a plurality of narrower parallel data words, encoding the narrower parallel data words and transmitting data contained in the plurality of narrower encoded parallel data words serially over a corresponding plurality data of serial channels, the number of printed circuit board runs or fiber transmission channels are significantly reduced and an extremely low bit error rate can be achieved. In the case of copper printed circuit board runs, significant space savings on the printed circuit board may be achieved as fewer printed circuit board runs and fewer connector contacts are necessary.

[0030] Along the receive path, data moves in the reverse direction from the transmit path. In particular, serialized extended width cipher data words received on serial data channels A-D at the physical medium interface 18 are converted to the logic levels employed by the deserializers 16. The deserializers 16 convert the respective serial extended width cipher data words into parallel extended width cipher data words and the parallel extended width cipher data words are coupled to the physical coding sublayer logic 14 over the SERDES interface 28. The physical coding sublayer logic 14 decodes the cipher data words to recreate the original parallel data word at the XGMII interface 24. The parallel data words are presented to the reconciliation logic 12, which, in the disclosed embodiment, converts the signalling from that employed on the XGMII interface 24 to the internal signalling format employed by the MAC. The system interface 20 supplies data to the system across the system bus. Bus ordering reflects IEEE 802.3 conventions used on the XGMII bus. Within a channel, bit 0 is transmitted on the wire first which is conventional for 1000B-X and Fibre Channel implementations.

[0031] On the physical coding sublayer side of the reconciliation logic 12, the reconciliation logic 12 interface generally conforms to the XGMII interface 24. In particular, for the transmit path, the XGMII interface 24 (See FIGS. 1 and 2) includes a parallel data bus TXX_D<63:0>, a control bus TXX_C<7:0> and a clock TXX_CLK. Along the receive path the XGMII interface includes a parallel data bus RXX_D<63:0>, a control bus RXX_C<7:0> and a receive clock RXX_CLK. The signalling on the XGMII bus 24 is conventional. A 64-bit implementation of the XGMII is used although the bus signaling definition is independent of width.

[0032] Normal Ethernet packets are transmitted over the XGMII bus. The Ethernet packets may start and stop on any byte boundary and require delimiters, along with a series of control characters used to signal the bus state, such as idle or error. All bus states are transmitted on a per-byte basis and are encoded using the control bit and data byte for that specific byte.

[0033] Listed below are the byte states used on the XGMII bus.

[0034] Data Valid (DV):

[0035] Used to indicate a valid byte within an Ethernet packet.

[0036] Idle (I):

[0037] Used to signal the byte is idle during normal inter-packet gap.

[0038] Start of Packet-SOP (S):

[0039] Used to signal the beginning of each packet by replacing the first byte of preamble in an Ethernet packet.

[0040] End of Packet-EOP (T):

[0041] Used to signal the end of each packet by asserting for one byte immediately after the last byte of an Ethernet packet.

[0042] ERROR (E)

[0043] Used to signal when an error needs to be forced on the TX bus or when an error is detected by the receive PCS.

[0044] These XGMII byte states have the specific bit encoding shown below in Table 1.

[0045] The XGMII bus contains 64 data bits (D63 . . . D0) in each direction which are divided into eight groups, each of eight bits, or a byte. Each of the bytes are accompanied by a control bit (C7 . . . C0). All the bits are clocked with a source-synchronous clock labeled TXR_CLK. The control bits C7 . . . C0 received as TXR_C<7:0> collectively make up the TXX_C<7:0> bus.

[0046] The interface to the physical coding sublayer logic 14 and the interfaces for the Serializers/Deserializers 16 are depicted in FIG. 2. On the reconciliation logic 12 side of the physical coding sublayer logic 14, the interface comprises the XGMII interface. The SERDES interface 28 includes signals in the transmit path and signals in the receive path. In the transmit path, the SERDES interface 28 includes a parallel data bus TXCED<9:0> and a transmit clock TXCE_CLK for each of the respective channels. The data buses in the SERDES interface 28 for the respective channels in the transmit path are identified as TXCEDa<9:0>, TXCEDb<9:0>, TXCEDc<9:0> and TXCEDd<9:0> for channels A, B, C and D respectively. Transmit clocks TXCEa_CLK, TXCEb_CLK, TXCEc_CLK and TXCEd_CLK are provided for each of the respective channels.

[0047] In the receive path, the SERDES interface includes a parallel data bus RXCED<9:0> and a differential receive clock comprising signals RXCE_CLK+/− for data received over each of the channels A-D. The data buses in the SERDES interface in the receive path are identified as RXCEDa<9:0>, RXCEDb<9:0>, RXCEDc<9:0> and RXCEDd<9:0> for channels A, B, C and D respectively. Differential clocks signals RXCEa_CLK+/−, RXCEb_CLK+/−, RXCEc_CLK+/− and RXCEd_CLK+/− are provided for each channel in the receive path.

[0048] The serializers/deserializers 16 include a serializer/deserializer for each channel and are identified as SERDES A 16a,SERDES B 16b,SERDES C 16c,and SERDES D 16drespectively. Each SERDES 16athrough 16dis coupled to transmit and receive channels as depicted in FIG. 2. In the disclosed embodiment, the serial data transmitted between the SERDES logic 16 and the Physical Medium Interface 18 is communicated in differential form. Accordingly, differential drivers and receivers are employed within the SERDES logic between the SERDES logic 16 and the Physical Medium Interface 18. For example, SERDES A 16adrives differential signals TXSOa+/− along the transmit path and receives differential signals RXSOa+/− along the receive path. The physical coding sublayer 14 and the Serializers/Deserializers 16 also receive a system clock or reference clock as illustrated in FIG. 2. The system clock is used by the Serializer as a low jitter reference clock and by the Deserializer to check the frequency of the received serial data.

[0049] Exemplary transmit path logic within the physical coding sublayer logic 14 is depicted in FIG. 3. The use of the presently disclosed physical coding sublayer logic 14 is particularly beneficial in environments where crosstalk and random noise events are present. Redundancy and a high coding strength are built into the coding to provide extremely low bit error rates. Single bit error correction in both the data and control portions of the code are provided.

[0050] Transmit Path Operation

[0051] The transmit path logic within the physical coding sublayer logic 14 comprises several logical functions that collectively provide the desired performance while maintaining a pipelined design required for high-speed transmission and low power. More specifically, the transmit path logic within the physical coding sublayer logic 14 includes an XGMII controller 50, a data error correction code generator 52, an interleave function 53, transmit side-scrambler logic 54, and a Parity and Control ECC encoder 56. All these functions are built into a 4×20-bit cell that carries 64 bits of data and framing compatible with Ethernet and cell applications. The 80-bit cell format comprising four 20 bit channels that are output from the physical coding sublayer logic 14 is illustrated in FIG. 4.

[0052] XRMTT Transmit Controller

[0053] The transmit control block 50 is used to encode XGMII transmit state information into a more compressed format used within the physical coding sublayer logic 14 transfers. A four-state (two bit) control path C<1:0> is defined along with additional fields in the data payload to transfer the XGMII control state information on 64-bit boundaries. This control coding limits the Inter Packet Gap (IPG) to 8 bytes minimum. The XGMII Transmit Controller also generates Transmit Error (TX_ER) in response to XGMII Errors which are then signalled across the link and appear as receive errors at the receive PCS. Transmit Error coding is not required per byte (as defined by XGMII) and needs only to be transmitted on a per-frame basis. Transmit Error (TX_ER) is defined as any XGMII Error (E) which occurs within a packet.

[0054] The XGMII control state is received on the XGMII bus TXX_C<7:0> is translated into 4 basic control states.

[0055] The control state is encoded within the XGMII transmit Controller 50 into the two bits, C<1:0>, using the mapping in Table 2.

[0056] C<1:0> and TX_ER define primary control states for the data nsfers as shown in Table 3.

[0057] Further encoding of valid data bytes is contained within the data bus itself during the Data Valid High and Data Valid Low states. These are shown in Tables 4 and 5.

[0058] Transmit Error (TX_ER) is encoded by the XGMII Transmit Controller as follows.

[0059] If the current control state is Idle then no action is taken because the error is not within a packet.

[0060] If the current control state is Data Valid Low the control state is sent with the TXD[3] bit set in the reserved control space.

[0061] If the current control state is Data Valid High the control state is sent with the TXD[59] bit set in the reserved control space.

[0062] If the current control state is Data Valid All the control state is changed to Data Valid High with the TXD[59] bit set in the reserved control space.

[0063] Data ECC Encoder

[0064] The Data ECC generator 52 generates seven redundant bits, E<6:0>, from the 65-bit data payload comprising the data carried on TXD<63:0> received from the XGMII Transmit Control Logic 50 and the monitor channel bit of the monitor channel 26. The seven ECC bits are generated using a CRC algorithm that provides single bit error correction, double bit error detection and six bit burst error detection. Additional error detection capabilities are realized when the CRC detection is combined with the parity protection added later. This is equivalent to most commonly used 8-bit cyclic redundancy checkers that have (1+x) as a factor in the polynomial.

[0065] The message polynomial, M(x), is generated from the data and monitor transmit payload, TXD<63:0> and the monitor bit M, using the convention that the highest polynomial term is the first bit on the wire, IE bit 0.

[0066] M(x)=TXD0x⁶⁴+TXD1x⁶³+ . . . +TXD62x²+TXD63x+M

[0067] The message polynomial is then divided by the generating polynomial, G(x), to produce the quotient, Q(x), and the remainder, E(x). $\frac{x^{7}M\left(x\right)}{G\left(x\right)}=Q\left(x\right)+\frac{E\left(x\right)}{G\left(x\right)}$

[0068] Where E(x) has the form

[0069] E(x)=E0x⁶+E1x⁵+ . . . +E5x+E6

[0070] The transmit message is then the concatenation of the message, M(x), and the remainder, E(x).

[0071] TX(x)=M(x)+E(x)

[0072] This 72 bit payload is then inserted in the physical coding sublayer cell format depicted in FIG. 4 and has the property that it is divisible by G(x) in the absence of errors.

[0073] The generating polynomial, G(x), in the preferred embodiment, was chosen to minimize the number of gates in the implementation.

[0074] G(x)=x⁷+x+1

[0075] Shown below are the reduced XOR logical equations that constitute the CRC function within the data ECC generator 52 for the exemplary embodiment herein disclosed.

[0076] E0=TXD2+TXD5+TXD9 +

[0077] TXD10+TXD11+TXD16+TXD18 +

[0078] TXD19+TXD20+TXD21+TXD22 +

[0079] TXD25+TXD27+TXD29+TXD30 +

[0080] TXD31+TXD34+TXD35+TXD37 +

[0081] TXD41+TXD44+TXD45+TXD46 +

[0082] TXD47+TXD51+TXD53+TXD58 +

[0083] TXD59;

[0084] E1=TXD0+TXD3+TXD6 +

[0085] TXD10+TXD11+TXD12+TXD17 +

[0086] TXD19+TXD20+TXD21+TXD22 +

[0087] TXD23+TXD26+TXD28+TXD30 +

[0088] TXD31+TXD32+TXD35+TXD36 +

[0089] TXD38+TXD42+TXD45+TXD46 +

[0090] TXD47+TXD48+TXD52+TXD54 +

[0091] TXD59+TXD60;

[0092] E2=TXD0+TXD1+TXD4 +

[0093] TXD7+TXD11+TXD12+TXD13 +

[0094] TXD18 +

[0095] TXD20+TXD21+TXD22+TXD23 +

[0096] TXD24 +

[0097] TXD27+TXD29+

[0098] TXD31+TXD32+TXD33 +

[0099] TXD36+TXD37+TXD39+TXD43 +

[0100] TXD46+TXD47+TXD48+TXD49 +

[0101] TXD53+TXD55+TXD60+TXD61;

[0102] E3=TXD1+TXD2+TXD5 +

[0103] TXD8+TXD12+TXD13+TXD14+TXD19 +

[0104] TXD21+TXD22+TXD23+TXD24 +

[0105] TXD25+TXD28+TXD30 +

[0106] TXD32+TXD33+TXD34 +

[0107] TXD37+TXD38+TXD40 +

[0108] TXD44+TXD47+TXD48 +

[0109] TXD49+TXD50+TXD54 +

[0110] TXD56+TXD61+TXD62;

[0111] E4=TXD0+TXD2+TXD3 +

[0112] TXD6+TXD9+TXD13+TXD14 +

[0113] TXD15+TXD20+TXD22+TXD23 +

[0114] TXD24+TXD25+TXD26+TXD29 +

[0115] TXD31+TXD33+TXD34+TXD35 +

[0116] TXD38+TXD39+TXD41+TXD45 +

[0117] TXD48+TXD49+TXD50+TXD51 +

[0118] TXD55+TXD57+TXD62+TXD63;

[0119] E5=TXD0+TXD1+TXD3 +

[0120] TXD4+TXD7+TXD10+TXD14 +

[0121] TXD15+TXD16+TXD21+TXD23 +

[0122] TXD24+TXD25+TXD26+TXD27 +

[0123] TXD30+TXD32+TXD34+TXD35 +

[0124] TXD36+TXD39+TXD40+TXD42 +

[0125] TXD46+TXD49+TXD50+TXD51 +

[0126] TXD52+TXD56+TXD58+TXD63 +M;

[0127] E6=TXD1+TXD4+TXD8 +

[0128] TXD9+TXD10+TXD15+TXD17 +

[0129] TXD18+TXD19+TXD20+TXD21 +

[0130] TXD24+TXD26+TXD28 +

[0131] TXD29+TXD30+TXD33 +

[0132] TXD34+TXD36+TXD40 +

[0133] TXD43+TXD44+TXD45 +

[0134] TXD46+TXD50+TXD52 +

[0135] TXD57+TXD58+M;

[0136] Transmit Channel Assignments

[0137] The transmit data bus, monitor bit and ECC bits are divided into separate groups which are then scrambled as subsequently described and transmitted over respective channels. In the present embodiment, the 64 data bits comprising the parallel input data word, the monitor bit and the seven (7) ECC bits comprise 72 bits that are split into four 18 bit groups as indicated below. This is the function of the transmit interleaver 53. This interleaver may comprise active logic to drive respective signals or alternatively may simply define the coupling of appropriate outputs TXD<63:0>, E<6:0> and M to the appropriate inputs of the transmit scrambler logic 54 as defined below.

[0138] TXPa<17:0>=<E0, M, TXD15, TXD14, TXD13, TXD12, TXD11, TXD10, TXD9, TXD8, TXD7, TXD6, TXD5, TXD4, TXD3, TXD2, TXD1, TXD0>

[0139] TXPb<17:0>=<E2, E1, TXD31, TXD30, TXD29, TXD28, TXD27, TXD26, TXD25, TXD24, TXD23, TXD22, TXD21, TXD20, TXD19, TXD18, TXD17, TXD16>

[0140] TXPc<17:0>=<E4, E3, TXD47, TXD46, TXD45, TXD44, TXD43, TXD42, TXD41, TXD40, TXD39, TXD38, TXD37, TXD36, TXD35, TXD34, TXD33, TXD32>

[0141] TXPd<17:0>=<E6, E5, TXD63, TXD62, TXD61, TXD60, TXD59, TXD58, TXD57, TXD56, TXD55, TXD54, TXD53, TXD52, TXD51, TXD50, TXD49, TXD48>

[0142] Transmit Scrambler

[0143] The transmit scrambler 54 is used to provide DC balance, insert transitions, spread the signal spectrum across the available bandwidth and produce low EMI. The incoming data is XORed with the scrambler's pseudo random binary sequence (PRBS).

[0144] Each channel has a separate side-stream scrambler 54a,54b,54cand 54d,which is generating the same sequence, but offset in time, so the channels are de-correlated locally in time. A more detailed block diagram depicting an exemplary structure of the side-stream scramblers 54a,54b,54cand 54dis shown in FIG. 5. While only one side-stream scrambler is shown in FIG. 5, all of the scramblers operate in a similar manner. In a preferred embodiment, de-correlation is achieved over +/−2.6 us using a pseudo random binary sequence of length 15, which is sufficient to de-correlate Near End Crosstalk (NEXT) and Far End Crosstalk (FEXT) contributions from other channels. The time offset of the sequences in the respective channels is achieved by loading different seed values in each channel at startup. Separate scramblers are used to keep global interconnect low while providing a scalable structure. Alternatively, a centralized scrambler may be employed.

[0145] Offset scramblers also effectively encode channel skew information into the transmission words that could be used by the receiver to establish inter-channel skew. The cell encoder uses a more direct method of establishing inter-channel alignment so checking this relationship within the receiver is optional.

[0146] In the illustrated embodiment, a pseudo random binary sequence of length 15 (PRBS15) was chosen to allow receiver synchronization within one Idle transmission period. Data in each channel is defined to be constant at 0×00 during an idle transmission. The monitor bit, and, consequently, the error correction bits, E5 and E6 bits, are not guaranteed to have a known state during idle. The first 15 bits within each channel, i.e. TXCx<14:0>, give the state of the scrambler so the 15 bit seed can be recovered completely within each 80-bit idle cell.

[0147] Two PRBS15 sequences are included, primary and secondary. The receiver waveform can be de-correlated from the transmitter NEXT if both ends of the link are using different sequences. Correlation can occur as the near and far end sequences come in phase if both ends of the link are operating asynchronously or if startup at each end of the link is not phased correctly. Selecting which sequence to use is typically not worth the complexity of establishing a startup protocol, however, sequence choice could be done out-of-band within a closed system and add very little complexity to the physical coding sublayer logic.

[0148] Scrambler Implementation

[0149] An exemplary side-stream scrambler implementation is depicted in FIG. 5. Each of the scramblers 54a,54b,54c,54d(See FIG. 3) employs the logic depicted in FIG. 5 in a preferred embodiment. The side stream scramblers includes a three to one MUX 100. The MUX 100 has a control signal 102 that enables the loading of 15 bits of data from a seed register 104. Additionally, the three to one MUX 100 has an output bus that is coupled to a pseudo random binary sequence (PRBS) register 106. The outputs of the PRBS register 106 are coupled to the inputs of primary feedback logic 108 and secondary feedback logic 110. The outputs of the primary and secondary feedback logic are fed back to inputs of the three to one MUX 100. Either the primary or secondary feedback logic outputs are selected as the operative input to the three to one MUX 100 in response to a primary/secondary selection control signal 112. Exclusive OR logic 114 receives as inputs transmit data from bus TXP<17:0> and the PRBS register 106 outputs X<17:0>. The signals on TXP<17:0> and X<17:0> are exclusive ORed by exclusive OR logic 114 to produce cipher data TXCI<17:0> at each of the respective scrambler outputs; e.g. TXCIa<17:0>, TXCIb<17:0>, TXCIc<17:0> and TXCId<17:0>.

[0150] The two generator polynomials used for the primary and secondary PRBS15 sequences are:

[0151] These sequences have known linear feedback shift register (LFSR) implementations. To achieve high speed, the physical coding sublayer 14 employs an 18-bit parallel implementation for the side scramblers, which is obtained by applying 18 levels of recursion to the LFSR equations to produce the bus wide pseudo random binary sequence generator structure illustrated in FIG. 5.

[0152] The feedback equations for the primary sequence are shown below. The bit ordering is such that the pseudo random binary sequence will appear on the serial lines in the same order as would be generated by the linear feedback shift register approach.

[0153] XPnext0=X3+X4;

[0154] XPnext1=X4+X5;

[0155] XPnext2=X5+X6;

[0156] XPnext3=X6+X7;

[0157] XPnext4=X7+X8;

[0158] XPnext5=X8+X9;

[0159] XPnext6=X9+X10;

[0160] XPnext7=X10+X11;

[0161] XPnext8=X11+X12;

[0162] XPnext9=X12+X13;

[0163] XPnext10=X13+X14;

[0164] XPnext11=X0+X1+X14;

[0165] XPnext12=X0+X2;

[0166] XPnext13=X1+X3;

[0167] XPnext14=X2+X4;

[0168] XPnext15=X3+X5;

[0169] XPnext16=X4+X6;

[0170] XPnext17=X5+X7;

[0171] The primary seeds to start a four-channel transmitter up are:

[0172] S_A=0×7FFF(M(0))

[0173] S_B=0×7F00 (M(½))

[0174] S_C=0×70FF(M(¼))

[0175] S_D=0×780F(M(¾))

[0176] Where M(x) denotes the relative starting position in the maximum length sequence.

[0177] Similarly, the feedback equations for the secondary sequence are shown below.

[0178] XSnext0=X3+X7;

[0179] XSnext1=X4+X8;

[0180] XSnext2=X5+X9;

[0181] XSnext3=X6+X10;

[0182] XSnext4=X7+X11;

[0183] XSnext5=X8+X12;

[0184] XSnext6=X9+X13;

[0185] XSnext7=X10+X14;

[0186] XSnext8=X0+X4+X11;

[0187] XSnext9=X1+X5+X12;

[0188] XSnext10=X2+X6+X13;

[0189] XSnext11=X3+X7+X14;

[0190] XSnext12=X0+X8;

[0191] XSnext13=X1+X9;

[0192] XSnext14=X2+X10;

[0193] XSnext15=X3+X11;

[0194] XSnext16=X4+X12;

[0195] XSnext17=X5+X13;

[0196] The secondary seeds to start a four-channel transmitter up are:

[0197] S_A=0×7FFF(M(0))

[0198] S_B=0×00CC(M(½))

[0199] S_C=0×0AAA(M(¼))

[0200] S_D=0×0008 (M(¾))

[0201] Where M(x) denotes the relative starting position in the maximum length sequence.

[0202] The outputs of the respective side scramblers provide scrambled or cipher data that are identified as TXCIa<17:0>, TXCIb<17:0>, TXCIc<17:0> and TXCId<17:0> as indicated above. The side scrambler output buses are coupled to the inputs of a Parity and FEC Control Matrix 56 which is shown in FIG. 3 and depicted with greater particularity in FIG. 6.

[0203] Parity and Control PFC Matrix

[0204] Referring to FIG. 6. The Parity and Control ECC Logic 56 generates two additional bits in each channel. The two bits per channel carry the transmit control state and provide parity for the respective channels. The bits are used to obtain alignment on word boundaries within each channel (word alignment) and additionally to obtain interchannel alignment. These added bits are redundant with a Hamming distance of 4 to allow correction of single bit control errors and detection of two-bit errors. The inputs to the parity and control ECC encoder 56 comprise the control bus c<1:0> and the TXCI bus data from the scramblers 54a-54d.The parity and Control ECC encoder generates extended cipher data words TXCEa<19:0> through TXCEd<19:0> (See FIG. 6) which are applied to double clock logic 57 (See FIG. 3). The double clock logic 57 clocks out the 20 bit per channel TXCE data as two sequential 10 bit words TXCED<9:0> to reduce the number of signal lines that need to be accommodated within the system.

[0205] The first of the two parity bits previously identified as the CECC bit and referred to in the drawing as the RO bit, starts with the definition of a new variable, K<3:0> in a K word generator 120. The K word generator 120 receives as an input the control word C<1:0> from the XGMII Transmit Control Logic 50. The output of the K word generator 120 comprises a four bit wide bus K<3:0> that holds the control state redundantly and has zero DC content. The states themselves have a minimum Hamming distance of 2 and require the additional information from the parity bits R1 discussed below to increase the Hamming distance to 4 and allow correction to be performed. The generation of the K values based upon the C<1:0> inputs is illustrated below in Table 6.

[0206] Intermediate parity checks, R<a:d>, are calculated on the 72-bit TXCI data payload (data+Monitor+data EVC) in parity check logic 122a,122b,122cand 122das follows: $\begin{array}{c}{R}_a=\sum _{k=0}^{17}{\mathrm{TXCI}}_a\left(k\right)\\ R_b=\sum _{k=0}^{17}{\mathrm{TXCI}}_b\left(k\right)\\ R_c=\sum _{k=0}^{17}{\mathrm{TXCI}}_c\left(k\right)\\ R_d=\sum _{k=0}^{17}{\mathrm{TXCI}}_d\left(k\right)\end{array}$

[0207] Thus, Ra indicates the parity of the data contained in TXCIa<17:0>, Rb indicates the parity of the data contained in TXCIb<17:0>, Rc indicates the parity of the data contained in TXCIc<17:0> and Rd indicates the parity of the data contained in TXCId<17:0>. The parity check variables are random if the TXCI payload is random, which will be the case due to the use of side-stream scramblers 54a,54b,54cand 54d.The intermediate parity bits Ra, Rb, Rc and Rd are XORed with the K bits in R0 bit generation logic 124 to scramble the control state and the R0 bits are further rotated across the channels to permit inter-channel skew detection. The resulting R0<a:d> bits are transmitted as the TXCE18<a:d> bits in each channel and are defined as follows.

[0208] TXCE18_a=R0_a=R_d+K0

[0209] TXCE18_b=R0_b=R_a+K1

[0210] TXCE18_c=R0_c=R_b+K2

[0211] TXCE18_d=R0_d=R_c+K3

[0212] Finally, the overall parity across all 19 bits in each channel is calculated in R1 bit generation logic 126 and transmitted in the TXCE19<a:d> slot as illustrated in FIG. 4. These bits are designated as the R1<a:d> bits and calculated as indicated below. $\begin{array}{c}{\mathrm{TXCE19}}_a={\mathrm{R1}}_a=!\sum _{k=0}^{18}{\mathrm{TXC}}_a\left(k\right)=!\left(R_a+{\mathrm{R0}}_a\right)\\ {\mathrm{TXCE19}}_b={\mathrm{R1}}_b=!\sum _{k=0}^{18}{\mathrm{TXC}}_b\left(k\right)=!\left(R_b+{\mathrm{R0}}_a\right)\\ {\mathrm{TXCE19}}_c={\mathrm{R1}}_c=!\sum _{k=0}^{18}{\mathrm{TXC}}_c\left(k\right)=!\left(R_c+{\mathrm{R0}}_c\right)\\ {\mathrm{TXCE19}}_d={\mathrm{R1}}_d=!\sum _{k=0}^{18}{\mathrm{TXC}}_d\left(k\right)=!\left(R_d+{\mathrm{R0}}_d\right)\end{array}$

[0213] The R1<a:d> (TXCE19) bits are used as parity bits to enhance error correction and detection in both the data and control payloads. They also provide correlation information to allow word and channel alignment to be achieved as discussed further below. Inversion of the parity guarantees at least one transition within the 20-bit word. Two worst case words back to back can produce the maximum run length of 38 with a probability of 3.6E-12.

[0214] Within each channel all bits in a word sum to one in the absence of any errors. This characteristic is used to acquire word alignment. $\begin{array}{c}\sum _{k=0}^{19}{\mathrm{TX}}_a\left(k\right)=1\\ \sum _{k=0}^{19}{\mathrm{TX}}_b\left(k\right)=1\\ \sum _{k=0}^{18}{\mathrm{TX}}_c\left(k\right)=1\\ \sum _{k=0}^{18}{\mathrm{TX}}_d\left(k\right)=1\end{array}$

[0215] Additionally, when the channels are correctly aligned all R1 bits within a cell sum to zero in the absence of errors.

[0216] TXCE19_a+TXCE19_b+TXCE19_d+TXCE19_d=0

[0217] R1_a+R1_b+R1_d+R1_d=0

[0218] This is used to achieve channel alignment which is discussed below.

[0219] Receive Path

[0220] The receive path through the physical coding sublayer 14 is depicted in FIG. 7. Referring to FIG. 7, the receive path roughly follows the transmit path in reverse with the added complexity of having to acquire word and inter-channel alignment and perform error correction.

[0221] Channels A, B, C and D include channel receive logic 150 that comprise word framer logic 152 and a word delay FIFO 154. The channel receive logic for channels A, B, C and D are designated as channel receive logic 150a,150b,150cand 150drespectively and receive parallel data over buses RXCEDa<9:0>-RXCEDd<9:0>. The outputs of the channel receive logic 150a,150b,150cand 150dare coupled to inter-channel alignment logic 156 which in turn has outputs that are coupled to a descrambler 158 and a control ECC Decoder 160. The outputs from the descrambler 158 are coupled to receive interleave and data ECC decode logic 162. The outputs from the receive interleave and data ECC logic 162 and the control ECC decode logic 160 are coupled to the XGMII receive controller 164. The XGMII receive controller produces at its output the original parallel data word on the bus RXX_D<63:0>, the original control byte on bus RXX_C<7:0> and a receive clock RXX_CLK. The receive interleave and data ECC logic 162 also provides as an output the bit M of the monitor channel as depicted in FIG. 7.

[0222] Alignment of receive data is achieved in several steps. Each step is dependent on acquisition of the previous steps. Acquisition starts with achieving word-frame alignment within each channel. The channels are then de-skewed to achieve inter-channel alignment and finally the scrambler states are acquired during an idle transmission.

[0223] The receive channels are synchronous but do not have a defined phase at the input to the receiver after de-serialization. All channels are synchronized to a master channel which in the present embodiment is defined to be channel A. Inter-channel alignment is accomplished in the inter-channel alignment block 156. The inter-channel alignment block includes a FIFO structure in the respective channels to permit the changing of clock domains.

[0224] The bit error rate (BER) during acquisition is assumed to be reasonably good (better than 1E-6) such that there is a high probability that correlation calculations done over 256 words will not experience an error.

[0225] Word Frame Alignment

[0226] Word framing logic that may be employed in each of the receive channels is depicted with greater particularity in FIG. 8. Word framing within each channel is obtained by checking for correct parity across a word (20 bits). The word frame control state machine shifts the word framing until the parity calculations are correct over a sample period (typically 256 words). Acquisition is then declared. This process is duplicated in all the channels. The parity R1 bit is derived from scrambled data and can be considered to have a random distribution. This allows acquisition to be obtained with a low probability of false alignment.

[0227] The parity calculation is done over 20 receive bits to produce the Channel Error (CE) variable. $\mathrm{CE}\left(n\right)=!\sum _{k=0}^{19}\mathrm{RX}\left(k\right)=0$

[0228] Each CE bit has roughly a 50% chance of being correct (=0) in a random data stream. Integrating over N samples gives the required low probability of false alignment. $\sum _{n=0}^N\mathrm{CE}\left(n\right)=0$

[0229] The probability of false alignment is 3E-39 if the calculation is done over 128 words (N=128), 9E-78 over 256 words (N=256) with random data.

[0230] One exemplary technique for obtaining word framing is illustrated in FIG. 8. The received word is delayed in a register 180 to produce a delayed word and fed into a multiplexer 182 along with the un-delayed word. The multiplexer 182 has access to 40 contiguous bits of the serial stream and can re-frame across the arbitrary word boundary presented at the physical coding layer 14 logic input. The Word Frame Control logic 184 uses the output of parity logic 186 to search through the 20 possible framing options until the correct frame location is acquired. More specifically, as indicated above, the parity check logic inspects the 20 bit frame presented and provides an indication of no error if CE(n)=0 and provides an indication of a channel error if CE(n)=1. The word frame control logic 184 provides an output signal Word Lock once proper word framing has been achieved. Correct word framing is virtually assured by confirming correct parity over a large number of samples, such as 128 or 256 samples.

[0231] Receiver Inter-channel Alignment

[0232] FIG. 9 depicts an exemplary block diagram for achieving inter-channel alignment of received parallel data words. Inter-channel alignment is needed to avoid the possibility of word skew between the respective serial channels. Once word framing is achieved in all channels and the R1 bits (RX19) have been identified in each channel, inter-channel alignment can proceed. Inter-channel alignment relies on the property that the R1 parity bits sum to zero if the channels are correctly aligned (in the absence of errors).

[0233] A(n)=R1_a+R1_b+R1_c+R1_d==0

[0234] The A bit has a roughly 50% chance of being correct (=0) in a random data stream. Integrating over N samples gives the required low probability of false alignment. $\sum _{n=0}^{N}A\left(n\right)=0$

[0235] The probability of false alignment is 3E-39 if the calculation is done over 128 words (N=128), 9E-78 over 256 words (N=256) with random data.

[0236] Inter-Channel alignment can be achieved by delaying specific channels relative to other channels. Referring to FIG. 9 each channel contains word delay logic 200. The delay logic 200 in the presently disclosed embodiment includes cascaded delay registers 202, 204, 206 and a MUX 208 that selects one of the progressively delayed versions of the receive words. The number of delay stages required is a function of the possible skew that may occur during transmission through the channel and is system dependent. The implementation in FIG. 9 allows for an inter-channel skew of +/−1 word. A greater number of cascaded delay registers may be employed. The multiplexer 208 in each channel can select the appropriate delayed word as the operative input to the MUX 208. The Inter-Channel Alignment Control logic 210 adjusts the delays until the R1 bits across the four channels sum to 0 over a predetermined number of samples.

[0237] The FIFO structure of the inter-channel alignment block lends itself to re-synchronizing the B, C and D receive clocks into the channel A clock domain. The FIFOs can be initialized after word alignment has been achieved in each channel, which guarantees an acceptable BER in each channel and the link is operating in a steady state with no phase gradients caused by the phase locked loops (PLLs).

[0238] The search pattern used to acquire inter-channel alignment is somewhat arbitrary however the highest probability of achieving alignment is around the equal delay point across channels. Searching around this point can minimize acquisition time. Table 7 shows a weighted-search over +/−1 word. Executing the search in Table 8 after Table 7 will achieve a weighted-search over +/−2 words.

[0239] Channel A is used as the delay reference (always 0) and negative numbers indicate that channel is advanced relative to channel A while positive numbers indicate they are retarded in Tables 7 and 8.

[0240] Receiver Control Decoder

[0241] Control decoding can proceed once correct word and inter-channel alignment of the serially received data is achieved. The control portion of the cell is not scrambled and can be decoded without scrambler synchronization. The redundant nature of the control coding allows for correction of any single bit error or detection of double bit errors in the control bits of the cell (R0 and R1 in RXCI<18> and RXCI<19> respectively). A block diagram depicting exemplary Control ECC Decoder Logic 160 is shown in FIG. 10. The method used to decode the control word is shown in FIGS. 11aand 11b. The R0 and R1 bits (RXCI<19:18>) are decoded in K word estimation logic 220 to give an estimate of K in accordance with the equations set forth below.

[0242] {circumflex over (K)}₀=!(R0_a+R0_d+R1_d)=!(RX<18>_a+RX<_d+RX<19>_d)

[0243] {circumflex over (K)}₁=!(R0_b+R0_a+R1_a)=!(RX<18>_b+RX<_a+RX<19>_a)

[0244] {circumflex over (K)}₂=!(R0_c+R0_bR1_b)=!(RX<18>_c+RX<_b+RX<19>_b)

[0245] {circumflex over (K)}₃=!(R0_d+R0_c+R1_c)=!(RX<18>_d+RX<_c+RX<19>_c)

[0246] The estimated value of K is then checked and corrected, if required, in K word correction logic 222. Correction is possible because the control information in K can be recovered from only two channels and the channel parity checks indicate which channel is in error. The dependence of the K value to the channel is clear from the equations above.

[0247] {circumflex over (K)}₀=F(A,D)

[0248] {circumflex over (K)}₁=F(A,B)

[0249] {circumflex over (K)}₂=F(B,C)

[0250] {circumflex over (K)}₃=F(C,D)

[0251] Where F(x) indicates the output is a function of x. The coding of K is such that the correct value of K can be regenerated with the loss of any one channel. The Control State, C<1:0>, is decoded from the corrected K value in K word decode logic 224 and status flags are generated in status flag generation logic 226. In particular, the status flag generator asserts an error signal in the event a single bit error is detected, asserts a MultError signal in the event a multi-bit error is detected and asserts a CorC signal in the event a single bit error in the control field C<1:0> has been detected and corrected.

[0252] The flow diagram of FIGS. 11aand 11billustrates the operation of the control ECC decoder depicted in FIG. 10 and discussed above. Estimated values of K bits are calculated as described above and as illustrated in step 250. Inquiry is made whether any parity errors were detected in the respective channels as shown in inquiry steps 252 and 254.

[0253] If a single parity error is detected in channel A as indicated by a CE<a:d> value of 1000, the correct value of K is calculated based on the R0 values contained in channels 2 and 3 as indicated in step 256. If a single parity error is detected in channel B as indicated by a CE<a:d> value of 0100, as indicated in step 258, the correct value of K is calculated based on the R0 values contained in channels 0 and 4. If a single parity error is detected in channel C as indicated by a CE<a:d> value of 0010, as indicated in step 260, the correct value of K is calculated based on the R0 values contained in channels 0 and 1. If a single parity error is detected in channel D as indicated by a CE<a:d> value of 0001, as indicated in step 262, the correct value of K is calculated based on the R0 values contained in channels 1 and 2. A variable Error is then set to equal true, as depicted in step 266 to indicate that a single channel error has been detected. If as a result of inquiry step 254 it is determined that CE<a:d> indicates errors in two or more channels, control passes to step 278.

[0254] A determination is, next made whether there is an error in K in inquiry step 268. If there is no error in K, the control bits C<1:0> are decoded as a function of K as illustrated in step 270. Inquiry is then made whether the value of K equals the value of K estimated as depicted in step 272. If K=K estimated, no control error was detected and control decoding is terminated as illustrated in step 276. If K does not equal k estimated, control passes to step 274. In step 274 an indication is recorded that a single bit control error has been detected and corrected. Following step 274, control decoding is terminated as indicated in step 276.

[0255] If it is determined in step 268 that there is an error in K, control passes to step 278 and an indication of an error and the fact that the error involves a multi-channel error is recorded. The C values are then set to a default condition as illustrated in step 280 since the multiple errors cannot be corrected. Following step 280 control passes to step 276 and control decoding is terminated.

[0256] Receiver De-scrambler

[0257] The De-scrambler 158 uses the same side scrambler structure as the transmitter with the added complexity of having to acquire current scrambler state. Each channel has a separate de-scrambler 158a,158b,158cand 158d(see FIG. 7). A more detailed block diagram depicting an exemplary structure of the de-scramblers 158a,158b,158cand 158dis shown FIG. 12. The receive logic can detect when an Idle cell is being transmitted with the decoded Control State data appearing on control lines C<1:0> . This will occur frequently during the Inter Packet Gap (IPG) of a normal Ethernet transmission. Presence of Idle cells can be guaranteed by use of the well known Far End Fault protocol given in the Ethernet standard. The Idle state is defined to have 0×0000 in the 16 least significant bits of the data payload in each channel. The Idle is scrambled in each channel but if the data field is zeros then RXCI<14:0> is the scrambler state (seed) in each channel. The scrambler seed is recovered and loaded into the receiver scramblers. The sequence can be completely recovered in one idle period because the sequence length is 15 and the complete state is defined in each channel's data payload. The Monitor bit and its effect on the error correction terms do not effect the bits used for scrambler seed acquisition and are not restricted during idle transmission. The scrambler state can be recovered in each channel separately or the receiver can use the property that all channels have synchronized scrambler states which are offset from each other by a known amount.

[0258] A state machine controls the scrambler state acquisition and verifies that the scrambler remains in lock during Idle cells. Scrambler states between channels can also be optionally checked. The data ECC, which follows the scrambler, also provides an indication of loss of scrambler sync by recording a high number of multiple errors.

[0259] Referring to FIG. 12, scrambler control logic 308 decodes control signals C<1:0> to determine when an idle character is being transmitted. In response to detection of an idle, an acquire signal is conveyed to the 2:1 MUX 306 to acquire the seed for the respective channel.

[0260] De-scrambler Implementation

[0261] An exemplary side-stream de-scrambler implementation is depicted in FIG. 12. Each of the de-scramblers 158a,158b,158c,158d(See FIG. 7) employs the logic depicted in FIG. 12 in a preferred embodiment. 2:1 MUX 300 has an output bus that is coupled to pseudo random binary sequence (PRBS) register 301. The output of PRBS register 301 is coupled to one input of 2:1 MUX 306. Received cipher data from bus RXCI_Data<17:0> is coupled to the second input of 2:1 one MUX 306. The MUX 306 is controlled by Scrambler Control 308. The MUX 306 is set to accept cipher data from bus RXCI_Data<17:0> during acquisition or set to accept the output of PRBS register 301 X<14:0> during normal receive operation. The output of the MUX 306 is coupled to the inputs of primary feedback logic 302 and secondary feedback logic 304. The outputs of the primary and secondary feedback logic are fed back to the inputs of the two to one MUX 300. Either the primary or secondary feedback logic outputs are selected as the operative input to the two to one MUX 300 in response to a primary/secondary selection control signal 311. Exclusive OR logic 310 receives as inputs received cipher data from bus RXCI_Data<17:0> and the PRBS register 301 outputs X<17:0>. The signals on RXCI_Data<17:0> and X<17:0> are exclusive ORed by exclusive OR logic 310 to produce plain data RXP<17:0> at each of the respective De-Scrambler outputs; e.g. RXPa<17:0>, RXPb<17:0>, RXPc<17:0> and RXPd<17:0>.

[0262] The feedback equations for the primary sequence are the same as for the Transmit Scrambler 54 (See FIG. 3) and are shown below.

[0263] XPnext0=X3+X4;

[0264] XPnext1=X4+X5;

[0265] XPnext2=X5+X6;

[0266] XPnext3=X6+X7;

[0267] XPnext4=X7+X8;

[0268] XPnext5=X8+X9;

[0269] XPnext6=X9+X10;

[0270] XPnext7=X10+X11;

[0271] XPnext8=X11+X12;

[0272] XPnext9=X12+X13;

[0273] XPnext10=X13+X14;

[0274] XPnext11=X0+X1+X14;

[0275] XPnext12=X0+X2;

[0276] XPnext13=X1+X3;

[0277] XPnext14=X2+X4;

[0278] XPnext15=X3+X5;

[0279] XPnext16=X4+X6;

[0280] XPnext17=X5+X7;

[0281] Similarly, the feedback equations for the secondary sequence are the same as for the Transmit Scrambler 54 (See FIG. 3) and are shown below.

[0282] XSnext0=X3+X7;

[0283] XSnext1=X4+X8;

[0284] XSnext2=X5+X9;

[0285] XSnext3=X6+X10;

[0286] XSnext4=X7+X11;

[0287] XSnext5=X8+X12;

[0288] XSnext6=X9+X13;

[0289] XSnext7=X10+X14;

[0290] XSnext8=X0+X4+X11;

[0291] XSnext9=X1+X5+X12;

[0292] XSnext10=X2+X6+X13;

[0293] XSnext11=X3+X7+X14;

[0294] XSnext12=X0+X8;

[0295] XSnext13=X1+X9;

[0296] XSnext14=X2+X10;

[0297] XSnext15=X3+X11;

[0298] XSnext16=X4+X12;

[0299] XSnext17=X5+X13;

[0300] The outputs of the respective de-scramblers provide plain data that are identified as RXPa<17:0>, RXPb<17:0>, RXPc<17:0> and RXPd<17:0> as indicated above. The de-scrambler output buses are coupled to the inputs of the Receive Interleaver and Data ECC Decoder 162 which is shown in FIG. 7 and depicted with greater particularity in FIG. 13.

[0301] Receive Interleave and Data ECC Decoder

[0302] The Receive Interleave and Data ECC Decoder 162 (See FIG. 7) recovers the data from each of the channels and performs the Data ECC Decoder function. An exemplary block diagram of a Receive Interleave and Data ECC Decoder is depicted in FIG. 13. The receive interleave 320 (See FIG. 13) is performed in accordance with the following equations to reproduce the original data ordering in the input to the transmit interleaver 53 (See FIGS. 3 and 4). The interleave function may simply comprise recombination of the RXP<17:0> plain data to form the original data word, the ECC bits E<6:0> and the monitor bit M.

[0303] RXP<71:0>=<RXPd17, RXPd16,

[0304] RXPc17, RXPc16, RXPb17, RXPb16,

[0305] RXPa17, RXPa16, RXPd15 . . . RXPd0,

[0306] RXPc15 . . . RXPc0, RXPb15 . . . RXPb0,

[0307] RXPa15 . . . RXPa0>

[0308] Receive Data ECC Decoder

[0309] The Receive Data ECC Decoder 162 (See FIG. 7) is illustrated in greater detail in FIG. 13. The receive data ECC decoder uses the redundant E<6:0> bits in the physical coding sublayer cell payload contained with the respective RXP channels RXPa, RXPb, RXPc and RXPd to detect and correct errors in the data payload. The data from each channel are combined using the receive interleave logic 320. The syndrome S<6:0> is calculated in the syndrome generator 322 over the 72-bit payload using the syndrome generation equations set forth below.

[0310] S0=RXP2+RXP5+RXP9 +

[0311] RXP10+RXP11+RXP16+RXP18 +

[0312] RXP19+RXP20+RXP21+RXP22 +

[0313] RXP25+RXP27+RXP29+RXP30 +

[0314] RXP31+RXP34+RXP35+RXP37 +

[0315] RXP41+RXP44+RXP45+RXP46 +

[0316] RXP47+RXP51+RXP53+RXP58 +

[0317] RXP59+RXP65;

[0318] S1=RXP0+RXP3+RXP6 +

[0319] RXP10+RXP11+RXP12+RXP17 +

[0320] RXP19+RXP20+RXP21+RXP22 +

[0321] RXP23+RXP26+RXP28+RXP30 +

[0322] RXP31+RXP32+RXP35+RXP36 +

[0323] RXP38+RXP42+RXP45+RXP46 +

[0324] RXP47+RXP48+RXP52+RXP54 +

[0325] RXP59+RXP60+RXP66;

[0326] S2=RXP0+RXP1+RXP4 +

[0327] RXP7+RXP11+RXP12+RXP13+RXP18 +

[0328] RXP20+RXP21+RXP22+RXP23+RXP24 +

[0329] RXP27+RXP29 +

[0330] RXP31+RXP32+RXP33+RXP36 +

[0331] RXP37+RXP39+RXP43+RXP46 +

[0332] RXP47+RXP48+RXP49+RXP53 +

[0333] RXP55+RXP60+RXP61+RXP67;

[0334] S3=RXP1+RXP2+RXP5 +

[0335] RXP8+RXP12+RXP13+RXP14 +RXP19 +

[0336] RXP21+RXP22+RXP23+RXP24 +

[0337] RXP25+RXP28+RXP30+

[0338] RXP32+RXP33+RXP34+RXP37 +

[0339] RXP38+RXP40+RXP44+RXP47 +

[0340] RXP48+RXP49+RXP50+RXP54 +

[0341] RXP56+RXP61+RXP62+RXP68;

[0342] S4=RXP0+RXP2+RXP3 +

[0343] RXP6+RXP9+RXP13+RXP14 +

[0344] RXP15+RXP20+RXP22+RXP23 +

[0345] RXP24+RXP25+RXP26+RXP29 +

[0346] RXP48+RXP49+RXP50+RXP51 +

[0347] RXP55+RXP57+RXP62+

[0348] RXP63+RXP69;

[0349] S5=RXP0+RXP1+RXP3 +

[0350] RXP4+RXP7+RXP10+RXP14 +

[0351] RXP15+RXP16+RXP21+RXP23 +

[0352] RXP24+RXP25+RXP26+RXP27 +

[0353] RXP30+RXP32+RXP34+RXP35 +

[0354] RXP36+RXP39+RXP40+RXP42 +

[0355] RXP46+RXP49+RXP50+RXP51 +

[0356] RXP52+RXP56+RXP58+RXP63 +

[0357] RXP64+RXP70;

[0358] S6=RXP1+RXP4+RXP8 +

[0359] RXP9+RXP10+RXP15+RXP17+RXP18 +

[0360] RXP19+RXP20+RXP21+RXP24+

[0361] RXP26+RXP28+RXP29+

[0362] RXP30+RXP33+RXP34+RXP36 +

[0363] RXP40+RXP43+RXP44+RXP45 +

[0364] RXP46+RXP50+RXP52+RXP57 +

[0365] RXP58+RXP64+RXP71;

[0366] Any value for the generated syndrome other than zero indicates the presence of an error. All single bit errors will yield a unique syndrome value, which indicates the location of the error within the 72-bit field. The error location is determined in Lookup logic 324 using the illustrative lookup table shown in Table 9 below. The error is then cross-checked against the channel parity flags using error check logic 326 and corrected, if possible using error correction logic 328. The 64-bit data message and monitor bits are then extracted and coupled to the XGMII receive controller 164.

[0367] Multiple errors are checked using several methods that guarantee detection of all two-bit errors. The R1 channel parity bits are used to cross check the location of a single bit error. Absence of a parity error with a non-zero syndrome indicates a multiple bit error. A syndrome that does not map to a valid error location indicates a multiple bit error.

[0368] The method of operation of the data error correction code decoder is further illustrated in the flow chart depicted in FIGS. 14aand 14b.

[0369] The Data ECC Decoder first checks if multiple errors have been detected by the Control ECC Decoder 160 (See FIG. 7) using the Multiple Errors inquiry step 350 (See FIG. 14a). This is determined by examining the MultError input flag. If multiple errors are detected in inquiry step 350 the Data ECC Decoder does not attempt decoding and terminates though step 370 setting the MultError and Error status flags and through step 368. If no multiple errors were detected by inquiry step 350 the Data ECC Decoder calculates the syndrome in step 352. The syndrome value is checked in inquiry step 354. If the syndrome value is zero in inquiry step 354 the Data ECC Decoder checks if the Error flag is set in inquiry step 372. The Error flag indicates an error was detected in any channel by checking the parity. If an error was detected in inquiry step 372 the Data ECC Decoder terminates through step 370 setting the MultError and Error status flags and through step 368 because it is not possible to get a zero syndrome value and a channel error without having multiple errors. If the Error flag is not set in inquiry step 372, then the Data ECC Decoder terminates through the No Data Error step 372 and through step 368 because no error was detected and no correction is required. If the syndrome value checked in inquiry step 354 is non-zero then the syndrome detected an error. The Data ECC Decoder then checks if the Error flag in inquiry step 356 has detected an error in any channel parity. If the Error flag is not set in inquiry step 356 the Data ECC Decoder terminates through step 370 setting the MultError and Error status flags and through step 368 because it is not possible to get a non-zero syndrome value and no channel error without having multiple errors. If the Error flag detected an error in inquiry step 356 then the Data ECC Decoder proceeds to calculate the error location in step 358 because the syndrome and Error flags are both consistent in detecting an error. The Calculate Error Location step 358 calculates the error location from the syndrome value which is then checked by the Valid Error Location inquiry step 360. If the error location is not valid in inquiry step 360, i.e., it does not correspond to any of the 72 received bits in RXP<71:0>, the Data ECC Decoder terminates though step 370 setting the MultError and Error status flags and through step 368 because it is not possible to have a bad error location without having multiple errors. If the error location is validated by inquiry step 360 the Data ECC Decoder calculates which channel the error occurred in using the Calculate Error Channel step 362. The error channel is calculated from the error location and the known mapping of error location to transmitted channel. The error channel (EC) determined by step 362 is then checked against the channel error (CE) determined by the parity checks in each channel using inquiry step 364. If the two error channel indicators do not match in inquiry step 364 the Data ECC Decoder terminates through step 370 setting the MultError and Error status flags and through step 368 because it is not possible to get inconsistent channel errors without having multiple errors. If the channel error indicators match in inquiry step 364 the Data ECC Decoder corrects the single bit error in step 366. The bit value at the calculated error location is flipped. The Data ECC Decoder then sets the error flag to false indicating an error is no longer present and sets the corrected data (CorD) flag indicating a single bit error has been corrected in the data field. The Data ECC Decoder then terminates through step 368.

[0370] XGMTT Receive Controller

[0371] The XGMII receive control logic 164 (See FIG. 7) translates the receive state and data into XGMII format for delivery to the MAC 11 within the system interface 10 (See FIG. 1). Mapping into the XGMII format is straightforward. Any uncorrected physical coding sublayer cell error received during a packet will generate corresponding symbol error(s) on the equivalent bytes on the XGMII. Cell errors received during idle will typically be discarded. In the event the XGMII interface requires cell errors to be identified to the MAC as a false carrier event, they should be so indicated.

[0372] Receiver Monitors and Statistics

[0373] The Receive State Sync Controller (See FIG. 7) assures that synchronization of the received signal is obtained in the correct sequence and monitor the errors within the channel to declare the link down when the error rate reaches an unsustainable level. Synchronization is first achieved within each channel (Word Lock), then inter-channel alignment (Cell Lock), and then scrambler synchronization (Sync Lock). Any loss of synchronization by the lower process will automatically cause loss of the higher level synchronization states. The status of each of the receive blocks is indicated by flags and are collectively shown as RxFlags (See FIG. 7). Word Lock indicates if word synchronization has been achieved in each channel. Cell Lock indicates that the complete physical coding sublayer cell is correctly aligned across all channels. Sync Lock in each channel indicates that the scramblers have acquired their correct states.

[0374] After acquisition, the receive logic goes into a track mode where errors are detected and counted. Parity errors within each channel are indicated by the channel error variable, CE<a:d>. The corrected control flag, CorC, indicates single control errors. Single data field errors are indicated by the corrected data flag, CorD. Multiple bit errors are indicated by the MultError flag, which can be generated either by the Control FEC Decoder or the Data FEC Decoder. MultError generates symbol error(s) on the receiver XGMII if they occur in a data frame.

[0375] The two single bit error flags (corrected control, CorC and corrected data, CorD) should be summed. A channel error mask (CE<a:d>) is used to keep separate counters on single bit errors per channel.

[0376] Multiple bit errors (100% of two-bit errors, lower probability of detection with higher bit errors) are accumulated in a separate counter. The error location of multiple bit errors is not guaranteed using physical coding sublayer encoding so only a single counter is employed in a preferred embodiment.

[0377] It will be apparent to those of ordinary skill in the art that modifications to and variations of the above described methods and apparatus may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.