Semiconductor laminated module

[0002] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-184783, filed Jun. 19, 2001, the entire contents of which are incorporated herein by reference.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor laminated module, for example, comprising a plurality of laminated unit packages loaded with thin film semiconductor chips that are flip-chip connected with base substrates.

[0005] 2. Description of the Related Art

[0006] An example of a constitution of a semiconductor laminated module according to the prior art will be described with reference to FIG. 4. FIG. 4 shows a sectional view of the prior art module. The semiconductor laminated module 41 is constituted by sequentially laminating, for example, three unit packages 42a, 42band 42c. For example, a semiconductor chip 44ahaving a thickness of, for example, about 100 μm is flip-chip connected to an upper surface of a base substrate 43amade of a glass-epoxy resin, and is bonded with a chip adhesive 45asuch as a film-like thermosetting resin adhesive comprising, for example, an epoxy-based resin, whereby the unit package 42aas the lowermost layer is constituted. The semiconductor chip 44ais integrally bonded onto the base substrate 43awith a substrate adhesive 46ato complete the unit package 42a. A plurality of solder balls 47 are provided on a lower surface of the base substrate 43a, and they constitute connecting terminals to be connected with external devices.

[0007] On the lowermost unit package 42a, the unit package 42bas a second layer is laminated, and the unit package 42cas a third layer is further laminated. An upper surface of the unit package 42cof the third layer is covered with a base substrate 43d, thereby forming a laminated body of the semiconductor laminated module 41.

[0008] During the unit packages 42a, 42band 42care laminated sequentially, they are pressured together and heated, thus sequentially bonded using substrate adhesives 46a, 46band 46csuch as a Prepreg composed of a thermosetting resin adhesive such as an epoxy-based resin. Thus, a three-layer laminated body is formed as shown in FIG. 4.

[0009] The base substrate 43dprovided on the uppermost unit package 42cas a cover is made from a glass-epoxy resin similarly to the base substrates 43a, 43band 43c, and bonded with the substrate adhesive 46c.

[0010] After the three unit packages 42a, 42band 42care laminated, through holes 48aand 48bare formed to penetrate the three-layer laminated body at both sides of the semiconductor chips 44a, 44band 44c. Copper plating layers 49aand 49bare formed on the inside walls of the through holes 48aand 48b.

[0011] When a heat-cycle test is performed on the semiconductor package 41 thus formed by laminating the unit packages 42a, 42band 42cas shown in FIG. 4, the package 41 would be warped. This warp would cause detachment of each flip-chip connection portions between the base substrates 43a, 43band 43cand the semiconductor chips 44a, 44band 44c. This causes the adhesion of the laminated parts in the laminated body to be less reliable. In addition, when the semi-conductor chips 44a, 44band 44care in thin film forms, the semiconductor laminated package 41 is warped repeatedly in the heat-cycle test, which in some cases causes cracks in one or more of the semiconductor chips 44ato 44c.

[0012] Considering causes of the above-mentioned prior art problems, it is evident that, after the semi-conductor chips 44ato 44care flip-chip connected to the base substrates 43ato 43c, the warp is caused by stress occurred by a difference of thermal expansion amount between chip adhesives 45ato 45c, which are used as seal resin films for sealing lower sides of the semiconductor chips 44ato 44c, and the substrate adhesives 46ato 46c, which are used as seal resin films for sealing upper sides of the semiconductor chips 44ato 44cwhen the unit packages 42ato 42care laminated. Further, it is evident that the warp is also caused by stress occurred by a difference of their elasticity modulus that varies with the temperature.

[0013] A semiconductor laminate module according to one aspect of the present invention comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive; a second adhesive for forming a laminated body by bonding the plurality of unit packages to each other; a third adhesive formed to cover upper surfaces of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive; and an uppermost substrate bonded to an uppermost unit package with the second adhesive.

[0014] FIG. 1 is a sectional view showing a semiconductor laminated module according to a first embodiment of the present invention.

[0015] FIG. 2 is a sectional view showing a constitution of a unit package, which is a component of the first embodiment semiconductor laminated module shown in FIG. 1.

[0016] FIG. 3 is a sectional view showing a laminated body constituted by laminating three unit packages each having the constitution of FIG. 2 in a manufacturing process of the semiconductor laminated module shown in FIG. 1.

[0017] FIG. 4 is a sectional view showing an example of a constitution of a prior art semiconductor laminated module.

[0018] One embodiment of the present invention will be described with reference to FIG. 1 to FIG. 3.

[0019] FIG. 1 shows a completed semiconductor laminated module 11 according to the first embodiment of the present invention. The semiconductor laminated module 11 is constituted by laminating three unit packages 12a, 12band 12cin a vertical direction. The module 11 is formed as a square thin plate of 12 mm×18 mm to have an overall thickness of about 780 μm.

[0020] For example, as shown in FIG. 2, the lowermost unit package 12aincludes a base substrate 13ahaving a thickness of 60 μm made of a glass-epoxy resin. On an upper surface of the base substrate 13a, a plurality of wirings 23a-1, 23a-2, 23a-3 and 23a-4 formed by, for example, patterning copper foil, are formed having a thickness of about 100 μm, for example. Any metal foil may be used for the copper foil.

[0021] On the base substrate 13a, for example, a square semiconductor chip 14aof 10 mm×13 mm is flip-chip connected. On a lower surface of the semiconductor chip 14a, a plurality of solder bumps acting as input/output terminals 14ab-1, 14ab-2, 14ab-3 and 14ab-4 are formed. These input/output terminals 14ab-1, 14ab-2, 14ab-3 and 14ab-4 are selectively electrically connected to the wirings 23a-1, 23a-2, 23a-3 and 23a-4 formed on the upper surface of the base substrate 13a.

[0022] The sides of the input/output terminals 14ab-1, 14ab-2, 14ab-3 and 14ab-4 are covered with a first chip adhesive 15asuch as a film-like thermosetting resin adhesive made of an epoxy-based resin having a thickness of about 40 μm. for example. In this state, the semiconductor chip 14ais bonded to the base substrate 13a.

[0023] On a lower surface of the base substrate 13a, copper wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 are provided in the same way as the wirings 23a-1, 23a-2, 23a-3 and 23a-4, so that the copper wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 may be connected to the solder bumps 21ato 21eshown in FIG. 1, respectively.

[0024] As shown in FIG. 1, an upper surface of the semiconductor chip 14ais covered with a second chip adhesive 17abeing a film-like thermosetting resin adhesive made of an epoxy-based resin having the same composition and thickness as those of the first chip adhesive 15a. Then, a substrate adhesive 18asuch as a Prepreg composed of a thermosetting resin adhesive of an epoxy-based resin is deposited in a way to cover the whole of the semiconductor chip 14aand the first and second chip adhesives 15aand 17a, with an upper surface of the second chip adhesive 17aexposed from the substrate adhesive 18a. In this way, the unit package 12ais completed. The chip adhesives 15aand 17amay be formed of the same material, or may be formed of any material, provided that they have substantially the same thermal expansion coefficient.

[0025] The other unit packages 12band 12care constituted in the same way as the unit package 12a.Although not shown in FIG. 1, the base substrates 13band 13cmay have the same or similar wirings formed on their upper and lower surfaces as the wirings 23a-1, 23a-2, 23a-3 and 23a-4 and the wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 in the same or similar way as the base substrate 13ain FIG. 2. If this manufacturing scheme is used, a merit of mass production can be realized for the base substrates 13ato 13c. This is effective for reducing manufacture costs of the semiconductor laminated module.

[0026] Then, to an upper surface of the unit package 12c, an uppermost substrate 13dmade of a glass-epoxy resin having a thickness of 60 μm is bonded using the substrate adhesive 18csuch as a Prepreg composed of a thermosetting resin adhesive of an epoxy-based resin, for example.

[0027] FIG. 3 shows a three-package laminated body constitution manufactured in such a way.

[0028] Furthermore, in the laminated body in which the unit packages 12ato 12care three-dimensionally laminated, semiconductor chips 14ato 14care laminated in an aligned fashion in such a manner that the semiconductor chips 14ato 14care positioned at corresponding positions within the unit packages 12ato 12c. In predetermined positions of the unit packages 12ato 12cand of the base substrate 13dwhich are adjacent to the semiconductor chips 14ato 14c, as shown in FIG. 1, a plurality of through holes are formed through the laminated body. In FIG. 1, only two through holes 19aand 19bpenetrating the laminated body are shown. Inside the through holes 19aand 19b, copper plating layers 20aand 20bare provided. As shown in FIG. 2, these copper plating layers 20aand 20bare selectively connected to predetermined wirings among the wirings 23a-1, 23a-2, 23a-3 and 23a-4 and the wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 that are formed on the upper and lower surfaces of the base substrate 13arespectively. For example, in FIG. 2, one copper plating layer 20ais connected to an upper wiring 23a-1 that is connected to the semiconductor chip 14avia the bump 14ab-1 and the lower wiring 24a-1. The other copper plating layer 20bis connected to the upper wiring 23a-4, which is connected to the semiconductor chip 14avia the bump 14ab-4, and the lower wiring 24a-6. Though not shown in the figure, other unit packages 12band 12care also connected in the similar way.

[0029] Furthermore, to the lower wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 that are provided on the lower surface of the base substrate 13aof the lowermost unit package 12a, solder balls 21a, 21b, 21c, 21dand 21eare stuck, as shown in FIG. 1. The semiconductor laminated module 11 is thus completed.

[0030] The manufacture processes of the semiconductor laminated module 11 having such a constitution as above described will be performed in the following steps.

[0031] First, as shown in FIG. 2, the semiconductor chip 14ais flip-chip connected to a predetermined position on the lowermost base substrate 13awith the first film-like chip adhesive 15aprovided in between, whereby the lowermost unit package 12 is constituted. Then, the second film-like chip adhesive 17ais put on the semiconductor chip 14a, and the substrate adhesive 18ais applied to the whole upper surfaces of the base substrate 13aand the semiconductor chip 14a.

[0032] Next, as in the lowermost unit package 12a, the semiconductor chip 14bis flip-flop connected to a predetermined position on the second base substrate 13bwith the first film-like chip adhesive 15bprovided in between. The second or middle unit package 12bthus constituted is laminated on the second chip adhesive 17aand the substrate adhesive 18athat are provided to cover the lowermost semiconductor chip 14a.

[0033] Then, the second film-like chip adhesive 17bis put on the semiconductor chip 14b, and the substrate adhesive 18bis applied to the whole upper surfaces of the base substrate 13band the semiconductor chip 14b.

[0034] Next, as in the lowermost unit package 12a, the semiconductor chip 14cis flip-flop connected to a predetermined position on the uppermost substrate 13cwith the first film-like chip adhesive 15cprovided in between. The uppermost unit package 12cthus constituted is laminated on the second chip adhesive 17band the substrate adhesive 18bthat are provided to cover the semiconductor chip 14bof the middle unit package 12b.

[0035] Then, the second film-like chip adhesive 17cis put on the semiconductor chip 14c. The substrate adhesive 18cis applied to the whole upper surfaces of the base substrate 13cto cover the side surfaces of the semiconductor chip 14c.

[0036] Finally, the uppermost substrate 13dis put on the second chip adhesive 17cand the substrate adhesive 18c, thereby forming the laminated body shown in FIG. 3.

[0037] After the laminated body shown in FIG. 3 formed by sequentially laminating the unit packages 12ato 12cis manufactured, it is heated, for example, at a predetermined temperature of 180° C., and at the same time is given a pressure of, for example, 20 kg/cm for 70 minutes in the vertical direction between the lowermost base substrate 13aand the uppermost substrate 13d. During the heat and pressure applying step, the substrate adhesives 18ato 18care flown into spaces formed between each two adjacent base substrates to fill the spaces. Then, the first, second and third adhesives are hardened in a room temperature, for example.

[0038] In this way, the unit packages 12ato 12cshown in FIG. 3 form a three-dimensional laminated body.

[0039] After this, the through holes 19aand 19bare formed to penetrate through predetermined positions of the laminated body. The insides of the through holes 19aand 19bare covered by the copper plating layers 20aand 20b. Furthermore, to the lower wirings 24a-1, 24a-2, 24a-3, 24a-4 and 24a-5 that are provided on the lower surface of the base substrate 13a, the solder balls 21ato 21eare stuck and formed respectively as shown in FIG. 1.

[0040] After the semiconductor laminated module 11 constituted as above is heated and pressured, its warp is checked. The warp is much reduced and there are not any cracks found in the flip-chip connection portions between the base substrates 13ato 13cand the semiconductor chips 14ato 14c, and the adhesion of the laminated portions is still good. In the heat cycle test, as the semiconductor chips 14ato 14care put between the first and second chip adhesives 15ato 15cand 17ato 17cthat have an equal composition and thickness, and that have equal or almost equal thermal expansion coefficient, it is possible to reduce stress occurring in the semiconductor chips 14ato 14cdue to the temperature change of the laminated body. Further, there is no crack caused in the semiconductor chips 14ato 14cthemselves. Thus, the fear of cracks to be caused is reduced. Therefore, even when the semiconductor chips 14ato 14care thinly formed, the semiconductor laminated module 11 can be still reliable. It is best for the first and second chip adhesives 15ato 15cand 17ato 17cto employ the same adhesive material. However, different adhesive materials may be used as the first and second adhesives if they have substantially the same or similar thermal expansion coefficient. In addition to the same or similar thermal expansion coefficient, if adhesive materials, which have substantially the same or similar change rate of elasticity modulus dependent on temperature change, are used, there are no differences in the stress change caused by elasticity modulus change according to the temperature change. This never causes a warp of the semiconductor laminated module and no stress change occurs.

[0041] According to the above-mentioned embodiment, the semiconductor chips 14ato 14chave a thickness of 100 μm. The same advantage can be obtained as above in those that have a thickness of 200 μm or less at which cracks of the semiconductor chips may occur.

[0042] As apparent from the above description, according to the present invention, warping that occur when unit packages are three-dimensionally laminated is reduced. Detachment of semiconductor chips that are flip-chip connected to the base substrates is reduced. The adhesion of the laminated parts is maintained unchanged. There is no fear of cracks to be caused even in thin semiconductor chips. It is thereby possible to provide a semiconductor laminated module with improved reliability.

[0043] Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general invention concept as defined by the appended claims and their equivalents.