Wafer start order release algorithm in a foundry fab

[0002] 1. Field of Invention

[0003] This invention relates generally to optimization of scheduling and release of foundry fab wafer orders and, more particularly, to a lot release control algorithm in a foundry fab producing multiple products that have different due dates and different process flows.

[0004] 2. Description of Related Art

[0005] In a typical foundry making wafers there are many constraints that affect the efficiency of the process. For optimization of the entire process there must be an attempt to maximize the output of the wafers and minimize the entire cycle from start to finish. There is no systematic optimized order release model that provides this scheduling. With the many variables present in running a wafer fab line, conflicts may result in idle time for the tools and wait time for the product. Even worse, promised delivery dates to customers can be missed when the wafer fab becomes too busy due to conflicts and delays with other processing.

[0006] On-time delivery of wafer is also impacted by bottlenecks caused by tool problems. Once tool problems present themselves, all schedules using the malfunctioning tools are delayed. This can cause a ripple effect that has a major impact on the current customer's wafers and on subsequent orders. Without a good method to factor in these impacts, it becomes difficult to give the customers accurate new completion dates. With optimized order release capability, schedules can more successfully be met with the result of happier and retained customers.

[0007] Several methods or systems related to wafer process control are available. In U.S. Pat. No. 4,887,218 (Natarajan) a conceptual decision analysis tool for production release planning is described. In U.S. Pat. No. 5,369,570 (Parad) a method for continuous real-time management of heterogeneous interdependent resources is described. In U.S. Pat. No. 5,796,614 (Yamada) a level-by-level explosion method for material requirements planning is provided. In U.S. Pat. No. 5,594,639 (Atsumi) an order process control model is described. In U.S. Pat. No. 6,119,102 (Rush et al.) a Manufacturing Requirements Planning (MRP) system is provided. Finally, in U.S. Pat. No. 5,093,794 (Howie et al.) a job scheduling system for jobs without special purpose coding is provided.

[0008] An optimized order release algorithm could save significant time and money in a number of situations and cut down on missed schedules that could result in a loss of customers.

[0009] This invention provides a start order release method to achieve maximum output with a minimum of cycle time, thus saving processing time and money due to the increased efficiencies from the method. The first overall objective is to provide a control model that with a planned step-by-step process optimizes release of work lots in a manufacturing line.

[0010] A second, more specific, objective is to provide a set of control algorithms to determine the most optimum control model for production of lots, taking into consideration the start date of processing, the committed due date, theoretical process time, and customers' needs.

[0011] Another specific objective is to provide lower and upper bound constraints to control the processing using linear programming techniques on which the final development of the Start To Build (STB) plan is based.

[0012] These objectives are achieved by using a specified lot release algorithm. The algorithm takes into account multiple products that have different due dates plus different process flows. Using the algorithms with linear program techniques, the method of this invention produces more accurate start schedules and high resource utilization while minimizing the number of late orders. This method has been found useful for foundry wafer fab systems to maximize output in wafer production and minimize cycle time in real production environments.

[0013] This invention will be described with reference to the accompanying drawings, wherein:

[0014] FIG. 1 is a flow diagram of the original way an order is released in prior art.

[0015] FIG. 2 is a flow diagram of the lot release control model method of the present invention.

[0016] FIG. 3 is two tables that show the equations of X-ratio definition and the upper bound constraint generation algorithm.

[0017] FIG. 4A is a table with lot simulation examples.

[0018] FIG. 4B is a table with lots selected by X-ratio rule.

[0019] FIG. 4C is a table with lots selected by the lower bound rule.

[0020] FIG. 4D is a table with lots selected by the upper bound rule, and

[0021] FIG. 4E is a table with lots in final release order.

[0022] FIG. 1 shows a flow diagram that best describes the prior art and the problem that exists with that prior art. A chip manufacturing fab line runs on a continuous 24 hours-a-day basis with a mix of customer orders. The choice of different tool technology depends on their function and type, such as logic or SRAM products, and can be varied during fabrication. Each tool has an inherent speed and capacity, and one tool may be dependent on another forcing undesirable idle time for these expensive tools. As a customer order begins 110, a delivery date is given to the customer, and the customer has an expectation that the date will be met. As the order is released 120 to the first tool for processing, that required technology tool (Tech #) 130 begins its work. Once that tool is completed 140 it goes to the next tool. Multiple customer orders are begun if the following order or orders use a different tool so as to keep all tools as busy as possible. When the orders reach the next tool 150, some may need the same tool and have to wait or some may not need the tool at all and the tool remains idle.

[0023] Complexity increases as more tools are needed to satisfy the customer order. More tool idle time and order waiting result. Missed customer completion dates and reduced customer satisfaction result. The cost of the idle tools and lost opportunity to use all tools concurrently increases the cost of running the fab line.

[0024] FIG. 2 is a flow diagram of the new method of the lot release control model. This is used for each customer order. Each order is put through the constraints of the model to determine when to start its production in relation to other work so that all the tools of the fab line will be in use. An X-ratio is calculated for each lot that gives a relationship between the start dates and the processing time. This x-ratiospec, it is sometime called, becomes the primary value by which the lots are sorted to insure customer delivery dates are always meet. The lots, in X-ratio sorted order, are processed based on this order using linear programing (LP) equations techniques. An upper bound on the high x-ratio value (lots where time to produce is not critical) is chosen by manufacturing engineers to insure that time constrained lots are always processed first. A lower bound constant on the X-ratio is also chosen to immediately get those lots into production regardless of the LP equations results. Use of this X-ratio provides an easy to use and calculate value to bound (upper and lower) the linear program equations making the method results fast and easy to program. FIG. 3 shows the necessary equations to control the model. The term X-ratio 302 is defined as follows 304:

[0025] X-ratio=(Ci−D)/Ti

[0026] where:

[0027] Ci=Committed due date of the ith lot

[0028] D=Wafer start date

[0029] Ti=Theoretical process time of the ith lot

[0030] The upper bound constraint generation uses a Linear Programming (LP) model to handle the variables required by the technology processing 310. The Max. Daily Output becomes the daily start quantity and is the upper bounds constraint of each technology tool to avoid bottlenecks. The LP model is as follows:

[0031] Objective Function 320

[0032] Max Daily Output: Y=X₁+X₂+ . . . +X_j

[0033] Subject to 330

[0034] a₁₁X₁+a₁₂X₂+ . . . +a_1jX_j≦S₁*W₁*A₁*24_(the_first_tools_constra int)

[0035] a₁₂X₁+a₂₂X₂+ . . . +a_2jX_j≦S₂*W₂*A₂*24_(the_second_tools_constra int)

[0036] . . .

[0037] a_i1X₁+a_i2X₂+ . . . +a_ijX_j≦S_i*W_i*A_i*24_(the_—ith_tools_constra int)

[0038] X₁≧0,X₂≧,X_j≧0

[0039] where:

[0040] Y=daily_start_quantity

[0041] X_j=the_daily_start_quatnity_of_the_—jth_technology_process

[0042] a_ij=the_repetitve_times_of_the_—ith_tool_type_in_—jth_technology_process_flow

[0043] S_i=total_tool_set_of_—ith_tool_type

[0044] W_i=WPH(wafer_per_hour)_of_the_—ith_tool_type

[0045] A_i=tool_available_time_of_—ith_tool_type

[0046] Using this lot release model, there are three control constraints that control the process. They are the X-ratio, the lower bound constraint, and the upper bound constraint. Using these formulas and the lot release model method, appropriate start schedules result that provide high resource utilization with a minimum number of late orders.

[0047] To see the entire wafer start order release algorithm with the lot release model, it is best to do a simulation by using real wafer lots. FIG. 4 is a table 410 that contains a set of orders we can call the original order distribution. Each lot is given a lot number. The X-ratio has been calculated using the customer due date, the start date, and the process time of the lot. A product number is assigned for tracking. The quantity and the technology group are assigned by customer specification.

[0048] Before the model can be used, the equations must be set using assumptions based on past experience with the wafer line and customer requirements. Past processing has shown that an X-ratio of 3.8 is reasonable. A maximum daily output of the fab has been determined to be 250 pieces. For the lower bound constraints, two equations are set from customer requests. They are:

[0049] 25 Logic≧50 pieces (pcs) for 0.25 Logic lower bound constraint

[0050] 50 Logic≧25 pcs for 0.5 Logic lower bound constraint

[0051] For the upper bound constraints three equations are set as follows:

[0052] SRAM≦50 pcs for SRAM upper bound constraint

[0053] 35 Logic≦75 pcs for 35 Logic upper bound constraint

[0054] Each product≦50 pcs for single product constraint

[0055] A daily start quantity (maximum daily output) is set to 250 pcs from past experience with the wafer line.

[0056] Using the lot release model in FIG. 2, the process begins 200 with the X-ratio calculation 204. This is called rule 1 of the model. Continuing with the lot release control model, we now have the necessary information to determine which lots should be considered for production first. Next there is a sort of all these unscheduled lots by X-ratio 208. In FIG. 4B are four lots that meet the X-ratio criteria. From the model 212 they meet the criteria and they take the path 214 that routes them to production and assigns them to the Start To Build (STB) plan.

[0057] The second lower bound constraint is now done on the remaining lots 216. In FIG. 4C there are two lots that meet the lower bound constraint 228. This is called rule 2. They are added to the STB plan 234. These are the lots that have special customer preferences. Remaining lots that do not meet the lower bounds are sorted by X-ratio 226.

[0058] The upper bound LP formula is used to select the remaining lots 238. In FIG. 4D four lots meet the upper bound constraint of the formula. This is called rule 3. If there were too many lots that meet the upper bound 242 then the STB plan needs to reselect lots by the sorted X-ratio and remove the lots with the highest X-ratio 244. This is done until the STB plan meets the upper bound constraint without exceeding the maximum daily output value of 250 that was set at the beginning for the fab 248. In this simulation, two of the lots are not part of the day's STB plan due to the 250 piece maximum being attained 254. FIG. 4E has the final order of the lots selected.

[0059] The method of the invention provides several advantages over the prior art. These include reduced expensive wait and idle time with the use of linear program techniques, the ability to create optimized start schedules, and high resource utilization with a minimum number of late customer orders.

[0060] While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.