Accurate resistance measurement for magnetoresistive head

[0002] The present invention relates generally to the field of magnetic data storage and retrieval systems. In particular, the present invention relates to a magnetic data storage and retrieval system having improved magnetoresistive head resistance measurement accuracy.

[0003] In magnetic data storage and retrieval systems, a magnetoresistive (MR) head utilizes MR elements to sense the selective magnetization of tracks on a magnetic data storage medium. A typical MR element is formed from an alloy of materials so as to have an electrical resistance which varies in the presence of a magnetic field. By passing a bias current through the MR element, the selective magnetization of a corresponding track can be determined in relation to variations in voltage detected across the MR element.

[0004] The sensitivity of an MR head depends on many factors. One of the most significant factors is the bias current provided to the MR head. The ability to read a signal from a magnetic medium is, in part, a function of the amount of bias current supplied to the MR head. Signal sensitivity can be increased by increasing the amount of bias current supplied to the MR head. Therefore, increased bias current will generally produce an improved signal-to-noise ratio and will therefore result in lower error rates.

[0005] However, excessive bias current can significantly shorten the useful life span of the MR head. It is important to ensure that the maximum power dissipation capability of the MR head is not exceeded. Because the MR element operates as a highly sensitive resistance, the power dissipated by the MR element will be proportional to the resistance of the MR element multiplied by the square of the bias current. Accordingly, there is an upper limit on the magnitude of the bias current that can be applied to any given MR head, and the application of too large a bias current, even momentarily, can stress the MR head and adversely affect its operational reliability over time.

[0006] Thus, in order to optimize the performance of the MR head, the maximum bias current that can be safely applied to the MR head must be determined. The accuracy in determining this optimal bias current depends directly on the accuracy in measuring the resistance of the MR head; the greater the accuracy of the MR head resistance measurement, the greater the accuracy that can be achieved in determining the optimal bias current. In this way, accurate measurement of the MR head resistance is crucial for optimal MR head performance.

[0007] Accordingly, there is a need for a magnetic data storage and retrieval system that measures the resistance of the MR head with greater accuracy in order to optimize the bias current to the MR head.

[0008] The present invention is a magnetic data storage and retrieval system. A preamplifier circuit is operably coupled to a magnetoresistive head and a resistor, and applies a first current to the magnetoresistive head and a second current to the resistor. A voltage measurement circuit measures a first voltage across the magnetoresistive head and a second voltage across the resistor. A resistance calculation circuit calculates a resistance of the magnetoresistive head based upon the first and second voltages.

[0009] FIG. 1 shows a block diagram of a prior art MR head resistance measurement system.

[0010] FIG. 2 shows a block diagram of an MR head resistance measurement system incorporating the present invention.

[0011] Magnetic data storage and retrieval systems typically utilize an MR head resistance measurement system located on the MR head chip to measure the resistance of the MR head whenever it is required to optimize a bias current to the MR head. This measurement can be done any time before the magnetic data storage and retrieval system performs a read function or a write function.

[0012] FIG. 1 shows a block diagram of a prior art MR head resistance measurement system 10. Prior art MR head resistance measurement system 10 measures the resistance of MR head 11, which is represented in FIG. 1 as a resistor R_MRH. Prior art MR head resistance measurement system 10 includes a preamplifier 12, a buffer stage 14, an analog-to-digital converter 16, and head nodes H1 and H2.

[0013] Preamplifier 12 has first and second output nodes connected respectively to head nodes H1 and H2. MR head 11 is connected between head nodes H1 and H2. Preamplifier 12 applies a bias current I_biasto MR head 11 from head node H1 to H2.

[0014] Buffer stage 14 has first and second input nodes, and an output node. The first and second input nodes of buffer stage 14 are connected respectively to head nodes H1 and H2. Buffer stage 14 measures a voltage V_MRHacross MR head 11 between its first and second input nodes. Buffer stage 14 then multiplies voltage V_MRHby a scale factor A (in this example A=5) and provides the resulting scaled voltage signal at its output node. Buffer stage 14 also electrically isolates preamplifier 12 from noise generated by analog-to-digital converter 16.

[0015] Analog-to-digital converter 16 has an input node connected to the output node of buffer stage 14. Analog-to-digital converter 16 converts the scaled voltage signal from buffer stage 14 to digital form, and then calculates the resistance R_MRHof MR head 11 according to the following equation:

[0016] R_MRH=V_MRH*A/I_bias

[0017] Prior art MR head resistance measurement system 10 typically experiences a measurement error of about 10-15%. Because the MR head resistance measurements are made in an operating environment where MR head 11 is used, prior art MR head resistance measurement system 10 is affected by circuit parameter variations such as temperature. The accuracy of the MR head resistance measurement depends on the accuracy of analog-to-digital converter 16, buffer stage 14, and bias current I_biasin this operating environment. A common method of reducing the measurement error of prior art MR head resistance measurement system 10 is to increase the accuracy of analog-to-digital converter 16. This is accomplished by increasing the complexity, or the number of bits, of analog-to-digital converter 16. Increasing the number of bits, however, significantly increases the die area, power consumption, and cost of analog-to-digital converter 16. As a result, it has not been previously possible to achieve a measurement error of less than 1% while satisfying the die area restraints and cost restraints required by today's magnetic data storage and retrieval systems.

[0018] FIG. 2 shows a block diagram of an MR head resistance measurement system 20 incorporating the present invention. MR head resistance measurement system 20 measures the resistance of MR head 21, which is represented in FIG. 2 as a resistor R_MRH. MR head resistance measurement system 20 includes a preamplifier 22, a buffer stage 24, an analog-to-digital converter 26, an external reference resistor R_ref, switches S1 and S2, head nodes H1 and H2, resistor nodes R1 and R2, and a fixed potential GND.

[0019] Preamplifier 22 has first, second, and third output nodes, wherein the first and second output nodes are used to provide a bias current I_biasand the third output node is used to provide a reference current I_ref. The first and second output nodes are connected respectively to head nodes H1 and H2, and the third output node is connected to resistor node R1. MR head 21 is connected between head nodes H1 and H2, and resistor R_refis connected between resistor nodes R1 and R2, with resistor node R2 connected to fixed potential GND. Preamplifier 22 applies bias current I_biasto MR head 21 from head node H1 to H2, and applies reference current I_refto resistor R_reffrom resistor node R1 to R2. Reference current I_refis typically much smaller than bias current I_biasto minimize power consumption. In addition, the value of resistor R_refis typically much greater than the resistance R_MRHof MR head 21 such that the ratio R_ref/R_MRHis approximately equal to the ratio I_bias/I_ref. This creates voltages of the same order across resistor R_refand MR head 21.

[0020] Buffer stage 24 has first and second input nodes, and an output node. The first and second input nodes of buffer stage 24 are connected respectively to switches S1 and S2. During a calibration mode, switches S1 and S2 selectively connect the first and second input nodes of buffer stage 24 to first and second resistor nodes R1 and R2, respectively. At this time, buffer stage 24 measures a voltage V_refacross resistor R_ref. Buffer stage 24 then multiplies voltage V_refby a scale factor A (in this example A=5) and provides the resulting scaled voltage signal at its output. During a measurement mode, switches S1 and S2 selectively connect the first and second input nodes of buffer stage 24 to first and second head nodes H1 and H2, respectively. At this time, buffer stage 24 measures a voltage V_MRHacross MR head 21. Buffer stage 24 then multiplies voltage V_MRHby scale factor A and provides the resulting scaled voltage signal at its output node. Buffer stage 24 also electrically isolates preamplifier 22 from noise generated by analog-to-digital converter 26.

[0021] Analog-to-digital converter 26 has an input node connected to the output node of buffer stage 24. Analog-to-digital converter 26 converts the scaled voltage signals from buffer stage 24 to digital form, and stores the digital voltage signals in memory. Analog-to-digital converter 26 then calculates the resistance R_MRHof MR head 21 according to the following equation: $R_{\mathrm{MRH}}=\frac{V_{\mathrm{MRH}}}{V_{\mathrm{ref}}}*\frac{R_{\mathrm{ref}}}{K}$

[0022] where K is a constant equal to the ratio I_bias/I_ref.

[0023] MR head resistance measurement system 20 typically experiences a measurement error of less than 1%. The measured resistance R_MRH(meas)of MR head 21 is expressed as: $R_{\mathrm{MRH}\left(\mathrm{meas}\right)}=\frac{V_{\mathrm{MRH}\left(\mathrm{meas}\right)}}{V_{\mathrm{ref}\left(\mathrm{meas}\right)}}*\frac{R_{\mathrm{ref}}}{K}$

[0024] where V_MRH(meas)is the measured voltage across MR head 21 and V_ref(meas)is the measured voltage across resistor R_ref. Measured voltages V_MRH(meas)and V_ref(meas)can be expressed as: $\begin{array}{c}{V}_{\mathrm{MRH}\left(\mathrm{meas}\right)}=V_{\mathrm{MRH}}\left(1+E_1\right)\\ V_{\mathrm{ref}\left(\mathrm{meas}\right)}=V_{\mathrm{ref}}\left(1+E_2\right)\end{array}$

[0025] where V_MRHis the actual voltage across MR head 21, E₁is the voltage measurement error associated with MR head 21, V_refis the actual voltage across resistor R_ref, and E₂is the voltage measurement error associated with resistor R_ref. From this the measured resistance R_MRH(meas)of MR head 21 can now be expressed as: $R_{\mathrm{MRH}\left(\mathrm{meas}\right)}=\frac{V_{\mathrm{MRH}}\left(1+E_1\right)}{V_{\mathrm{ref}}\left(1+E_2\right)}*\frac{R_{\mathrm{ref}}}{K}$

[0026] Because both measurement error E₁and E₂are measured by the same instrument and because voltages V_MRHand V_refare of the same order, any difference between measurement error E₁and E₂is negligible and the measurement errors cancel each other. As a result, the above expression can be reduced to: $R_{\mathrm{MRH}\left(\mathrm{meas}\right)}=\frac{V_{\mathrm{MRH}}}{V_{\mathrm{ref}}}*\frac{R_{\mathrm{ref}}}{K}$

[0027] This shows that the accuracy of measured resistance R_MRH(meas)does not depend on the accuracy of measured voltages V_MRH(meas)and V_ref(meas). Instead, the accuracy of measured resistance R_MRH(meas)depends only on the accuracy of resistor R_ref.

[0028] Therefore, if the value of resistor R_refhas an error (or tolerance) of less than 1%, then MR head resistance measurement system 20 will experience a measurement error of less than 1%.

[0029] Thus, the present invention provides a magnetic data storage and retrieval system that measures the resistance of the MR head with greater accuracy in order to optimize the bias current to the MR head.

[0030] Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.