Apparatus for pipe latch control circuit in synchronous memory device

[0002] The present invention relates to an apparatus for pipe latch control circuit in a synchronous memory device.

[0003] The most prominent issue of the semiconductor memory field is a synchronous memory device such as SDRAM, DDR, double data rate SDRAM and RAMBUS DRAM. Synchronous memory is advantageous in that the operation is fast compared to general memory devices.

[0004] In synchronous memory devices such as the DDR SDRAM, a pipeline method is applied to most of the data buses. FIG. 1 is a block diagram of a synchronous memory data path utilizing an ordinary pipeline method in accordance with the prior art.

[0005] In FIG. 1, the synchronous memory data path includes: four pipe latches 14A through 14D, a first switch 12 for selectively passing output data, which is applied from a global data bus gio to one of the pipe latches by pipe input control signals pinz<0:3>, a data output buffer 18 for outputting the data to a data output terminal DQ using a data output buffer drive signal clk_do and a second switch 16 for selectively passing each output of the pipe latches 14A through 14D to the data output buffer 18 by pipe output control signals poutz<0:3>.

[0006] Furthermore, in the above synchronous memory data path, the pipe output control signals poutz<0:3> are provided for controlling the output of the pipe latches 14A through 14D and they come from a pipe latch control circuit 10, which inputs an output enable signal outen and a DLL clock signal clk_dll.

[0007] Meanwhile, the pipe latch 14A is divided into an even path and an odd path in the DDR SDRAM, because the global data bus gio is divided into an even data bus and an odd data bus. Furthermore, the pipe latch control circuit 10 is classified into even and odd parts.

[0008] FIG. 2 is a circuit diagram of the pipe latch control circuit in accordance with the prior art.

[0009] In FIG. 2, the pipe latch control circuit is reset by a reset signal rstdoutz and starts counting when an increment signal outeninc is received.

[0010] However, the pipe latch control circuit includes an initial counting controller 20 for generating an initial counting signal. The rest of the units form four stage counters. Each counting stage includes a transfer gate controlled by the increment signal, an inverter latch and an ordinary counter.

[0011] FIG. 3 is a timing chart of the pipe latch control circuit shown in FIG. 2 in accordance with the prior art. In FIG. 3, let the burst length BL be 4 when using the SDRAM and the burst length BL be 8 when using the DDR SDRAM.

[0012] In the pipe latch control circuit in accordance with the prior art, the increment signal outeninc is generated by performing a NAND operation on the output enable signal outen and the DLL clock signal clk_dll. That is, the increment signal outeninc is generated by receiving the DLL clock signal clk_dll during the active cycle of the output enable signal outen. The output enable signal outen forms a window as much as the burst length for the data outputting the data.

[0013] The increment signal outeninc controls the transfer gate in order to output count signals k<0:3> through the latch. The count signals k<0:3> pass through three inverters to generate the pipe output control signals poutz<0:3>. That is, the pipe output control signals poutz<0:3> are enabled by synchronizing with a falling edge of the increment signal outeninc.

[0014] However, the DLL clock signal clk_dll passes through eight gates before the pipe control signals poutz<0:3> appear as in FIG. 2. Actually, the data output buffer drive signal clk_do for controlling the data output from a DQ pin is a delayed signal compared with the DLL clock signal clk_dll. Therefore, the data output buffer drive signal clk_do is enabled so that the data is outputted from the data output buffer within the enabling period of the pipe output control signals poutz<0:3> under normal conditions. However, the data output buffer drive signal clk_do receives the DLL clock signal clk_dll during the activation of the output enable signal outen.

[0015] However, the operation timing of all semiconductor circuits is greatly changed according to whether an operation condition is the best condition or the worst condition. In the prior art as mentioned above, after the DLL clock signal clk_dll is disabled, since the pipe output output control signal poutz<0:3> is generated by passing through 8 gates, a long delay time is caused. Specifically, a considerable difference of the delay time between the best condition and the worst condition can occur. Accordingly, in case of the worst condition, the corresponding data from the data output buffer may not be outputted completely within the enabling period of the pipe output control signals poutz<0:3>. Therefore, the memory access time TAA should be limited for the complete data output. As an operation frequency increase, a loss of the memory access time TAA can be a serious problem.

[0016] It is, therefore, an object of the present invention to provide an apparatus for a pipe latch control circuit in a synchronous memory device.

[0017] In accordance with an aspect of the present invention, there is provided an apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device, comprising: a plurality of counting stages for counting in sequence in response to a data output buffer drive signal; and a counting signal drive means for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.

[0018] The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0019] FIG. 1 is a block diagram of a synchronous memory data path utilizing an ordinary pipeline method in accordance with the prior art;

[0020] FIG. 2 is a circuit diagram of a pipe latch control circuit shown in FIG. 1 in accordance with the prior art;

[0021] FIG. 3 is a timing chart of the pipe latch control circuit shown in FIG. 2 in accordance with the prior art;

[0022] FIG. 4 is a pipe latch control circuit diagram of a synchronous memory device in accordance with the present invention; and

[0023] FIG. 5 is a timing chart of the pipe latch control circuit shown in FIG. 4.

[0024] Hereinafter, an apparatus for a pipe latch control circuit in a synchronous memory device according to the present invention will be described in detail with reference to the accompanying drawings.

[0025] FIG. 4 is a pipe latch control circuit diagram of the synchronous memory device in accordance with the present invention.

[0026] In FIG. 4, the pipe latch control circuit includes an initial counting signal generator 40 for generating an initial counting signal and a NAND latch unit 44 having a plurality of counting stages for generating pipe control signals poutz<0:3> by driving counting signals k<0:3>.

[0027] The initial counting signal generator 40 is controlled by a reset signal rstdoutz and it is configured identically to the initial counting controller 20 of the pipe latch control circuit shown in FIG. 2.

[0028] Each counting stage includes a transfer gate controlled by an increment signal outeninc_new, an inverter latch and an ordinary counter. However, the increment signal outeninc_new, which controls the transfer gate of each counting stage, uses an inverting signal of a drive signal clk_do in a data output buffer and an output signal of the initial counting signal generator 40 uses the initial counting signal k<0> without any delay.

[0029] Also, the initial counting signal generator 40 is placed in first counting stage rather than in a fourth counting stage as in the prior art. However, it is simply the change for using the output signal of the initial counting signal generator 40 and the initial counting signal generator 40 is operated the same as any other counting stage.

[0030] A NAND latch unit 44 includes NAND latches 44A through 44D for latching counting signals k<0:3> of each counting stage. Each NAND latch 44A through 44D is made up of two NAND gates and two inverters. For each NAND latch, the counting signal outputted from each counting stage becomes one input and the data output buffer drive signal clk_do becomes the other input. That is, each NAND latch is controlled by the data output buffer drive signal clk_do and the relevant counting signal k<0:3>, which is outputted from the corresponding counting stage.

[0031] FIG. 5 is a timing chart of the pipe latch control circuit shown in FIG. 4. In FIG. 5, let the burst length BL be 4 when using the SDRAM and the burst length BL is 8 in case of using the DDR SDRAM.

[0032] In the pipe latch control circuit of the present invention, a NAND operation is performed on the data output buffer drive signal clk_do to generate the increment signal outeninc_new. That is, the increment signal outeninc_new is generated by inverting the data output buffer drive signal clk_do rather than performing a NAND operation on the output enable signal outen and the DLL clock signal clk_dll as in the prior art.

[0033] First of all, once the reset signal rstdoutz is in logic ‘high’ and deactivated, the initial counting signal k<0> becomes logic ‘high’ in response to the reset signal rstdoutz and the initial pipe output control signal poutz<0> becomes logic ‘low’ because the data output buffer drive signal clk_do, which is in logic ‘low’, is inputted into the NAND latch unit 44.

[0034] Next, once the data output buffer drive signal clk_do becomes logic ‘high’, the data output buffer opens and the data is outputted to the data output terminal DQ. At the same time, the increment signal outeninc_new becomes logic ‘low’ and the pipe output control signal poutz<0> is maintained at the logic ‘low’ state. However, once the data output buffer drive signal clk_do becomes logic ‘high’, all the counters start the operation.

[0035] After that, the data output buffer is closed once the data output buffer drive signal clk_do is disabled to logic ‘low’. The increment signal outeninc_new is disabled to logic ‘high’ in order to disable the initial pipe output control signal poutz<0> to logic ‘high’. Also, the pipe output control signal poutz<1> is enabled by driving the counting signal k<1> in the next stage after latching from the NAND latch 44B.

[0036] In the present invention, the counter in each stage is incremented by receiving the data output buffer drive signal clk_do. That is, the counting signal is synchronized with the reset signal to generate the initial pipe output control signal poutz<0>. Once the data from the data output buffer is completely outputted to the data output terminal DQ by the data output buffer drive signal clk_do, the next pipe output control signal poutz<1> is enabled.

[0037] The possibility of the data output buffer drive signal clk_do deviating from the activated windows of the pipe output control signals poutz<0:3> is very low. This means, the loss of data access time TAA does not occur even in the worst conditions because the data output buffer drive signal clk_do passes through four gates to receive the data as soon as the data output buffer drive signal clk_do is disabled.

[0038] In the present invention, the numbers of counter stages and the logic configuration of the pipe latch control circuit can be changed.

[0039] According to the present invention, an erroneous operation of the memory device can be avoided by reducing the loss of data access time TAA and applying the operation frequency to the synchronous memory device.

[0040] While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.