Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integrated circuit used for a multi-chip package and a multi-chip package including a plurality of semiconductor integrated circuits.

[0004] 2. Description of Related Art

[0005] FIG. 12 is a diagram showing a configuration of semiconductor integrated circuits used for a conventional multi-chip package. In this figure, the reference numeral 1 designates a multi-chip package (called “MCP” from now on) for packaging a plurality of chips; and reference numerals 2aand 2beach designate a chip (semiconductor integrated circuit).

[0006] In the MCP 1, each reference numeral 3 designates an MCP external terminal.

[0007] In the chips 2aand 2b,each reference numeral 4 designates a pad, 5 designates an external output driver for outputting an internal signal to the outside of the MCP 1; 6 designates an internal input driver for inputting a signal from another chip within the MCP 1; 7 designates an internal output driver for outputting an internal signal to another chip within the MCP 1; reference numerals 8aand 8beach designate a module; and each reference numeral 9 designates a wire for connecting one of the MCP external terminals 3 with one of the pads 4.

[0008] FIG. 13 is a block diagram showing a configuration for an individual wafer test of a conventional chip. In this figure, the reference numeral 2adesignates a chip and 11 designates a tester.

[0009] In the chip 2a,the reference numeral 5 designates an external output driver and 7 designates an internal output driver, which correspond to the components designated by the same reference numerals in FIG. 12. In the tester 11, the reference numeral 12 designates a comparator. Reference numerals 13aand 13beach designate a load capacitance of the tester 11.

[0010] In FIG. 12, each couple of the pad 4 and external output driver 5 constitutes an external output terminal, each couple of the pad 4 and internal input driver 6 constitutes an internal input terminal, and each couple of the pad 4 and internal output driver 7 constitutes an internal output terminal. In addition, although not shown in FIG. 12, there is an external input/output driver for inputting a signal from the outside of the MCP 1 and for outputting an internal signal to the outside of the MCP 1. A couple of the pad and external input/output driver constitutes an external input/output terminal. Furthermore, there is an internal input/output driver for inputting a signal from another chip within the MCP 1 and for outputting an internal signal to another chip within the MCP 1. A couple of the pad and internal input/output driver constitutes an internal input/output terminal.

[0011] Next, the operation of the conventional device will be described.

[0012] The input/output terminals and output terminals of the chips 2aand 2bin the conventional MCP 1 have considerable sizes, and are divided into two types: terminals used as an external input/output terminals or external output terminals after packaging; and terminals used as an internal input/output terminals and internal output terminals after packaging.

[0013] As for the internal input/output terminals and internal output terminals, their drivers can be made smaller than the drivers of the external input/output terminals and external output terminals considering the usage after packaging.

[0014] However, for the individual wafer test as shown in FIG. 13 which is carried out before packaging, it is necessary for the drivers of the external input/output terminals and external output terminals and the drivers of the internal input/output terminals and internal output terminals to have a size needed for driving the load capacitances 13aand 13bof the tester 11, which are connected only during the test.

[0015] Therefore, although the size of the drivers of the internal input/output terminals and internal output terminals may be smaller than that of the drivers of the external input/output terminals and external output terminals after packaging, they must have about the same size for the individual wafer test before packaging.

[0016] With the foregoing configuration, the conventional semiconductor integrated circuit has a problem in that it is inevitable to increase the driver size of the internal input/output terminals and internal output terminals to drive the load capacitances 13aand 13bof the tester 11 before packaging. In addition, the improper driver size after packaging offers a problem of causing noise or increasing power consumption.

[0017] The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a semiconductor integrated circuit and multi-chip package capable of preventing noise and power consumption from being increased by optimizing the drive capacity after packaging.

[0018] According to a first aspect of the present invention, there is provided a semiconductor integrated circuit including driving power variably setting means for variably setting driving power of a driver in an internal input/output terminal or an internal output terminal, which is used for exchanging a signal with another semiconductor integrated circuit in the multi-chip package. It offers an advantage of being able to optimize the driving power after packaging, thereby suppressing the noise and power consumption.

[0019] According to a second aspect of the present invention, there is provided a multi-chip package including driving power variably setting means for variably setting driving power of a driver in an internal input/output terminal or an internal output terminal, which is used for exchanging a signal with another semiconductor integrated circuit in the multi-chip package, a driving power control pad for transferring a control signal to the driving power variably setting means; and an external terminal for transferring the input control signal to the driving power control pad. It offers an advantage of being able to optimize the driving power after packaging by supplying the control signal via the external terminal.

[0020] FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit used for a multi-chip package of an embodiment 1 in accordance with the present invention;

[0021] FIG. 2A is a diagram showing a detailed configuration of an internal output terminal;

[0022] FIG. 2B is a diagram showing a detailed configuration of an internal input/output terminal;

[0023] FIG. 3 is a waveform chart illustrating waveforms of an output signal corresponding to a control signal;

[0024] FIG.4 is a diagram showing a configuration of a semiconductor integrated circuit used for a multi-chip package of an embodiment 2 in accordance with the present invention;

[0025] FIG. 5 is a diagram showing a configuration of a multi-chip package on which the semiconductor integrated circuit is mounted;

[0026] FIG. 6 is a block diagram showing a detailed configuration from an external terminal 32 to an internal output driver 7;

[0027] FIG. 7 is a block diagram showing a configuration of a control signal generating circuit of an embodiment 3 in accordance with the present invention;

[0028] FIG. 8 is a circuit diagram showing a detailed configuration of the multiplexer of FIG. 7;

[0029] FIG. 9 is a circuit diagram showing a detailed configuration of an internal output driver based on a selector system of an embodiment 4 in accordance with the present invention;

[0030] FIG. 10 is a circuit diagram showing a detailed configuration of an internal output driver based on a path gate system of an embodiment 5 in accordance with the present invention;

[0031] FIG. 11 is a circuit diagram showing a detailed configuration of an internal output driver based on a clocked gate system of an embodiment 6 in accordance with the present invention;

[0032] FIG. 12 is a diagram showing a configuration of semiconductor integrated circuits constituting a conventional multi-chip package; and

[0033] FIG. 13 is a block diagram showing a configuration for an individual wafer test of a conventional chip.

[0034] The invention will now be described with reference to the accompanying drawings.

[0035] Embodiment 1

[0036] FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit used for a multi-chip package of an embodiment 1 in accordance with the present invention. In this figure, the reference numeral 2adesignates a chip (semiconductor integrated circuit).

[0037] In the chip 2a,each reference numeral 4 designates a pad; the reference numeral 5 designates an external output driver for outputting an internal signal to the outside of the multi-chip package (abbreviated to MCP from now on); 6 designates an internal input driver for inputting a signal from another chip within the MCP; 7 designates an internal output driver for outputting an internal signal to another chip within the MCP; 8adesignates a module; and 21 designates a control signal for variably setting the driving power of the internal output driver 7.

[0038] In FIG. 1, a pad 4 coupled to an external output driver 5 constitutes an external output terminal, a pad 4 coupled to an internal input driver 6 constitutes an internal input terminal, and a pad 4 coupled to an internal output driver 7 constitutes an internal output terminal. In addition, although not shown in FIG. 1, there is an external input/output driver for inputting a signal from the outside of the MCP and for outputting an internal signal to the outside of the MCP. A pad 4 coupled to an external input/output driver constitutes an external input/output terminal. Furthermore, there is an internal input/output driver for inputting a signal from another chip within the MCP and for outputting an internal signal to another chip within the MCP. A pad 4 coupled to an internal input/output driver constitutes an internal input/output terminal.

[0039] FIG. 2A is a diagram showing a detailed configuration of the internal output terminal 27. The internal output terminal 27 comprises the internal output driver 7 and a pad 4. The internal output driver 7 comprises a normally used driver 22 and a power adjusting driver 23, both of which are supplied with an internal signal 24, and the power adjusting driver 23 is supplied with a control signal 21. The output signal 25 of the internal output driver 7 is delivered outside via the pad 4.

[0040] FIG. 2B is a diagram showing a detailed configuration of the internal input/output terminal 29. It consists of an internal input/output driver 28 and pad 4, and the internal input/output driver 28 consists of the internal output driver 7 and an AND gate 30. The AND gate 30 outputs an input signal 26.

[0041] FIG. 3 is a waveform chart illustrating waveforms of an output signal corresponding to a control signal.

[0042] Next, the operation of the present embodiment 1 will be described.

[0043] The present embodiment 1 as shown in FIG. 1 is configured such that the control signal 21 variably sets the driving power of the internal output driver 7.

[0044] FIG. 2A shows the details of the internal output driver 7. It comprises the normally used driver 22 and power adjusting driver 23 connected in parallel. The parallel connection is supplied with the internal signal 24, and outputs the output signal 25. The power adjusting driver 23 is controlled by the control signal 21 such that its driving power undergoes on/off control.

[0045] For example, assume that the power adjusting driver 23 has the driving power equal to that of the normally used driver 22, and that the driving power of the power adjusting driver 23 is turned on by the “H” level control signal 21. When it is turned on, both the normally used driver 22 and power adjusting driver 23 drive the load on the output side simultaneously. In contrast, when the “L” level control signal 21 turns off the driving power of the power adjusting driver 23, only the normally used driver 22 drives the load on the output side.

[0046] Since they can secure sufficient driving power of the load capacitance between the tester and the internal input/output terminal or internal output terminal in the former case, they can solve the above-mentioned problem in the individual wafer test, thereby enabling a stable test.

[0047] In addition, since it is not necessary to drive large load capacitance after packaging, the latter setting is enough. That is, only the normally used driver 22 is used for driving the external load with the power adjusting driver 23 being used as an off transistor. Thus, the present embodiment 1 can prevent the noise and power consumption from being increased.

[0048] In the waveform chart of FIG. 3, while the control signal 21 is at “L” level, the power adjusting driver 23 is turned off so that only the normally used driver 22 drives the load on the output side. In this case, if the load on the output side is a large load such as that connected at the individual wafer test, the waveform of the output signal 25 cannot rise up to the power supply level Vcc. In contrast, if the load on the output side is a small load such as that after packaging, the waveform of the output signal 25 can rise up to the power supply level Vcc, and suppress the noise and power consumption in that case.

[0049] On the other hand, while the control signal 21 is at the “H” level, the power adjusting driver 23 is turned on so that both the normally used driver 22 and the power adjusting driver 23 drive the load on the output side. In this case, even if the load on the output side is a large load such as that connected at the individual wafer test, the waveform of the output signal 25 can rise up to the power supply level Vcc. In addition, if the load on the output side is a small load such as that after packaging, although the waveform of the output signal 25 can rise up to the power supply level Vcc, it is inevitable that the noise and power consumption will increase in this case.

[0050] As described above, the present embodiment 1 is configured such that it can variably set the driving power of all or part of the internal input/output terminals and internal output terminals, which are used only within the MCP. Thus, it can sufficiently drive the large load connected between the tester and the internal input/output terminal or internal output terminal by increasing the driving power during the individual wafer test before packaging. In addition, it can suppress the noise or power consumption by reducing the driving power after packaging.

[0051] Embodiment 2

[0052] FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit used for a multi-chip package of an embodiment 2 in accordance with the present invention. In this figure, the reference numeral 31 designates a driving power control pad through which the control signal 21 is input. The remaining configuration is the same as that of FIG. 1.

[0053] FIG. 5 is a diagram showing a configuration of a multi-chip package on which the semiconductor integrated circuit as shown in FIG. 4 mounted. In this figure, the reference numeral 1 designates a multi-chip package, 2bdesignates another chip (semiconductor integrated circuit), and 32 designates an external terminal connected to the driving power control pad 31 by the wire 9, for transmitting the input control signal 21 to the driving power control pad 31.

[0054] FIG. 6 is a block diagram showing a detailed configuration from the external terminal 32 to the internal output driver 7. In this figure, the reference numeral 32 designates the external terminal, 31 designates the driving power control pad, 33 designates a pull-down transistor, 34 designates an N-channel transistor, 35 designates a power supply Vcc, and 36 designates a ground. The reference numeral 7 designates the internal output driver.

[0055] Next, the operation of the present embodiment 2 will be described.

[0056] As shown in FIG. 4, the present embodiment 2 comprises the driving power control pad 31 for inputting the control signal 21 to the chip 2aused by the MCP.

[0057] Thus, the present embodiment 2 can supply the control signal to the driving power control pad 31 directly, thereby enabling the driving power to be variably set easily.

[0058] The configuration of FIG. 5 provides the MCP 1 with the external terminal 32 for transferring the control signal 21 to the driving power control pad 31.

[0059] Accordingly, it can readily optimize the driving power by supplying the control signal via the external terminal 32 even after packaging.

[0060] FIG. 6 is a block diagram showing a detailed configuration from the external terminal 32 to the internal output driver 7.

[0061] During the individual wafer test, the driving power control pad 31 is supplied with the “H” level control signal 21 so that the driving power of the power adjusting driver 23 is turned on. Thus, both the normally used driver 22 and power adjusting driver 23 drive the load on the output side by their driving power.

[0062] Other than the time of the individual wafer test such as after packaging, the external terminal 32 is supplied with the “L” level control signal 21 so that the driving power of the power adjusting driver 23 is turned off via the driving power control pad 31. Thus, only the normally used driver 22 drives the load on the output side by its own driving power.

[0063] The pull-down transistor 33 includes the N-channel transistor 34 which is brought into conduction by the power supply Vcc 35, even when the driving power control pad 31 is not supplied with the “L” level control signal 21 during the time other than the individual wafer test. Thus, the power adjusting driver 23 is supplied with the “L” level by the ground 36 in this case. Therefore, it is enough for the driving power control pad 31 to be supplied with the “H” level control signal 21 only during the individual wafer test.

[0064] As described above, the present embodiment 2 is configured such that the chip 2acomprises the driving power control pad 31 which is supplied with the control signal 21, or that the MCP 1 comprises the external terminal 32 which is connected to the driving power control pad 31. Thus, the present embodiment 2 can variably set the driving power easily by supplying the control signal 21 to the driving power control pad 31, or optimize the driving power at ease by supplying the control signal 21 via the external terminal 32 even after packaging.

[0065] Embodiment 3

[0066] FIG. 7 is a block diagram showing a configuration of a control signal generating circuit of an embodiment 3 in accordance with the present invention. In this figure, the reference numeral 41 designates a test signal that is input from the outside; 42 designates a multiplexer for generating the control signal 21 in response to the test signal 41 to variably set the driving power of the internal output driver 7; 43 designates other input signals; and 44 designates an auxiliary logic for processing the other input signals 43, and for supplying them to the internal output driver 7 as an internal signal 24.

[0067] FIG. 8 is a circuit diagram showing a detailed configuration of the multiplexer 42. In this figure, the reference numerals 45aand 45beach designate an inverter, 46aand 46beach designate an inverter, 47aand 47beach designate an AND gate, and the reference numeral 48 designates an OR gate.

[0068] Next, the operation of the present embodiment 3 will be described.

[0069] The present embodiment 3 as shown in FIG. 7 is configured such that the multiplexer 42 generates the control signal 21 in response to the test signal 41 supplied via the pads 4 of the chip 2aor the external terminals 3 of the MCP 1, thereby variably setting the driving power of the internal output driver 7.

[0070] FIG. 8 shows a detailed configuration of the multiplexer 42. It outputs the “H” level control signal 21 only when the input test signal 41 T[0:1] is {T[0]=L, T[1]=L}, and {T[0]=L, T[1]=H}.

[0071] As described above, the present embodiment 3 generates the control signal 21 in response to the test signal 41 supplied from the outside. Accordingly, it can readily optimize the driving power without the dedicated driving power control pad 31 or external terminal 32 used for variably setting the driving power.

[0072] Embodiment 4

[0073] FIG. 9 is a circuit diagram showing a detailed configuration of an internal output driver based on a selector system of an embodiment 4 in accordance with the present invention. In this figure, the reference numeral 51 designates an inverter for inverting the internal signal 24; 35 designates a power supply Vcc, 36 designates a ground, 51adesignates a P-channel transistor, and 51bdesignates an N-channel transistor.

[0074] The reference numeral 52 designates a selector section for enabling the power adjusting driver 23 in response to the control signal 21; reference numerals 52aand 52beach designate an inverter; the reference numeral 52cdesignates an OR gate; and 52ddesignates an AND gate.

[0075] The normally used driver 22 comprises a P-channel transistor 22a,and an N-channel transistor 22b.

[0076] The power adjusting driver 23 comprises a P-channel transistor 23aand an N-channel transistor 23b.

[0077] The reference numeral 53 designates an off transistor comprising a P-channel transistor 53aand an N-channel transistor 53b.

[0078] Next, the operation of the present embodiment 4 will be described.

[0079] The inverter 51 inverts the internal signal 24 and outputs it. The normally used driver 22 further inverts the inverted internal signal 24, and supplies it to the pad 4 via the off transistor 53. The off transistor 53 is provided as anti-surge measures.

[0080] When supplied with the “H” level control signal 21, the selector section 52 supplies the internal signal 24 passing through the inverter 51 to the gates of the P-channel transistor 23aand N-channel transistor 23bof the power adjusting driver 23 through the OR gate 52cand AND gate 52d,thereby enabling the power adjusting driver 23 to operate as an internal output driver.

[0081] On the other hand, when supplied with the “L” level control signal 21, the selector section 52 supplies the gates of the P-channel transistor 23aand N-channel transistor 23bof the power adjusting driver 23 with “H” level through the OR gate 52cand “L” level through the AND gate 52d,respectively, regardless of the internal signal 24 passing through the inverter 51. Thus, the present embodiment 4 can make the power adjusting driver 23 an off transistor, which is effective as anti-surge measures.

[0082] As described above, the present embodiment 4 is configured such that the selector section 52 enables the power adjusting driver 23 in response to the control signal 21. Thus, it can variably set the driving power of the internal output driver.

[0083] In addition, the selector section 52 can use the power adjusting driver 23 as an off transistor during the time other than the individual wafer test, which is an effective anti-surge measure.

[0084] Although the single control signal 21 and power adjusting driver 23 are provided in the present embodiment 4, this is not essential. A plurality of control signals 21 and power adjusting drivers 23 can be provided to more finely adjust the driving power stepwise.

[0085] Embodiment 5

[0086] FIG. 10 is a circuit diagram showing a detailed configuration of an internal output driver based on a path gate system of an embodiment 5 in accordance with the present invention. In this figure, the reference numeral 61 designates a path gate section for enabling the power adjusting driver 23 in response to the control signal 21; reference numerals 61aand 61beach designate an inverter; 61cand 61deach designate a transmission gate; the reference numeral 61edesignates a P-channel transistor; and 61fdesignates an N-channel transistor.

[0087] The remaining configuration is the same as that of FIG. 9.

[0088] Next, the operation of the present embodiment 5 will be described.

[0089] When supplied with the “H” level control signal 21, the path gate section 61 turns off the P-channel transistor 61eby the “H” level output of the inverter 61b,and the N-channel transistor 61fby the “L” level output of the inverter 61a.In addition, the transmission gates 61cand 61dare both turned on by the “H” level output of the inverter 61band the “L” level output of the inverter 61a.Thus, the internal signal 24 passing through the inverter 51 is supplied to the gates of the P-channel transistor 23aand N-channel transistor 23bof the power adjusting driver 23, thereby enabling the power adjusting driver 23 to operate as the internal output driver.

[0090] In contrast, when supplied with the “L” level control signal 21, the path gate section 61 turns on the P-channel transistor 61eby the “L” level output of the inverter 61b,and the N-channel transistor 61fby the “H” level output of the inverter 61a.In addition, the transmission gates 61cand 61dare both turned off by the “L” level output of the inverter 61band the “H” level output of the inverter 61a.Thus, the power adjusting driver 23 is made an off transistor, which is an effective anti-surge measure.

[0091] As described above, the present embodiment 5 is configured such that the path gate section 61 enables the power adjusting driver 23 in response to the control signal 21. Thus, it can variably set the driving power of the internal output driver.

[0092] In addition, the path gate section 61 can set the power adjusting driver 23 as an off transistor during the time other than the individual wafer test, which is an effective anti-surge measure.

[0093] Although the single control signal 21 and power adjusting driver 23 are provided in the present embodiment 5, this is not essential. A plurality of control signals 21 and power adjusting drivers 23 can be provided to more finely adjust the driving power stepwise.

[0094] Embodiment 6

[0095] FIG. 11 is a circuit diagram showing a detailed configuration of an internal output driver based on a clocked gate system of an embodiment 6 in accordance with the present invention. In this figure, the reference numeral 71 designates a clocked gate section for enabling the power adjusting driver 23 in response to the control signal 21; 71adesignates an inverter, 71bdesignates a P-channel transistor, and 71cdesignates an N-channel transistor.

[0096] The remaining configuration is the same as that of FIG. 10.

[0097] Next, the operation of the present embodiment 6 will be described.

[0098] When supplied with the “H” level control signal 21, the clocked gate section 71 turns on the N-channel transistor 71cby the “H” level control signal 21, and the P-channel transistor 71bby the “L” level output of the inverter 71a.Thus, the present embodiment 6 can operate the power adjusting driver 23 as an internal output driver.

[0099] In contrast, when supplied with the “L” level control signal 21, the clocked gate section 71 turns off the N-channel transistor 71cby the “L” level control signal 21, and the P-channel transistor 71bby the “H” level output of the inverter 71a.Thus, the present embodiment 6 can make the power adjusting driver 23 an off transistor, which is effective as the anti-surge measures.

[0100] As described above, the present embodiment 6 is configured such that the clocked gate section 71 enables the power adjusting driver 23 in response to the control signal 21. Thus, it can variably set the driving power of the internal output driver.

[0101] In addition, the clocked gate section 71 enables the power adjusting driver 23 to be used as an off transistor during the time other than the individual wafer test, which is effective as the anti-surge measures.

[0102] Although the single control signal 21 and power adjusting driver 23 are provided in the present embodiment 6, this is not essential. A plurality of control signals 21 and power adjusting drivers 23 can be provided to more finely adjust the driving power stepwise.