Chip carrier for a high-frequency electronic package

[0002] The present invention relates to a chip carrier and an electronic package for a high-frequency electronic device.

[0003] Several types of electronic devices utilizing a circuit, which is integrated in a chip of semiconductor material, are possible. The chip is typically mounted on a chip carrier, so as to protect the chip from mechanical stresses, and is then encapsulated to produce an electronic package. The chip carrier includes an insulating substrate with conductive tracks, each track bonded to a corresponding terminal of the chip. Each track terminates at a contact pad (typically for connection to a printed circuit board).

[0004] The transmission of a signal in a corresponding conductive track generates an electromagnetic wave; the wave propagates along a transmission line defined by the conductive track and an underlying ground plane (which is connected to a reference voltage for shielding the conductive track from electromagnetic interference). When the chip operates at a high frequency (for example more than about 1 Gigahertz), the propagation of the wave (microwave) can severely affect the performance of the electronic package.

[0005] Particularly, any discontinuity (or transition) in the transmission line that the signal encounters as it travels along a conductive track, such as any change in structure, material properties and/or design features, generates a reflected wave. Moreover, the package includes stray structures (capacitors, inductors and resistors), which act as low pass filters for the transmitted signal. As a consequence, the integrity of the electromagnetic wave propagated along the transmission line degrades, especially at high frequencies.

[0006] The transmitted signal, switching between a low voltage (logic value 0) and a high voltage (logic value 1) generates a square-shaped wave. Because of discontinuities in the transmission line, this wave is generally received as a pseudo-sinusoidal wave. The quality of the transmitted wave can be visualized by a so-called “eye diagram”, which plots the value of the received signal as a function of the phase of a clock signal controlling the electronic package. The above described discontinuities in the transmission line reduce the central opening of the eye diagram. Therefore, it is quite difficult to understand if a switching transition has actually taken place or if the shift of a signal baseline is due to background noise.

[0007] These drawbacks are particular acute in modern electronic devices working with a reduced level of power supply voltage (down to 1.2 V). In this case, there is a very low margin to discriminate between the logic value 0 (1V) and the logic value 1 (1.2V).

[0008] Moreover, the continuous trend towards miniaturization of electronic devices requires a reduction in the dimensions of chip carrier conductive tracks on which such devices are packaged. However, the impedance of the transmission line must be maintained at a desired value which optimizes the performance of the electronic device (typically 50 W). Therefore, it is necessary to use a thin dielectric layer between the conductive tracks and the ground plane of the electronic package (since the impedance is inversely proportional to the track width and directly proportional to the dielectric layer thickness). A shortened distance between conductive tracks and the ground plane increases the value of a corresponding stray capacitance. As a consequence, the bandwidth of the transmission line is strongly reduced.

[0009] Therefore, as the quality of the transmission in the package is degraded it can cause the electronic device to operate at a frequency far lower than the working frequency which is afforded by the chip.

[0010] It is an object of the present invention to overcome the above mentioned drawbacks.

[0011] According to one aspect of the invention, there is provided a chip carrier comprising a first conductive layer having at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal, and a reference structure including a first conductive reference track insulated and spaced from the first conductive layer, the first conductive reference track having a first portion and a second portion spacedly positioned from the first portion, and a second conductive reference track insulated from the first conductive layer and the first conductive reference track, a portion of the second conductive reference track spaced between the first conductive layer and the first conductive reference track, the signal track substantially overlying the portion of the second conductive reference track, and the contact area substantially overlying the first portion of the first conductive reference track, the signal track being electrically shielded by the reference structure.

[0012] According to another aspect of the invention, there is provided an electronic package comprising a chip carrier including a first conductive layer having at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal, the chip carrier further including a reference structure including a first conductive reference track insulated and spaced from the first conductive layer, the first conductive reference track having a first portion and a second portion spacedly positioned from the first portion, and a second conductive reference track insulated from the first conductive layer and the first conductive reference track, a portion of the second conductive reference track spaced between the first conductive layer and the first conductive reference track, the signal track substantially overlying the portion of the second conductive reference track, and the contact area substantially overlying the first portion of the first conductive reference track, the signal track being electrically shielded by the reference structure, and a semiconductor chip positioned on the chip carrier and having at least one terminal electrically interconnected to the at least one contact area.

[0013] The above objects, advantages, and features of the present invention will become more readily apparent from the following detailed description of the presently preferred embodiments as illustrated in the accompanying drawings.

[0014] FIG. 1 is an enlarged isometric view of one embodiment of the present invention illustrating the electronic package having a portion of a molded cap cut away to expose a portion of a semiconductor chip and a chip carrier;

[0015] FIG. 2ais an top view of an enlarged portion of the chip carrier of FIG. 1;

[0016] FIG. 2bis a partial sectional view, in elevation as taken along line A—A in FIG. 2a;

[0017] FIGS. 3aand 3bare eye-diagrams of a signal in a known electronic package and in the chip carrier and electronic package of the present invention, respectively; and

[0018] FIGS. 4aand 4bare graphical representations of the bandwidths of the signals of the eye-diagrams of FIGS. 3aand 3b, respectively, in the frequency domain.

[0019] With reference to FIG. 1, there is depicted an electronic package 100 of the BGA (Ball Grid Array) type. The electronic package 100 includes a chip 105 of semiconductor material, wherein a power circuit working at a high frequency (for example with a clock rate of about 5 Gigahertz) is integrated. The chip 105 can be supplied by a low voltage power supply (for example of 1.2V).

[0020] The chip 105 is mounted on a chip carrier 110, having an insulating circuitized substrate 115 provided on a stiffener 120. The substrate 115 comprises a multilayer structure, with several conductive layers (made for example of copper) insulated from each other (for example by means of an epoxy resin with glass fibers). The stiffener 120 consists of a metallic plate (made for example of copper) which can also act as a heat-sink for dissipating heat produced by chip 105. A cavity 125, exposing a central region of stiffener 120, is positioned in substrate 115. The chip 105 is positioned in cavity 125 and bonded to stiffener 120 by means of an epoxy glue, which can compensate for the different coefficients of thermal expansion of chip 105 and stiffener 120.

[0021] The chip 105 is wire-bonded to chip carrier 110. Particularly, several contact terminals 130 are formed on an upper surface of the chip. Pads 132 are positioned on an upper surface of chip carrier 110. Each terminal 130 is connected to a corresponding pad 132 and conductive track 140 by means of a thin metal wire 135. Thin metal wire 135 can be made of aluminum. Each track 140 terminates at a contact area 145. An interconnecting ball, or bump, 150 (made of a eutectic solder, such as a Tin Lead alloy) is positioned on area 145. The entire chip 105 and a portion of substrate 115 around cavity 125 is then covered with a molded cap 155 (for example of a thermosetting epoxy resin). The molded cap 155 protects chip 105 from the external environment and from mechanical stresses and increases the rigidity of the entire electronic package 100. The electronic package 100 can be turned upside down and mounted on a printed circuit board (not shown), by soldering interconnecting balls 150 onto respective printed circuit board conductive tracks.

[0022] Likewise considerations apply if the electronic package is other than a BGA type (for example for a pad-to-pad connection to the printed circuit board), if the chip does not include a (digital) power circuit, if it operates at a different frequency or with a different power supply, and so on.

[0023] Considering now FIG. 2a, there is shown a conductive signal track 140sconnected to a contact area 145s(shown as a hidden contact area). An interconnecting ball 150sis positioned on the contact area. A circuit including conductive signal track 140s, contact area 145sand interconnecting ball 150scan be used for transmitting a high-frequency signal from chip 105 to a printed circuit board. A couple of co-planar tracks 140cland 140ch, respectively, are arranged on either side of conductive signal track 140s. The co-planar tracks 140cland 140chterminate at corresponding contact areas 145cland 145ch(both shown as hidden), respectively. Interconnecting balls 150cland 150chare positioned on contact areas 145cland 145ch, respectively, and can be connected to a reference voltage or ground planes in the printed circuit board to which the interconnecting balls can be assembled.

[0024] When a high-frequency signal is transmitted on conductive signal track 140san electromagnetic wave is generated which propagates along a transmission line defined by conductive signal track 140s, co-planar tracks 140cland 140chand an underlying ground structure (not shown in FIG. 2a).

[0025] The inventors have discovered that signal degradation and reduced performance of known electronic packages during signal transmission is mainly due to a discontinuity in the transmission line associated with interconnecting ball 150s. Specifically, the transmission line is subjected to a sharp change of direction, from an horizontal direction along signal track 140sto a vertical direction to interconnecting ball 150s, even greater than the one associated with wire bonding (assuming that the wire is kept shorter than 1 mm).

[0026] Particularly, a stray capacitor formed between contact area 145sand the underlying ground structure has a relative high capacitance of about 500 femtoFarads (fF), if compared to the stray capacitance formed between interconnecting balls 150sand 150cland between the interconnecting balls 150sand 150ch, which is in the order of about 10 fF.

[0027] Considering now a cross-section along the line A—A of FIG. 1, as shown in FIG. 2b, substrate 115 comprises several conductive layers 210a, 210b, 210cand 210d. The conductive layers 210a-210dare insulated from each other and from stiffener 120, by means of a dielectric material 212.

[0028] The conductive signal track 140sand the co-planar tracks 140chand 140clare formed in conductive layer 210awhich is defined as the first conductive layer starting from the upper surface of the chip carrier 110. A ground plane 215gis formed in conductive layer 210badjacent to first conductive layer 210aand is defined as a second conductive reference track. Moreover, a power plane 220pis formed in conductive layer 210c(adjacent to the conductive layer 210b) and is defined as the second conductive layer. A further ground plane 225gand one or more further conductive signal tracks 225s(not shown) for transmitting high-frequency signals are formed in conductive layer 210d. Conductive layer 210dis defined as the first conductive reference track.

[0029] Substrate 115 includes at least via-hole 230h. The shape of via-hole 230his a cylinder. The via-hole can also be the shape of a truncated cone or other shape suitable for making a connection from one conductive plane of substare 115 to another. The via-hole 230hincludes a conductive material on its sidewall that electrically connects ground planes 215g(connection is shown in phantom) and 225gto co-planar track 140ch, and then to the reference voltage though interconnecting ball 150ch. The power plane 220pis connected (through a further via-hole, not shown in the figure) to a power supply voltage of about 1.2V.

[0030] The ground planes 215gand 225gand the co-planar tracks 140chand 140cldefine a reference structure which controls the impedance of the transmission line associated with conductive signal track 140sand shields the conductive signal track from electromagnetic interference.

[0031] A portion 145sof conductive signal track 140s, excluding an area corresponding to an area substantially equal to the orthographic projection of interconnecting ball 150son conductive layer 210a, is superimposed in plan view onto ground plane 215gand the projection of its image creates a shadow onto ground plane 215g. The area 145sis superimposed in plan view onto ground plane 225g, without interposition of any other of conductive layers 210a-210cand the projection of its image creates a shadow onto ground plane 225g. In other words, ground plane 215gdoes not intersect a shadow of the projection of contact area 145s. Importantly, ground planes 215gand 225gdefine an open reference structure with a discontinuity in its uniformity corresponding to the discontinuity in the transmission line defined by the conductive signal track 140sand interconnecting ball 150s.

[0032] The power plane 220pand conductive signal track 225s(not shown) are arranged outside an umbra shadow of contact area 145s. The umbra shadow is defined by drawing a line from an end surface of conductive layer 210c(shown in phantom) to an end surface of ground plane 215gand forming an angle, A, of about 30°-60° (preferably about 45°) with end surface of ground plane 215g.

[0033] Likewise considerations apply if the chip carrier has a different structure, for example with two differential signal tracks arranged between the co-planar tracks, if the chip carrier includes a different number of conductive layers, if a further ground plane is provided on top of the first conductive layer wherein the signal tracks are formed, if the ground planes and the power plane consists of two or more distinct tracks, if the contact area has a different dimension, and so on. A differential signal track is defined as two conductors spaced closely in the same plane and forming a complete conducting loop path for a signal.

[0034] More generally, the present invention provides a chip carrier for a high-frequency electronic device including a circuitized substrate with a plurality of conductive layers insulated from each other. The conductive layers are arranged in a sequence from a first one of the conductive layers wherein a plurality of signal tracks are formed, each one terminating at a contact area for transmitting a high-frequency signal. The chip carrier includes a reference structure connectable to a reference voltage for shielding the signal tracks; the reference structure has at least one reference track formed in a second one of the conductive layers adjacent to the first conductive layer and at least one further reference track formed in one of the conductive layers different from the first and second conductive layer; a portion of each signal track excluding the contact area is superimposed in plan view to a corresponding reference track, and the contact area of each signal track is superimposed in plan view to a corresponding further reference track without interposition of any other of the conductive layers.

[0035] The invention substantially reduces the capacitance of the stray capacitor formed between conductive signal track 140sand ground plane 215g(being inversely proportional to the distance between them).

[0036] The invention maintains integrity of the electromagnetic wave propagated along the transmission line. Importantly, the proposed design of the chip carrier has minimal effects on the performance of the chip, so that the electronic package can operate at a frequency very close to the working frequency which is afforded by the chip.

[0037] Moreover, the solution according to the present invention maintains the bandwidth of the transmission line at a satisfactory value, even if the dimensions of the conductive signal track and/or the thickness of the dielectric layer between the conductive signal track and the adjacent ground plane(s) are reduced. The chip carrier of the present invention, makes it possible to produce high performance electronic packages with small dimensions.

[0038] With reference in particular to FIG. 3a, there is shown an eye-diagram for a known electronic device, with only a single ground plane adjacent to a signal track. The single ground plane also lies under the respective contact area of an interconnecting ball. The eye-diagram shows the value (in V) of a signal s(t) received from a transmission line as a function of the phase of a clock signal. The central portion of the eye-diagram is substantially closed, due to the discontinuities in the transmission line. An eye-diagram for the electronic package embodying the chip carrier of the present invention is shown in FIG. 3b. The eye diagram is more open, so that it is easier to discriminate an actual switching transition of the signal from a shift of a signal baseline due to a background noise. As a consequence, the electronic package can be operated at a high-frequency even with a reduced level of power supply voltage.

[0039] In other words, in the known electronic device the low-pass filter defined by the stray capacitor formed between the contact area and the underlying ground plane has a very low cut-off frequency. Therefore, as shown in FIG. 4a, only the first harmonic f₀of the signal s(f) (expressed in the frequency domain) is transmitted. On the other hand, the chip carrier and electronic package of the present invention increases the bandwidth of the transmission line up to the third harmonic 3f₀of the signal, as shown in FIG. 4b.

[0040] The preferred embodiment of the present invention described above offers further advantages. Particularly, ground plane 225gformed in the last conductive layer 210 of the chip carrier allows the contact area and the underlying ground plane to be as far apart as possible, so that the capacitance of the corresponding stray capacitor is reduced to a minimum value (of the order of about 100 fF).

[0041] The values proposed for the acute angle defining the umbra shadow substantially assures that no interference is created within the reference structure for the conductive tracks formed in the intermediate layers and assures that a minimal chip carrier area is utilized for the reference structure. The conductive signal tracks (not shown) formed in last layer 210doutside the umbra shadow allow full exploitation of this layer without any interference with ground plane 115gformed therein.

[0042] The co-planar tracks improve the control of the impedance of the transmission line. Moreover, they increase the shielding of the corresponding conductive signal track from electromagnetic interference.

[0043] Each via-hole connects each co-planar track to a corresponding ground plane in a very simple manner. Moreover, the interconnecting balls associated with each co-planar track guarantee a very uniform distribution of the reference voltage across the entire structure.

[0044] The particular type of the electronic package wherein the chip is embedded within the cavity of the substrate, bonded to the stiffener, and wire bonded to the chip carrier, better exploits the high performance of the chip carrier of the present invention.

[0045] Moreover, the chip carrier of the present invention leads itself to be used even in an electronic package of a different type, for example, a flip chip package without a chip cavity, and so on.

[0046] In order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations all of which, however, are included within the scope of protection of the present invention as defined by the following claims.