Method of forming inter-metal dielectric

[0002] 1. Field of the Invention

[0003] The present invention relates in general to a semiconductor technology. More particularly, it relates to a method of forming inter-metal dielectric (IMD) to prevent voids or seams formed in the dielectric.

[0004] 2. Description of the Related Art

[0005] Conductive materials, semiconductors, and insulating materials are widely applied in the integrated circuit (IC) industry, and the main technology for IC industry includes thin film deposition, photolithography, and etching. Thin film deposition deposits the materials as mentioned above onto a wafer to be fabricated. Photolithography reproduces desired device or circuit patterns in the photoresist layer over the thin films. Etching transfers the device or circuit patterns onto the thin films through the patterned photoresist layer, to form devices such as transistors or capacitors on the wafer.

[0006] After the devices or circuits are finished, metal wires connecting each device or circuit must be formed, referred to as metallization. In metallization, a nonconductive layer of dielectric material, such as silicon dioxide is often formed between the metal wires or devices. This dielectric layer may protect metal wires from physical or chemical damage, insulate metal wire from other wires, and insulate devices. Typically, this dielectric layer is called inter-layer dielectric (ILD) and inter-metal dielectric.

[0007] As semiconductor device geometries continue to decrease in size to provide more devices per fabricated wafer and faster devices, line width of the metal wires for connecting each device and the spacing between the metal wires has been reduced. However, as the spacing or gaps between these metal wires decrease, it becomes more difficult to fill the gap with the dielectric material because of increasing the aspect ratio of the gap.

[0008] Accordingly, the gap cannot be filled fully with the dielectric material by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Particularly, as the aspect ratio of the gap exceeds 3.5, voids or seams are formed in the gap during dielectric filling. As a result, the reliability of the devices is reduced.

[0009] Accordingly, an object of the invention is to provide a method of forming inter-metal dielectric to avoid voids or seams in the dielectric in the gap by reducing the aspect ratio of the gap through a double dielectric filling process.

[0010] To achieve these and other advantages, the invention provides a method of forming inter-metal dielectric. First, a substrate having a patterned metal layer thereon is provided, in which the patterned metal layer has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, a conformable protective layer is formed over the patterned metal layer and the opening. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids therein. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

[0011] The patterned metal layer is aluminum, the protective layer is silicon nitride, and the first and the second dielectric layer are high density plasma oxide. Moreover, the predetermined height is 1000˜1400 Å.

[0012] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:

[0013] FIGS. 1-4 are cross-sections showing a method of forming inter-metal dielectric according to the present invention.

[0014] A preferred embodiment of the present invention is now described with reference to FIGS. 1-4.

[0015] First, in FIG. 1, a substrate 100, such as silicon wafer, has semiconductor devices thereon. In this invention, a dielectric layer 102, such as silicon dioxide, can be formed on the substrate 100 to serve as an ILD. Subsequently, a metal layer (not shown), such as aluminum, is formed over the dielectric layer 102 by conventional deposition.

[0016] Next, the metal layer is etched using a patterned oxide layer (not shown) as a hard mask to form a patterned metal layer 104 with a plurality of openings 103 to expose dielectric layer 102. This patterned metal layer 104 serves as metal wire to connect semiconductor devices (not shown). In addition, these openings have an aspect ratio of 3.5˜5.

[0017] Next, in FIG. 2, a conformable protective layer 106 having a thickness about 100˜200 Å is deposited over the patterned metal layer 104 and the openings 103. In this invention, the protective layer 106 can be a silicon nitride layer to serve as an etch stop layer for subsequent etching, and prevent the patterned metal layer 104 from damage because of etching.

[0018] Thereafter, a dielectric layer 108 is deposited over the patterned metal layer 104 covered by the protective layer 106 and filled into the openings 103 by conventional deposition. In this invention, the dielectric layer 108 can be an oxide layer and formed by high density plasma CVD (HDPCVD), to form an island-shaped dielectric 108bover the patterned metal layer 104. The dielectric layer 108 insulates metal lines from other lines. As mentioned above, these openings 103 have a higher aspect ratio, as the dielectric layer 108 is filled into the openings 103 by HDPCVD, voids 108aare formed in the upper portion of the dielectric layer 108.

[0019] Next, in FIG. 3, the island-shaped dielectric 108band the upper portion of the dielectric layer 108 containing voids 108ain the openings 103, are removed by spin etching using dilute hydrofluoric acid (DHF) as etchant to leave the lower portion of the dielectric layer 110 with a predetermined height. In this example of the invention, the width of the opening 103 (metal line spacing) is about 0.11 μm, and the depth of the opening 103 is about 3850˜4950 Å.

[0020] Accordingly, the height of the remaining dielectric layer 110 is about 1000˜1400 Å, to reduce the aspect ratio of the opening 103 lower than 3.5 and without voids 108ain the remaining dielectric layer 110.

[0021] Finally, in FIG. 4, a dielectric layer 112 is deposited over the patterned metal layer 104 covered by a protective layer 106 and the remaining dielectric layer 110 to completely fill the openings 103.

[0022] Also, the dielectric layer 112 can be an oxide layer and formed by HDPCVD. Thus, the island-shaped dielectric 112ais also formed on the patterned metal layer 104 covered by a protective layer 106. Since the aspect ratio of the opening 103 with a remained dielectric layer 110 therein is lower than 3.5, the dielectric layer 112 can completely fill the openings 103 without voids or seams. That is, the reliability of the devices can be increased due to improved insulation between metal lines or devices. Next, a dielectric layer 114 having a thickness about 6000 Å, such as tetraethyl orthosilicate (TEOS) oxide, is formed over the patterned layer 104 and the dielectric layer 112 in the openings 103 by CVD. Thereafter, the dielectric layer 114 is planarized by CMP to finish the IMD.

[0023] Compared to the prior art, the invention effectively eliminates voids or seams in the IMD by reducing the aspect ratio of the gap or spacing through a doubling of the dielectric filling process. Therefore, higher reliability of the devices can be obtained through improved insulation between metal wires or devices.

[0024] The foregoing description has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.