Back up power embodied non-volatile memory device

[0002] This application claims the priority benefit of Taiwan application serial no.91206362, filed on May 7, 2002.

[0003] 1. Field of Invention

[0004] The present invention relates to a non-volatile memory device. More particularly, the present invention relates to a back up power embodied non-volatile memory device.

[0005] 2. Description of Related Art

[0006] Due to the popularization of electronic products, digital data is now routinely stored in memory devices for subsequent recall. To increase portability and facilitate easy access to stored digital data, detachable hard disks or optical disks have been used in the past. However, these conventional devices have several drawbacks. For example, a hard drive or an optical disk may store a large volume of data, however the intricate internal structure inside the hard drive is vulnerable to shock and impact. Although an optical disk is less vulnerable to impact, each optical disk has a fixed memory capacity and requires special read-out equipment such as a re-writable optical device to access and re-write data. In other words, both detachable hard drives and optical disks are easy to use but inconvenient to carry.

[0007] To increase portability of storage devices and limit the need for special devices, manufacturers have developed non-volatile memory devices such as flash memory. These non-volatile memory devices may connect with a host system through various types of external bus interfaces including, for example, the universal serial bus (USB) interface, RS232 interface and the 1394 interface. The non-volatile memory device not only carries out data transfer with the host system via the external bus, but also obtains power from the host system via the external bus as well. Portability and ease of connection with various host systems are the major reasons for the popularity of non-volatile memory devices. However, the non-volatile memory device must engage with the external bus of a host system to access and transfer data. Hence, any untimely unplugging of the device from the external bus may corrupt the data inside a file. If the memory device is unplugged during a file allocation table (FAT) refreshing operation, an incomplete FAT file is created due to the sudden power outage.

[0008] In brief, untimely unplugging of externally connected non-volatile memory devices may lead to possible deletion of transfer data or so damage the links in a FAT file that important data is forever lost.

[0009] Accordingly, one object of the present invention is to provide a back up power embodied non-volatile memory device. The device contains a back up internal power source that automatically cuts in when external power to the device suddenly terminates. The back up internal power source provides necessary power to download data already transferred to the memory into appropriate files and execute other necessary programs to render the file readable. In addition, if power to the non-volatile memory device is accidentally cut when a file allocation table (FAT) is being refreshed, the back up power also provides the necessary power for completing the refresh operation.

[0010] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a back up power embodied non-volatile memory device. The memory device includes a connection port, a power supply unit and a memory system. Host data and host power are provided to the non-volatile memory device through an external bus of the connection port. The memory system temporarily holds the data picked up by the connection port and subsequently transfers the data to the non-volatile memory. The power supply unit provides back up power to the memory system when power from the host system is cut. Hence, the temporarily stored data inside the memory system is ultimately transferred to the non-volatile memory to become readable data.

[0011] This invention also provides an alternative back up power embodied non-volatile memory device. The memory device includes a connection port, a buffer unit, a non-volatile memory, a battery and a memory controller. The connection port is connected to a host system. The host system provides host data and host power to the back up power embodied non-volatile memory device through the external bus on the connection port. The buffer unit temporarily holds data received by the connection port. The memory controller controls the writing of data from the buffer unit into the non-volatile memory and monitors the presence of host power. When host power is cut out in the middle of a data transfer operation, the battery provides back up power to complete the write, operation.

[0012] The connection port is an interface connection device suitable for interfacing with any one of the following interfaces, including the universal serial bus (USB) interface, the 1394 interface, the RS232 interface, the parallel transmission interface, the PCMCIA interface, the CF interface, the SD interface, the MMC interface and the memory stick interface.

[0013] The back up power embodied non-volatile memory device according to this invention is capable of detecting any change in the power provided by the host system. If host system power suddenly fails before the completion of a data transfer operation, internal back up power immediately cuts in to complete the writing of transmitted data into the non-volatile memory. Hence, the invention guarantees the writing of all received data into the non-volatile memory so that none of the data transmitted to the non-volatile memory device is lost.

[0014] In addition, the back up power within the non-volatile memory device also provides necessary power to complete any FAT refreshing operation if host power is cut prematurely. Hence, integrity of the stored data can be maintained.

[0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0016] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0017] FIG. 1 is a block diagram of a host/memory system according to one preferred embodiment of this invention;

[0018] FIG. 2 is a block diagram showing a circuit layout of a host/memory system according to another preferred embodiment of this invention;

[0019] FIG. 3A is a block diagram showing a circuit layout of the power supply unit 208ain FIG. 2;

[0020] FIG. 3B is a block diagram showing an alternative circuit layout of the power supply unit 208ain FIG. 2;

[0021] FIG. 4A is a block diagram showing a circuit layout of a host/memory system having a power regulator therein according to another preferred embodiment of this invention;

[0022] FIG. 4B is a block diagram showing a circuit layout of a host/memory system having a power regulator therein according to yet another preferred embodiment of this invention; and

[0023] FIG. 5 is an explosion view of the components constituting a complete non-volatile memory package manufactured according to one preferred embodiment of this invention.

[0024] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0025] FIG. 1 is a block diagram of a host/memory system according to one preferred embodiment of this invention. As shown in FIG. 1, the back up power embodied non-volatile memory device 10 includes a connection port 100, a power supply unit 110 and a memory system 120 (drawn not to scale). A host system 12 communicates with the connection port 100 through an external bus 115. Aside from providing data to the non-volatile memory device 10 via the external bus 15, the host system 12 also provides power to activate the non-volatile memory device 10. Here, the external bus includes any one of the following interfaces: the universal serial bus (USB) interface, the 1394 interface, the RS232 interface, the parallel transmission interface, the personal computer memory card (PCMCIA) interface, the flash card (CF) interface, the safety digital (SD) memory card interface, the multimedia memory card (MMC) interface and the memory stick interface. Correspondingly, the connection port 100 is an interface connection device capable of connecting with any one of the aforementioned interfaces.

[0026] Data picked up by the connection port 100 from the host system 12 is transferred to the memory system 120 via a data signaling line 102. Conversely, data read from the memory system 120 is transferred to the connection port 100 via the data signaling line 102. Thereafter, the data is transferred from the connection port 100 to the host system 12 via the external bus 115. Since reading data from the memory 120 will not cause any disruption of stored data, the subsequent discussion centers around writing data into the memory system 120.

[0027] In general, the process of writing data into the memory system 120 involves three stages. In the first stage, data is written into the memory in batches. After all the data is written into a particular file, information regarding the file is written to a file description block. Finally, the file allocation table is refreshed so that a user may access this particular file. Because a file register must retain information such as primary/secondary file name, attributes, reserve, time, date, indicator, size and other related data, losing any one of these items may lead to incomplete storage of the file. Moreover, file information is only registered after all relevant file data has been written into the memory system 120. Hence, if power to the non-volatile memory device 10 is cut before all file data is written in, the user has no way of accessing the previously written data within the file.

[0028] To resolve this problem, this invention introduces a power supply unit 110 inside the non-volatile memory device to serve as a back up in case of a power interruption. Using the power provided by the back up unit 110, the data already transferred into the memory system 120 is written into a file followed by modifying the content within the file register. In this way, even if power is cut half way through the transmission of a file, the non-volatile memory device 10 still can retain the already transferred portion of data.

[0029] If the power outage occurs while refreshing the file allocation table, content within the file allocation table may be corrupted and prevent the access of previously stored files. This problem is also resolved by introducing the power supply unit 110. The power supply unit 110 provides all the necessary power to finish the refreshing operation should a sudden power failure occur.

[0030] The memory system 120 may use a control signal line 112 to control the power supply unit 110. In general, the back up power unit 110 remains in a standby mode if the host system 12 is operating normally. However, the power provided by the host system may suddenly fail before the transfer of data into the memory system 120 or the update of the file allocation table is complete. In this case, the power supply unit 110 will step in and provide necessary power to complete all operations.

[0031] FIG. 2 is a block diagram showing a circuit layout of a host/memory system according to another preferred embodiment of this invention. As shown in FIG. 2, data (D) is transmitted to a connection port 220 inside a host system 22 through a data signal line 222 (an internal bus). The connection port 220 also picks up a host voltage through a pair of power lines 224 (+) and 226 (−). A connection port 200 inside a non-volatile memory device 20 picks up the host data and the host voltage through an external bus (including a data signal line 222aand a pair of power lines 224aand 226a). The host voltage is re-directed from the connection port 200 to a buffer unit 202, a memory controller 204 and a non-volatile memory unit 206 through a pair of power lines 234 and 236. The host voltage provides all the power for driving the buffer unit 202, the memory controller 204 and the non-volatile memory unit 206. Host data is transferred from the connection port 200 to the buffer unit 202 through a data signal line 232 for temporary storage. Thereafter, the memory controller 204 schedules the transfer of data from the buffer unit 202 to the non-volatile memory unit 206.

[0032] In this invention, the presence or absence of host power is monitored by a built-in firmware inside the memory controller 204 or a voltage feedback module 310 as shown in FIG. 3. The host power may even be monitored through the response of a battery 208. In the following, an operation mode that utilizes the response of a battery 208 is described with reference to FIG. 2.

[0033] As host power suddenly fails or the external bus is accidentally unplugged leading to a failure to supply necessary power for driving the non-volatile memory device 20, voltage on the pair of power lines 234 and 236 will gradually drop. When the voltage drops to a level below the voltage provided by the back up battery 208, the battery 208 cuts in as a power source substitute. The memory controller 204 utilizes the back up power to transfer the temporarily registered data inside the buffer unit 202 to the non-volatile memory unit 206. On completion of data transfer, file registers are updated and the file allocation table is refreshed.

[0034] Aside from directly responding to the battery 208, the battery 208 and the built-in firmware inside the memory controller 204 may also be used together for detecting any voltage variation. After directing the transfer of all data from the buffer unit 202 to the non-volatile memory unit 206 and the updating of file registers and file allocation table, the memory controller 204 sends signals via control signal lines 252 and 254 to stop the buffer unit 202, the memory controller 204 and the non-volatile memory unit 206 from receiving any power through the power lines 234 and 236 so that some back up power is saved. Note that more energy is saved if the power supply line from the battery 208 is directly cut as shown in FIG. 3B. Only an additional switch 320 controlled by the memory controller 204 at the output circuit of the battery 208 is required.

[0035] FIG. 3A is a block diagram showing a circuit layout of the power supply unit 208ain FIG. 2. As shown in FIG. 3A, the power supply unit 208aincludes a voltage feedback module 310 for detecting the presence of host power. Note that the battery 208 is charged via a charging module 300 that consumes host power. However, the charging module 300 is not an essential component in this invention as indicated in FIG. 2.

[0036] The charging module in FIG. 3A further includes a voltage protection module 302 that protects the charging module against a sudden power surge or a heightened voltage. During normal operation, the host power will charge up the battery 208 through the charging module 300. The voltage feedback circuit 310 is able to detect any drop in voltage provided by the host power through the change in potential across the power lines 234 and 236. The battery 208 immediately kicks in and provides back up power to the power lines 234 and 236. Since subsequent operations are identical to the ones in FIGS. 2 and 3B, detailed description is omitted.

[0037] In general, external buses transmit a voltage in the 5V range. The components inside the non-volatile memory device 20 such as the memory system 120, the buffer unit 202, the memory controller 204 and the non-volatile memory unit 206 may operate without any voltage regulator since they operate at 5V. However, anyone familiar with the technology may add a voltage regulator so that memory devices operating at other voltage ranges may also be used.

[0038] FIGS. 4A and 4B are block diagrams showing two circuit layouts of a host/memory system that incorporates a power regulator. In FIGS. 4A and 4B, components similar to the ones in FIG. 2 are labeled identically. To simplify explanation, the buffer unit 202, the memory controller 204 and the non-volatile memory unit 206 in FIG. 2 are combined together to form a memory system just like the memory system 120 in FIG. 1. In FIG. 4A, host power received by the connection port 200 is transmitted to a power regulator 270a. The power regulator 270aconverts the host power into a voltage suitable for operating internal devices such as the memory system 120 or the power supply unit 208aand then transmits the voltage to these devices. In FIG. 4B, host power received by the connection port 200 is transmitted to a power regulator 270band a power supply unit 208b. The power regulator 270bconverts the host power into a voltage suitable for operation of the memory system 120. The power supply device 208bremains in a standby mode and provides back up power to the memory system through a pair of power lines 280 and 282 when necessary.

[0039] Furthermore, anyone familiar with the aforementioned design concept may tailor the circuit design to suit a particular need. For example, the power provided by the supply unit 208bin FIG. 4B may pass through the power regulator 270bfor conversion into a suitable voltage before providing necessary power to the memory system 120. Therefore, the aforementioned embodiment should be regarded as an example rather than a limitation of the range of application in this invention. Moreover, in the embodiment having a power regulator, the memory system and the power supply unit may work at a voltage different from the host power voltage transmitted through the external bus. The design may change according to cost and other circuit considerations.

[0040] In this invention, the back up power is preferably provided by a re-chargeable battery. Yet, a non-chargeable battery such as a button battery may similarly be applied to this invention. In addition, a circuit that can temporarily store energy and release energy in a voltage drop may be employed also. Circuits belonging to such a category, including the capacitor circuit, the capacitor/inductor circuit and the capacitor/inductor/resistor circuit, may serve as a principle component inside the power supply unit.

[0041] Table 1 lists major advantages of a non-volatile memory device fabricated according to this invention and compared with the device fabricated according to the conventional techniques.

[0042] FIG. 5 is an explosion view of the components constituting a complete non-volatile memory package manufactured according to one preferred embodiment of this invention. Through the component diagram, the non-volatile memory device is easily manufactured.

[0043] In summary, one major aspect of this invention is the provision of a back up power supply inside the non-volatile memory device so that data already transmitted to the device may be transferred to the non-volatile memory unit. Hence, this invention guarantees the transfer of already transmitted data into the non-volatile memory unit so that none of the transmitted data is lost by sudden power failure.

[0044] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.