Method for forming multiple structures in a semiconductor device

[0002] The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.

[0003] The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.

[0004] For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.

[0005] Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.

[0006] Implementations consistent with the present invention provide methodology for forming multiple fins for use in a FinFET device. The fins, consistent with the present invention, may be formed with a small pitch.

[0007] Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.

[0008] According to the present invention, the foregoing and other advantages are achieved in part by a method of forming multiple fins in a FinFET device. The method includes depositing a dielectric layer over a silicon on insulator (SOI) wafer, where the SOI wafer includes a conductive layer on an insulating layer. The method also includes forming a resist mask over portions of the dielectric layer and etching a trench in a portion of the dielectric layer not covered by the resist mask, where the trench has two side walls. The method further includes forming spacers adjacent the two sidewalls of the trench, etching the dielectric layer to form dielectric structures located below the spacers, etching the conductive layer to form the fins and removing the spacers and the dielectric structures.

[0009] According to another aspect of the invention, a method of manufacturing a semiconductor device is provided. The method includes depositing a film over a conductive layer, where the conductive layer is used to form a plurality of fin structures. The method also includes etching at least one trench in a portion of the film, where a first trench has two side walls. The method further includes forming spacers adjacent the two sidewalls of the first trench and etching the film, where the etching terminates on the conductive layer. The method also includes etching the conductive layer to form the fin structures, forming a source region and a drain region, depositing a gate material over the fin structures and patterning and etching the gate material to form at least one gate electrode.

[0010] Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.

[0011] Reference is made to the attached drawings, wherein elements having the same reference number designation may represent like elements throughout.

[0012] FIGS. 1-7 are cross-sectional views illustrating exemplary processing for forming fins in accordance with an embodiment of the present invention.

[0013] FIG. 8 is a top view illustrating an exemplary double gate device formed in accordance with an exemplary embodiment of the present invention.

[0014] FIGS. 9A and 9B are cross-sections illustrating the formation of asymmetrical source/drain regions in accordance with another embodiment of the present invention.

[0015] FIG. 10 is a cross-section illustrating the formation of a gate in accordance with another embodiment of the present invention.

[0016] The following detailed description of the invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents.

[0017] Implementations consistent with the present invention provide double gate FinFET devices with multiple fins and methods of manufacturing such devices. The fins formed in accordance with the present invention may have a small pitch (i.e., distance between the fins) based on the particular device requirements.

[0018] FIG. 1 illustrates the cross-section of a semiconductor device 100 formed in accordance with an embodiment of the present invention. Referring to FIG. 1, semiconductor device 100 may include a silicon on insulator (SOI) structure that includes a silicon substrate 110, a buried oxide layer 120 and a silicon layer 130 on the buried oxide layer 120. Buried oxide layer 120 and silicon layer 130 may be formed on substrate 110 in a conventional manner.

[0019] In an exemplary implementation, buried oxide layer 120 may include a silicon oxide, such as SiO₂, and may have a thickness ranging from about 1500 Å to about 3000 Å. Silicon layer 130 may include monocrystalline or polycrystalline silicon having a thickness ranging from about 200 Å to about 1000 Å. Silicon layer 130 is used to form multiple active lines or fins for a double gate transistor device, as described in more detail below.

[0020] In alternative implementations consistent with the present invention, substrate 110 and layer 130 may comprise other semiconducting materials, such as germanium, or combinations of semiconducting materials, such as silicon-germanium. Buried oxide layer 120 may also include other dielectric materials.

[0021] A dielectric layer 140, such as a silicon oxide layer, may be formed over silicon layer 130 to act as a protective mask during subsequent etching processes. In an exemplary implementation, dielectric layer 140 may comprise SiO₂and may be deposited using chemical vapor deposition (CVD) to a thickness ranging from about 300 Å to about 1000 Å. In other implementations consistent with the present invention, layer 140 may consist of other films or materials that may be deposited or grown, including conductive materials or other non-conductive materials.

[0022] Next, a photoresist material may be deposited and patterned to form a photoresist mask 150, as illustrated in FIG. 1. The photoresist may be deposited and patterned in any conventional manner. The dielectric layer 140 and photoresist mask 150 may be used to facilitate the formation of a number of active lines, as described in more detail below.

[0023] Semiconductor device 100 may then be etched. In an exemplary implementation, dielectric layer 140 may be etched to form trench 210, as illustrated in FIG. 2. Referring to FIG. 2, the cross-sectional width of the trench 210 is represented by L. In an exemplary implementation, L may range from about 1000 Å to about 3000 Å. It should be understood, however, that the particular value of L may vary based on the particular circuit requirements associated with the fins in the FinFET device that will be formed. In addition, the depth of trench 210 from the top surface of dielectric layer 140 may range from, for example, about 300 Å to about 1000 Å.

[0024] After the trench 210 has been formed, a material, such as polysilicon, may be deposited and etched in a conventional manner to form trench spacers 310, as illustrated in FIG. 3. The trench spacers 310 may be used as a hard mask to facilitate the formation of fins, as described in more detail below. The width of trench spacers 310 is illustrated in FIG. 3 as “S.” In an exemplary implementation, S may range from about 100 Å to about 500 Å. However, the particular width of trench spacers 310 (and the value of S) may be set based on the desired pitch associated with the subsequently formed fins.

[0025] After the formation of trench spacers 310, dielectric layer 140 may be etched, with the etching terminating on silicon layer 130 as illustrated in FIG. 4. Referring to FIG. 4, the trench spacers 310 protect the material in dielectric layer 140 located below the trench spacers 310 from being etched, resulting in dielectric structures 410.

[0026] After the dielectric layer 140 is etched to form dielectric structures 410, the trench spacers 310 may be removed, as illustrated in FIG. 5. Referring to FIG. 5, the center-to-center distance between the dielectric structures 410, referred to as the pitch, is represented by P. In the exemplary implementation described above, the value of P is based on both the width of trench 210 (“L” in FIG. 2) and the width of trench spacers 310 (“S” in FIG. 3). More particularly, the pitch P is equal to L minus S. That is, P=L−S. The particular value of P that may be obtained in accordance with the present invention may be very small, e.g., as small as about 500 Å. However, as discussed above, it should be understood that the particular value of P may vary based on the particular circuit requirements associated with the fins and double gate device that will be formed.

[0027] Silicon layer 130 may then be etched, with the etching terminating on buried oxide layer 120, as illustrated in FIG. 6. During the etching, dielectric structures 410 act as a mask to protect the silicon material in silicon layer 130 located below the dielectric structures 410 from being etched, resulting in fin structures 610 illustrated in FIG. 6.

[0028] Dielectric structures 410 may then be removed, for example, via a planarization process, resulting in fin structures 610 illustrated in FIG. 7. Fin structures 610 may be used as fins in a FinFET device or as active lines in other devices. Advantageously, the pitch P of the fins formed in accordance with the present invention may be very small.

[0029] After the fins 610 are formed, a protective dielectric layer, such as a silicon nitride or silicon oxide may be formed on the top surface of fins 610, followed by the formation of a gate dielectric on the side surfaces of the fins 610. Source/drain regions may then be formed at the respective ends of the fins 610, followed by formation of one or more gates. For example, a silicon layer, germanium layer, combinations of silicon and germanium or various metals may be used as the gate material. The gate material may then be patterned and etched to form the gate electrodes. For example, FIG. 8 illustrates a top view of semiconductor device 100 consistent with the present invention after the source/drain regions and gate electrodes are formed. As illustrated, semiconductor device 100 includes a double gate structure with fins 610, source drain regions 810 and 820, and gate electrodes 830 and 840.

[0030] The source/drain regions 810 and 820 may then be doped with n-type or p-type impurities based on the particular end device requirements. In addition, sidewall spacers may optionally be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements. Activation annealing may then be performed to activate the source/drain regions 810 and 820.

[0031] The present invention has been described above as forming two fins. The methodology of the present invention, however, may be used to form any number of fins, based on the particular circuit requirements. For example, if more than two fins are required, multiple trenches may be formed in dielectric layer 140 (FIG. 2). The processing for forming the fins may then proceed as described above with respect to FIGS. 3-7. In this case, the distance between neighboring trenches may be set to a predetermined distance so that the fin subsequently formed below one of the trenches is located the desired distance from another fin subsequently formed below a neighboring trench.

[0032] Thus, in accordance with the present invention, a FinFET device may be formed with multiple fins having a small pitch. Advantageously, the methodology for forming fins in accordance with the present invention allows multiple fins to be formed more closely together than that realized in conventional processing. Having multiple fins enables the resulting semiconductor device to increase the channel width per device as compared to a single fin FinFET device. In addition, by forming the multiple fins more closely together, the present invention is able to provide more fins in a smaller area than that obtained using conventional processes. Therefore, the present invention provides increased flexibility and can be easily integrated into conventional processing.

[0033] In other embodiments of the present invention, FinFETs with asymmetrical source/drain extensions may be formed. For example, FIG. 9A illustrates a cross-sectional view of semiconductor device 900 that includes gate 910, source region 920 and drain region 930. The semiconductor device 900 may be a FinFET device. The fin(s) in device 900, however, are not shown for simplicity.

[0034] In any event, after the fin(s), source/drain regions 920 and 930 and the gate 910 are formed, impurities may be ion implanted into the source/drain regions 920 and 930. In an exemplary implementation, a tilt angle implant process may be performed to dope the source and drain regions 920/930 as indicated by the arrows in FIG. 9A. After the tilt angle implant, the source region 920 and drain region 930 may be asymmetrical with respect to gate 910, as illustrated in FIG. 9B. That is, the source region 920 may extend laterally below gate 910, while drain region 930 may not extend laterally below gate 910, as illustrated in FIG. 9B. In this manner, the FinFET 900 may include asymmetrical source/drain extension regions.

[0035] In another embodiment of the present invention, a FinFET may be doped to reduce resistance. For example, FIG. 10 illustrates the cross-section of semiconductor device 1000 that includes a buried oxide layer 1010 that may be formed on a substrate. A fin 1020, comprising silicon, and a gate dielectric 1030 may be formed on the top surface and sidewalls of fin 1020 in a conventional manner, as illustrated in FIG. 10. Next, a polysilicon layer 1040 may be deposited, as illustrated in FIG. 10. Polysilicon layer 1040 may then be doped with n-type or p-type impurities. After the doping, a second polysilicon layer 1050 may be deposited, as illustrated in FIG. 10. Polysilicon layer 1050 may then be doped with n-type or p-type impurities. Polysilicon layers 1040 and 1050 may then be patterned and etched to form one or more gates. The resulting semiconductor device 1000 experiences reduced poly resistance as compared to conventional devices.

[0036] In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, the present invention can be practiced without resorting to the specific details set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention.

[0037] The dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the present invention can be deposited by conventional deposition techniques. For example, metallization techniques, such as various types of CVD processes, including low pressure CVD (LPCVD) and enhanced CVD (ECVD) can be employed.

[0038] The present invention is applicable in the manufacturing of double-gate semiconductor devices and particularly in FinFET devices with design features of 100 nm and below. The present invention is applicable to the formation of any of various types of semiconductor devices, and hence, details have not been set forth in order to avoid obscuring the thrust of the present invention. In practicing the present invention, conventional photolithographic and etching techniques are employed and, hence, the details of such techniques have not been set forth herein in detail.

[0039] Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein.