Multi-bit continuous time sigma-delta ADC

[0002] The present invention generally relates to the field of analog-to-digital converters (“ADC”). More specifically, the present invention relates to multi-bit quantizers in sigma-delta modulators.

[0003] A primary advantage of continuous-time sigma-delta ADC devices over discrete-time multi-bit sigma-delta ADC devices is reduced power dissipation. At the same time, a primary advantage of discrete-time multi-bit sigma-delta ADC devices over single-bit sigma-delta ADC devices is the increased resolution that can be achieved at lower sampling rates. As such, there is motivation in the art to apply multi-bit quantizer technology to a continuous-time sigma-delta ADC structure. However, multi-bit quantizer technology can be expensive in terms of power consumption and circuit area when applied to sigma-delta ADC devices. The reason for this is that multi-bit quantizers are made up of banks of low offset comparators, while a single-bit sigma delta ADC device requires only a single comparator with a non-critical offset specification. The power penalty is most significant in the context of continuous-time sigma-delta ADC devices, because the primary motivation for implementing a continuous-time sigma-delta ADC device is to reduce power.

[0004] The present invention advances the art by a contribution of a novel multi-bit continuous-time sigma-delta ADC structure that addresses the aforementioned power penalty associated with a multi-bit quantizer.

[0005] The present invention is an analog-to-digital converter comprising a summing module, a voltage controlled oscillating module, a dynamic element matching module and a feedback module. In a base form, the summing module is operated to provide an analog summation signal indicative of a summation of an analog input signal and an analog feedback signal. The voltage controlled oscillating module is operated to provide a first set of bits as a digital representation of the analog summation signal. The dynamic element matching module is operated to provide a second set of bits as a digital representation of a periodic sampling of the first set of bits. And, the feedback module is operated to provide the analog feedback signal as an analog representation of the second set of bits.

[0006] The foregoing form as well as other forms, features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.

[0007] FIG. 1 illustrates an ADC of present invention;

[0008] FIG. 2 illustrates a first embodiment of the FIG. 1 ADC;

[0009] FIG. 3 illustrates a second embodiment of the FIG. 1 ADC; and

[0010] FIG. 4 illustrates a TABLE 1 listing an exemplary operation of FIG. 2 ADC.

[0011] FIG. 1 illustrates an ADC 10 of the present invention. ADC 10 comprises a summing module 20, a voltage controlled oscillating module 30 (“VCO module 30”) dynamic element matching module 40 (“DEM module 40”), and a feedback module 50. Summing module 20 receives an analog input signal X, and is in communication with the feedback module 50 to thereby receive an analog feedback signal Z. The VCO module 30 is in communication with summing module 20 to thereby receive an analog summation signal XZ indicative of a summation of the analog input signal X and the analog feedback signal Z.

[0012] The DEM module 40 is in communication with the VCO module 30 to thereby receive a set of bits B₁-B_Nserving as a digital representation of the analog summation signal XZ. The DEM module 40 also receives a sampling clock CLK. The feedback module 50 is in communication with the DEM module 40 to thereby receive a set of sample bits SB₁-SB_Nserving as a digital representation of a periodic sampling of the bits B₁-B_Nin accordance with the sampling clock CLK. The sample bits SB₁-SB_Nform a digital output signal Y composed of N bits. Alternatively, the bits B₁-B_Nform the digital output signal Y composed of N bits.

[0013] Each component of ADC 10 may employ hardware (analog or digital), software, or any combination of hardware and software. Additionally, the communication between the various components of ADC 10 can be accomplished in numerous ways (e.g., electrically, optically, magnetically, and/or acoustically). The number of embodiments of ADC 10 is therefore essentially limitless. FIGS. 2 and 3 illustrate an ADC 11 and an ADC 12, respectively, as preferred embodiments of the ADC 10.

[0014] As illustrated in FIG. 2, the ADC 11 includes a conventional summer 21 and a conventional filter 22 collectively constituting one embodiment of summing module 20 (FIG. 1). The summer 21 sums the analog input signal X and the analog feedback signal Z to thereby provide the analog summation signal XZ. The filter 22 filters the analog summation signal XZ.

[0015] The ADC 11 further includes a conventional voltage controlled oscillator 31 and a feedback shift register 32 collectively constituting one embodiment of VCO module 30 (FIG. 1). The voltage controlled oscillator 31 generates an oscillating signal OS as a function of a magnitude of the analog summation signal XZ. The feedback shift register 32 has a Nth quantity of conventional bi-stable latching devices (“BLD”), where 1≦N≦∞. Each BLD has a clock input for receiving the oscillating signal OS. A data output of each BLD is communicated to a data input of a succeeding BLD with the exception of a data output of the Nth BLD being communicated to a data input of an inverter 33 and a data output of the inverter 33 being communicated to a data input of the first BLD. The data outputs of the BLD are the bits B₁-B_N, respectively, which are a function of a frequency of the oscillating signal OS.

[0016] The ADC 11 further includes a row 41 of an Nth quantity of BLD, a row 42 of an Nth quantity of BLD, and a row 43 of an Nth quantity conventional summers collectively constituting one embodiment of DEM module 40 (FIG. 1), where 1≦N≦∞. Each BLD of row 41 has data input in communication with a data output of a corresponding BLD of register 32, and a clock input for receiving the sampling clock CLK. Each BLD of row 42 has data input in communication with a data output of a corresponding BLD of row 41, and a clock input for receiving the sampling clock CLK. Each summer of row 43 receives the data outputs of a corresponding BLD of row 41 and a corresponding BLD of row 42. The data outputs of the summers of row 43 are sample bits SB₁-SB_N, respectively, which are a function of the sampling clock CLK and the bits B₁-B_N.

[0017] The ADC 11 further includes a digital-to-analog converter 51 (“DAC 51”) constituting one embodiment of feedback module 50 (FIG. 1). The DAC 51 has an input in communication with each summer of row 43 to thereby input the sample bits SB₁-SB_Nand an output in communication with the summer 21 to thereby provide the analog feedback signal Z to summer 21.

[0018] As illustrated in FIG. 3, the ADC 12 is an alternative version of the ADC 11 that includes a voltage controlled ring oscillator in lieu of the VCO 31 (FIG. 2) and the feedback shift register (FIG. 2). The voltage controlled ring oscillator includes a row 34 of an Nth quantity of conventional inverters and a row 35 of an Nth quantity of BLD (e.g., toggle flip-flops), N can be any odd number between one and infinity. Each inverter of row 34 has a supply input for receiving the analog summation signal XZ. A data output of each inverter of row 34 is communicated to a data input of a succeeding inverter with the exception of a data output of the Nth inverter being communicated to a data input of the first inverter. Each BLD of row 35 has a clock input in communication with a data output of a corresponding inverter of row 34, and a data output in communication with a data input of a corresponding BLD of row 41. The corresponding bits B₁-B_Nare a function of a magnitude of the analog summation signal XZ.

[0019] An operation of ADC 11 (FIG. 2) where N=8 will now be described herein. In operation, the analog summation signal XZ applied to the input of the VCO 31 will deviate above and below its nominal value. When the analog summation signal XZ is at its nominal value, the oscillating signal OS will have an operating frequency 4× the sampling frequency of the sampling clock CLK. When the analog summation signal XZ is greater than its nominal value, the operating frequency of the oscillating signal OS will increase to a value greater than 4× the sampling frequency of the sampling clock CLK. When the analog summation signal XZ is less than its nominal value, the operating frequency of the oscillating signal OS will decrease to a value less than 4× the sampling frequency of the sampling clock CLK.

[0020] To facilitate a further understanding of the operation of ADC 11, FIG. 4 illustrates a TABLE 1 based on N=8, and a frequency of sampling clock CLK being nominally ¼^ththe frequency of the oscillating signal OS. In TABLE 1, an initial state of the bits B₁-B_Nand sample bits SB₁-SB_Nis 00000000. Each time the feedback shift register 32 is clocked by the oscillating signal OS during clock cycles 1-8, the state of feedback shift register 32 changes with each successive bit becoming a logical 1 until feedback shift register 32 state becomes 11111111 at clock cycle 8. After that, clock cycles 9-16 cause successive bits of feedback shift register 32 to become a logical 0 until feedback shift register 32 returns to its initial state of 00000000 at clock cycle 16. This sequence is repeated for clock cycles 17-32 and so on and so on. When the operating frequency of the oscillating signal OS equals its nominal frequency, then half of the bits B₁-B_Nwill change state within a single clock cycle of the sampling clock CLK as indicated by clock cycles 1, 2, 3 and 6 of the sampling clock CLK illustrated in TABLE 1. When operating frequency of the oscillating signal OS is less than its nominal frequency, then less than half of the bits B₁-B_Nwill change state as indicated by clock cycles 4 and 5 of the sampling clock CLK illustrated in TABLE 1. Conversely, when operating frequency of the oscillating signal OS is greater than its nominal frequency, then more than half of the bits B₁-B_Nwill change state as indicated by clock cycles 7 and 8 of the sampling clock CLK illustrated in TABLE 1.

[0021] At the end of a sampling clock period of the sampling clock CLK, the current state of the bits B₁-B_Nis stored in the row 41 of BLD and the previous state of the bits B₁-B_Nis stored in the row 42 of BLD. The row 43 of summers compares the current state and the previous state of bits B₁-B_Nwhereby an output of the row 43 of summers consists of an N bit word. Each digits of the N bit word having a value of logical 1 indicates the number of bits B₁-B_Nthat changed state within the last sampling clock period of the sampling clock CLK. In TABLE 1, eight (8) clock cycles of the sampling clock CLK are illustrated.

[0022] At the end of the clock cycle 1 of the sampling clock CLK, bits B₁-B₄have changed state whereby the value of bits B₁-B₈is 11110000 and the value of sample bits SB₁-SB₈is 11110000.

[0023] At the end of the clock cycle 2 of the sampling clock CLK, bits B₅-B₈have changed state whereby the value of bits B₁-B₈is 11111111 and the value of sample bits SB₁-SB₈is 00001111.

[0024] At the end of the clock cycle 3 of the sampling clock CLK, bits B₁-B₄have changed state whereby the value of bits B₁-B₈is 00001111 and the value of sample bits SB₁-SB₈is 11110000.

[0025] At the end of the clock cycle 4 of the sampling clock CLK, bits B₅and B₆have changed state whereby the value of bits B₁-B₈is 00000011 and the value of sample bits SB₁-SB₈is 00001100.

[0026] At the end of the clock cycle 5 of the sampling clock CLK, bits B₇and B₈have changed state whereby the value of bits B₁-B₈is 00000000 and the value of sample bits SB₁-SB₈is 00000011.

[0027] At the end of the clock cycle 6 of the sampling clock CLK, bits B₁-B₄have changed state whereby the value of bits B₁-B₈is 11110000 and the value of sample bits SB₁-SB₈is 11110000.

[0028] At the end of the clock cycle 7 of the sampling clock CLK, bit B₁, bit B₂, and bits B₅-B₈have changed state whereby the value of bits B₁-B₈is 00111111 and the value of sample bits SB₁-SB₈is 11001111.

[0029] At the end of the clock cycle 8 of the sampling clock CLK, bits B₃-B₈have changed state whereby the value of bits B₁-B₈is 00000000 and the value of sample bits SB₁-SB₈is 0011111.

[0030] From the preceding description of the exemplary operation of ADC 11, those having ordinary skill in the art will appreciate an operation of ADC 12.

[0031] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the mathematical principles of linearity and superposition may enable the re-ordering of certain steps of the described embodiments, or may enable additional specific embodiments having essentially the same function, and such variations are within the scope of the present invention. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.