Trimming of a two point phase modulator

[0002] The invention relates to all areas where two-point phase modulation is used. In particular it relates to a Sigma Delta controlled fractional-N PLL modulator with an extra modulation input.

[0003] A Sigma Delta controlled fractional-N PLL (phase-locked loop) is often used in a radio system for generating spurious-free local oscillator (LO)-frequencies and to allow faster frequency jumps. A block diagram of this is shown in FIG. 1 By controlling a frequency divider 8 ratio with a sigma-delta modulator 9, modulation with a constant envelope can be generated. By using these properties of the fractional N PLL 15, compact radio architectures for constant envelope systems e.g., Global Sysem for Mobile Communications (GSM) or DCS could be developed. This also means that a complete radio could be integrated into a single ASIC (application specific integrated circuit).

[0004] Since constant envelope systems aren't bandwidth efficient, some proposed systems also use amplitude modulation. Examples of these systems are EDGE (enhanced data GSM environment) and WCDMA (wideband code division multiple access).

[0005] If the modulating signal is divided into a phase part and an amplitude part, the phase part could be introduced in the fractional N PLL and the amplitude part could be added (effectively multiplied) in an amplifier after the PLL. In this way, switching blocks could be used throughout the complete modulator, which is very power efficient.

[0006] But when dividing the signal into amplitude and phase part, the bandwidth of the phase and amplitude part become much wider than the combined signal. Since the amplitude and phase part are combined in a multiplier after the PLL 15 this imposes stringent requirements on dynamic range and bandwidth of the amplitude and phase part and also on the timing between the amplitude and phase part.

[0007] For the phase part this means that the usable modulation bandwidth of the fractional N PLL is not wide enough. This bandwidth is limited by PLL noise, sigma-delta noise and matching issues.

[0008] One way to get around this limitation is to add a second modulation point, i.e., two-point modulation. By also inserting the modulation signal after the PLL loop filter, there is no trade-off between PLL loop bandwidth and modulation bandwidth.

[0009] Referring now to the drawings, in FIG. 1, the instantaneous frequency first is inserted at two points 10, 12 in the modulator and the amplitude part A(S) is inserted at the PA (power amplifier) 14.

[0010] The transfer function from the modulation inputs to the output of the VCO (voltage controlled oscillator) 16 can be derived as ${\theta }_{\mathrm{out},\mathrm{VCO}}\left(s\right)=\frac{f_{\mathrm{inst}}\left(s\right)}{\mathrm{Ns}}\frac{K_{\mathrm{phd}}\frac{K_{\mathrm{vco}}}{s}{H}_{\mathrm{LP}}\left(s\right)}{1+K_{\mathrm{phd}}\frac{K_{\mathrm{vco}}}{s}{H}_{\mathrm{LP}}\left(s\right)/N}+\frac{f_{\mathrm{inst}}\left(s\right)}{K_{\mathrm{vco}}^{\prime }}\frac{\frac{K_{\mathrm{vco}}}{s}}{1+K_{\mathrm{phd}}\frac{K_{\mathrm{vco}}}{s}{H}_{\mathrm{LP}}\left(s\right)/N}=f_{\mathrm{inst}}\frac{\left(s\right)}{s}\frac{\frac{K_{\mathrm{vco}}}{K_{\mathrm{vco}}^{\prime }}+K_{\mathrm{phd}}\frac{K_{\mathrm{vco}}}{s}{H}_{\mathrm{LP}}\left(s\right)/N}{1+K_{\mathrm{phd}}\frac{K_{\mathrm{vco}}}{s}{H}_{\mathrm{LP}}\left(s\right)/N}=\left[\mathrm{If},K_{\mathrm{vco}}=K_{\mathrm{vco}}^{\prime }\right]=f_{\mathrm{inst}}\frac{\left(s\right)}{s}$

[0011] This is independent of PLL loop bandwidth.

[0012] This modulation scheme is included in patent document WO 99/07066, “Frequency synthesizer systems and methods for three point modulation with a DC-response.”

[0013] However, a new unknown is introduced, namely, the estimation of the VCO gain. If the estimation of the VCO gain is wrong we get spectral growth and break the ACPR (adjacent channel power ratio) requirement of the system.

[0014] In a RF-ASIC with onboard VCO the VCO-gain is dependent on the size of the inductor, the output frequency and the bias point of the varactor. A standard VCO configuration is depicted in FIG. 2.

[0015] In FIG. 2, there are inductors L1, L2 (20, 22) and a parasitic capacitance (24) Cpar, a combination of all capacitor loading and all parasitics as seen from the resonator. Then there is the tuning network, consisting of Cc 26, 28 (coupling capacitors to couple the varactors loosely to the resonator), Cv 30, 32 (the actual varactors) and Rgnd 34, 36 (ground reference for the varactors). The bottom part shows the active components (e.g., transistors 35, 40) responsive for sustaining the oscillation.

[0016] The tuning sensitivity of the VCO is derived by taking the derivative of the output frequency with respect to the tuning voltage. $w_o=\frac{1}{\sqrt{L_{\mathrm{tot}}{C}_{\mathrm{tot}}}};$ $\frac{\partial w_o}{\partial V_{\mathrm{tune}}}=\frac{\partial w_o}{\partial C_{\mathrm{tot}}}\frac{\partial C_{\mathrm{tot}}}{\partial C_v}\frac{\partial C_v}{\partial V_{\mathrm{tune}}}=-\frac{L_{\mathrm{tot}}}{2{\left(L_{\mathrm{tot}}{C}_{\mathrm{tot}}\right)}^{3/2}}\frac{1}{2}{\left(\frac{C_c}{C_c+C_V}\right)}^2\frac{\partial C_V}{\partial V_{\mathrm{tune}}}=-\frac{L_{\mathrm{tot}}{w}_o^3}{2}\frac{1}{2}{\left(\frac{C_c}{C_c+C_V}\right)}^2\frac{\partial C_V}{\partial V_{\mathrm{tune}}}$

[0017] The tuning sensitivity is dependent on many parameters.

[0018] The VCO on-chip inductor (e.g., L1, L2) is a large metal structure and is inherently stable.

[0019] The varactor capacitance and the slope of the varactor capacitance are dependent on the tuning voltage. The tuning voltage is dependent on the VCO center frequency.

[0020] By making a careful design keeping the above equation in mind, the total VCO gain variation could be reduced, but usually other parameters limit the flexibility.

[0021] A table with measured VCO gain versus frequency could compensate the variation. However, the main problem with this solution is that when manufacturing these circuits, the parasitic capacitance (Cpar) of the resonator varies and a different tuning voltage is required to get the correct output frequency. The VCO gain could vary as much as 50% from one sample to the other. This means that the VCO gain would have to be measured for each VCO chip to get stable performance.

[0022] In WO 99/07066 the author describes a different circuit configuration, where the VCO has two separate inputs, one for the PLL tuning voltage and one for the modulation input. A circuit configuration for this is depicted in FIG. 3.

[0023] In FIG. 3, a separate tuning input V mod 50 is added for modulation. This input is similar to the original tune input V tune 42 but it has a DC-voltage applied to set the operating point of the varactor.

[0024] Using this modified VCO (FIG. 3) means that the varactors can be biased at a suitable DC-level. Also the input bandwidth and tuning sensitivity can be optimized for modulation. If the DC-level applied to the varactors is constant, the only thing varying in the previous formula is the center frequency. This solution is independent of parasitic capacitor variations, since this is compensated in the tuning voltage.

[0025] This means that the VCO-gain variation from sample to sample is mainly dependent on spread in the varactor at the specific bias point and spread in the coupling capacitor. By careful design this could be less than 10% (mainly by choosing large size components).

[0026] However, for future systems with more complex modulation schemes (for example 16 QAM) the requirement of VCO-gain estimations will be higher using this modulation scheme. Therefore, some kind of automatic calibration is necessary. Also, using automatic calibration would secure a higher yield and more stable operation.

[0027] The present invention overcomes the above limitations by means of a frequency synthesizer generating an output frequency. The frequency synthesizer comprises a controlled oscillator having a tuning input which is responsive to a frequency control input signal to generate an output frequency, and having a feed back loop. The frequency synthesizer further comprises a compensation circuit for compensating gain variation of the controlled oscillator outside of the feedback loop.

[0028] The feed back loop further comprises a phase comparator wherein the phase comparator is responsive to a reference frequency signal and a feedback signal for producing an error output signal. The phase comparator comprises a first charge pump and a second charge pump. The first charge pump receives the reference frequency signal and the second charge pump receives a divided signal. The first and second charge pumps produce first and second output currents, wherein the first output current is used as an error signal and the second output current is used for trimming a gain estimation of the controlled oscillator.

[0029] In the drawings:

[0030] FIG. 1 is a block diagram showing two-point modulation;

[0031] FIG. 2 is a simplified schematic of a typical differential, on-chip VCO;

[0032] FIG. 3 is a simplified schematic of a modified VCO optimized for modulation;

[0033] FIG. 4 is a block diagram showing a modified phase detector with an extra charge pump;

[0034] FIG. 5 is a block diagram of a modulator using two-point phase modulation and feedback for setting the VCO gain estimation;

[0035] FIG. 6 is a block diagram of another embodiment of a modulator using two-point phase modulation and feedback for setting the VCO gain estimation; and

[0036] FIG. 7 is a block diagram of a modulator similar to FIG. 6, modified to measure the loop voltage instead of the chargepump output.

[0037] If the modified VCO (FIG. 3) is used, an estimation of the VCO-gain variation could be added by changing the DC-level at the modulation input varactor. By applying the estimation after the DAC (that is, the DAC used for applying modulation at the VCO input), the dynamic range requirement of this DAC is unaffected. These general considerations apply for the below-described feedback systems as well.

[0038] The modulation signal applied at the VCO input is suppressed by the PLL. Therefore, a counteracting output is produced from the phase detector 25. Now if the same modulation signal is applied at the prescaler input, the phase detector output is zero. By using the block diagram of FIG. 1, the transfer function to the chargepump (PFD) 25 output is derived. ${\theta }_{\mathrm{out}.\mathrm{PFD}}\left(s\right)=f_{\mathrm{inst}}\left(s\right)\frac{K_{\mathrm{vco}}^{\prime }-K_{\mathrm{vco}}}{K_{\mathrm{vco}}^{\prime }}\frac{\frac{K_{\mathrm{phd}}}{\mathrm{Ns}}}{1+\frac{K_{\mathrm{phd}}{K}_{\mathrm{vco}}{H}_{\mathrm{LP}}\left(s\right)}{\mathrm{Ns}}}$

[0039] This signal can be used to trim the VCO gain estimation.

[0040] The phase detector signals could be measured by adding an extra charge pump working in parallel with the original one. FIG. 4 shows a phase detector with two charge pumps 25, 45. The second charge pump 45 is used for the feedback path. The output from this extra charge pump is measured in a matched filter 70 (see FIG. 5), which also sets the dynamics of the regulation. The filter must be able to detect the polarity of the error signal to produce the correction signal. The polarity can be measured by correlating the output signal with the original modulation signal.

[0041] In FIG. 4, two output currents 60, 62 are produced with the same duty cycle. One output 60 is used for the ordinary PLL loop filter and the other 62 is used for trimming the VCO gain estimation.

[0042] A block diagram of the proposed trimming method is shown in FIG. 5. This scheme uses the phase detector 80 of FIG. 4 to measure the phase difference in the phase detector. In FIG. 5, the filter 65 in the feedback path is used both for measuring the modulation error due to VCO-gain estimation error and setting the dynamic behavior of the trimming loop. Since part of the VCO gain variation is known this could be compensated outside the feedback loop. This enables a faster control since the range of a variable amplifier 75 in the control loop could be reduced.

[0043] FIG. 6 shows a block diagram in which compensation for VCO-gain variation due to center frequency variations is added.

[0044] This version (FIG. 6) includes a rough estimation due to the center frequency (from the DAC) at the input of an amplifier 175, which reduces the gain range of the feedback path. This figure also shows a VCO version 116 with separate modulation input 90. Using this VCO 116 the amplifiers 75, 175 could change the DC level applied to the varactor (as in FIG. 3). The center frequency is set by adding a DC-voltage to the S-Δ input 0, corresponding to the average division ration (fout/fref).

[0045] A test signal could be applied to the two modulation points. If the VCO gain estimation is correct there will be no output from the phase detector 80. If the integrated PLL output signal is sampled coherent at the test signal frequency we get a DC voltage corresponding to the mismatch. This voltage can be used to set the gain in the second modulation path 175, 75 and we have a feedback system for controlling the VCO gain estimation. Some additional filtering 70 could be applied to get the correct dynamics in the compensation loop.

[0046] The test signal is seen at the PLL output. Therefore, the test signal has to be chosen low enough not to destroy the ACPR spectra, if the test signal is applied outside the transmit channel, or the EVM (error vector magnitude), if the signal is applied inside the transmit channel. The test signal is mixed with the amplitude signal after the PLL (see FIG. 1) so it will not appear as a spur at the modulator output.

[0047] When using the dual chargepump solution, the error signal measured represents a HP-filtered version of the phase error signal. Since the main energy of the error signal is contained in the LF part this could mean the quality of the error signal is less than optimal.

[0048] If the error signal is measured after the loop filter instead, we have a LP-filtered version of the frequency error, which could be used for automatic tuning. The error signal then becomes: $f_{\mathrm{error}}\left(s\right)=f_{\mathrm{inst}}\left(s\right)\frac{K_{\mathrm{vco}}^{\prime }-K_{\mathrm{vco}}}{K_{\mathrm{vco}}^{\prime }}\frac{\frac{K_{\mathrm{phd}}{H}_{\mathrm{LP}}\left(s\right)}{\mathrm{Ns}}}{1+\frac{K_{\mathrm{phd}}{K}_{\mathrm{vco}}{H}_{\mathrm{LP}}\left(s\right)}{\mathrm{Ns}}}$

[0049] This requires that both frequency insertion points are DC-coupled. A block diagram of this solution is presented in FIG. 7.

[0050] All these trimming methods are described above with reference to the two modulation points at the VCO and prescaler input. However, they could equally be applied to any two-point modulator which has one LP-path and one HP-path. For instance the LP path could be supplied through the PLL reference.

[0051] While particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.