Operational amplifier with independent input offset trim for high and low common mode input voltages

[0002] This application claims the benefit of provisional patent application No. 60/388,288 to Huang, filed Jun. 12, 2002.

[0003] 1. Field of the Invention

[0004] This invention relates to the field of trim circuits, and particularly to trim circuits for operational amplifiers which employ complementary input pairs to achieve a rail-to-rail common mode input range.

[0005] 2. Description of the Related Art

[0006] Operational amplifiers have an associated parameter, referred to as input offset voltage (V_os), which specifies the op amp's differential input voltage applied to the amplifier's input terminals when the output voltage or current is zero. V_osis zero for an ideal amplifier. To reduce V_os, some op amps provide one or more “trim” inputs; applying appropriate currents or voltages to the trim inputs reduces V_os.

[0007] One example of an op amp with a trimmable V_osis shown in FIG. 1; this approach is described in U.S. Pat. No. 6,194,962 to Chen. The op amp's input consists of a first differential transistor pair MN1 and MN2, and a complementary differential transistor pair MP1 and MP2; both input pairs are connected to receive a differential input signal applied to input terminals V+ and V−. MN1 and MN2 are biased with a tail current source 10 and MP1 and MP2 receive a tail current from a source 12. In responding to the differential input voltage, each input pair produces a differential current that feeds in to a folded cascode stage 14, which produces an output current I_outthat varies with the differential currents received from the input pairs. A pair of trim inputs TRIM1 and TRIM2 are connected to respective nodes of the folded cascode stage 14.

[0008] In operation, the PMOS input pair (MP1, MP2) is active when the input common mode voltage (V_cm) is low (below a pre-set threshold voltage), and the NMOS input pair is active when V_cmis high (above the pre-set threshold voltage). When a low V_cmis applied to the op amp, a first correction current ΔI1 is applied to TRIM1 or TRIM2 to reduce V_osto zero. The correction provided by ΔI1 is given by ΔI1/gmp, where gmp is the transconductance of PMOS transistors MP1 and MP2; correction current ΔI1 is applied throughout the entire common mode input range. After ΔI1 has been set, a high V_cmis applied to the op amp, and a second correction current ΔI2 is applied to TRIM1 or TRIM2 (with ΔI1 still applied) to reduce V_os. Thus, for a high V_cm, the correction provided by ΔI1 and ΔI2 is given by (ΔI1+AI2)/gmn, where gmn is the transconductance of NMOS transistors MN1 and MN2, since ΔI1 is present throughout the entire common mode input range, while ΔI2 is only present at high V_cm.

[0009] This approach has several disadvantages. For example, the trim range for a high V_cmoffset has to be larger than the untrimmed offset range, due to the effect of the low V_cmcorrection current ΔI1. For example, if the untrimmed offset for both high V_cmand low V_cmhas a range of ±2.5 mV, the trim range for low V_cmcan the be set at ±2.5 mV, but the trim range for a high V_cmhas to be set at ±5 mV. In addition, any supply voltage or V_cmdependent mismatch of ΔI1 and ΔI2 leads to a supply/V_cmdependence for the post-trim trim V_osat high V_cm. This approach also places a constraint on the procedure used to calibrate the op amp, requiring that the calibration be done in a prescribed sequence.

[0010] An operational amplifier is presented which overcomes the problems noted above.

[0011] The present op amp provides independent trimming of V_osfor both high and low common mode input voltages. The amplifier includes complementary input pairs, and employs a steering circuit which provides a tail current I_tailto one input pair when V_cmis less than a threshold voltage V_th, and provides I_tailto the other input pair when V_cmis greater than V_th. The input pairs produces an output current I_outthrough a load stage; I_outvaries with the pairs' differential output currents. The load stage, which is preferably a folded cascode stage, includes one or more trim inputs which enable V_osto be varied with one or more trim signals applied to the trim inputs. A first trim signal generating circuit provides a first trim signal to a trim input only when V_cmis less V_th, and a second trim signal generating circuit provides a second trim signal to a trim input only when V_cmis greater than V_th. This allows the input offset voltages at high and low V_cmto be adjusted independently, thereby avoiding the problems identified above.

[0012] In a preferred embodiment, the steering circuit includes a steering transistor which steers tail current to a PMOS input pair when V_cmis less than a threshold voltage V_th, and to a NMOS input pair via a current mirror circuit when V_cm>V_th. A first trim signal generating circuit generates a first trim signal, suitable for trimming V_osat low V_cm(PMOS pair active), by mirroring a fixed bias current to a first digital-to-analog converter (DAC) which produces the first trim signal in response. A second trim signal generating circuit generates a second trim signal suitable for trimming V_osat high V_cm(NMOS pair active) when tail current is steered to the NMOS input pair. A diverting circuit is connected to divert the fixed bias current when tail current is steered to the NMOS input pair, such that the first trim signal is reduced to zero. In this way, the first trim signal can be tailored to trim V_osat low V_cm, the second trim signal trims V_osat high V_cm, and each trim signal can be independently varied without affecting the other.

[0013] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

[0014] FIG. 1 is a schematic diagram of a known op amp with V_ostrim inputs.

[0015] FIG. 2 is a block/schematic diagram which illustrates the basic principles of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.

[0016] FIG. 3 is a schematic diagram of a preferred embodiment of an op amp with independent input offset trim for high and low common mode input voltages per the present invention.

[0017] The principles of an operational amplifier with independent input offset trim for high and low common mode input voltages are illustrated in FIG. 2. As before, the op amp includes complementary input pairs: an NMOS pair MN1, MN2, and a PMOS pair MP1, MP2; each is connected to receive a differential input signal at input terminals V+ and V−. The PMOS′ sources are connected together at a common mode node 20, and the NMOS′ sources are connected together at a common mode node 22. Each input pair produces a differential current that is fed to a load stage 18—preferably implemented as a folded cascode stage—which produces an output current I_outthat varies with the input voltage applied to the input pairs. Load stage 18 includes at least one trim input (two trim inputs, TRIM1 and TRIM2, are shown in the exemplary embodiment shown in FIG. 2), and is arranged such that the op amp's input offset voltage V_oscan be varied by applying one or more trim signals to the trim inputs.

[0018] The op amp includes a steering circuit 24, which is arranged to provide tail current to one or the other of the input pairs depending on the relationship between the differential input signal's common mode input voltage V_cmand a threshold voltage V_th. Steering circuit 24 provides a tail current I_tailto common mode node 20 when V_cmis less than V_th, and provides I_tailto common mode node 22 when V_cmis greater than V_th.

[0019] The op amp also includes a first trim signal generating circuit 26 and a second trim signal generating circuit 28. Circuit 26 is arranged to provide a first trim signal ΔI1 to at least one of the op amp's trim inputs only when V_cmis less than V_th. Similarly, circuit 28 is arranged to provide a second trim signal ΔI2 to at least one of the op amp's trim inputs only when V_cmis greater than V_th. The trim signal generating circuits are arranged such that first trim signal ΔI1 is set to trim V_osfor a low V_cm, and second trim signal ΔI2 is set to trim V_osfor a high V_cm.

[0020] The present op amp is arranged such that trim signals ΔI1 and ΔI2 can be independently varied without affecting the other. This provides several advantages over the prior art approach described above. The trim range for a high V_cmoffset is no longer required to be widened because of the adverse effect of the low V_cmtrim signal—the trim ranges can be set solely by the untrimmed offset voltage range for both high and low common mode input voltages. The independent trim signal generating circuits eliminate problems caused by supply voltage or V_cmdependent mismatch of ΔI1 and ΔI2, and remove constraints that were previously imposed on the amplifier's calibration procedure.

[0021] A preferred embodiment of the present invention is shown in FIG. 3. Here, steering circuit 24 is made from a fixed current source 30 which outputs tail current I_tail, a steering transistor MP3, and a current mirror made from an input transistor MN3 and an output transistor MN4. Steering transistor MP3 has its source-drain circuit connected between common mode node 20 and current mirror input transistor MN3, and its gate connected to a bias voltage V_th. When so arranged, when V_cm<V_th, steering transistor MP3 is off and I_tailis provided to common mode node 20 and the PMOS input pair. When V_cm>V_th, steering transistor MP3 is on and conducts I_tailto the current mirror, which mirrors the tail current to common mode node 22 and the NMOS input pair.

[0022] Trim signal generating circuit 26 is preferably made from a fixed current source 32 which outputs a bias current I1, a current mirror made from an input transistor MN5 and an output transistor MN6, and a DAC 34. The MN5/MN6 current mirror mirrors I1 to the reference current input of DAC 34. In response to the mirrored current, DAC 34 produces correction current ΔI1, which is connected to one of the trim inputs of load stage 18.

[0023] Trim signal generating circuit 28 is preferably made from a transistor MN7 connected to conduct a current I2 when steering transistor MP3 steers I_tailto the MN3/MN4 current mirror, and a DAC 36. Current I2 is applied to the reference current input of DAC 36, which produces correction current ΔI2 in response; ΔI2 is connected to one of the trim inputs of load stage 18. Since I2 is only present when steering transistor MP3 steers I_tailto the MN3/MN4 current mirror (i.e., when V_cm>V_th), ΔI2 is only generated when V_cm>V_th.

[0024] The operational amplifier also includes a diverting circuit 38, which is arranged to divert bias current ΔI1 from the MN5/MN6 current mirror when steering transistor MP3 steers I_tailto the MN3/MN4 current mirror, which serves to reduce or eliminate correction current ΔI1. When so arranged, correction current ΔI1 is reduced or eliminated when V_cm>V_th, such that correction current ΔI1 is only generated when V_cm<V_th. Diverting circuit 38 preferably comprises a diverting transistor MN8 which is connected to the output of fixed current source 32 and in parallel with MN7. MN8 diverts current I1 away from the MN5/MN6 current mirror when steering transistor MP3 steers I_tailto the MN3/MN4 current mirror; i.e, when V_cm>V_th. In this way, the drive current to DAC 34 is reduced or eliminated, as is correction current ΔI1.

[0025] Diverting transistor MN8 is preferably sized to reduce current I1 (and thus correction current ΔI1) to zero. For example, assume that tail current source 30 outputs 180 μA and trim signal generating circuit current source 32 outputs 10 μA (i.e., I1=10 μA). When V_cm>V_th, MP3 steers 180 μA to current mirror transistor MN3. To reduce I1 (and ΔI1 to zero, MN8 needs to conduct at least 10 μA. To achieve this, MN8 and MN3 need to form a current mirror having a ratio of at least 1:18.

[0026] The op amp is preferably arranged with trim input TRIM1 as a “positive” trim input, such that the application of a positive trim signal ΔI1 or ΔI2 reduces a positive V_os, and with TRIM2 as a “negative” trim input which reduces a negative V_oswith the application of a positive trim signal ΔI1 or ΔI2. Alternatively, DACs 34 and 36 could each be designed to output positive or negative trim signals. In this case, only one trim input would be needed, to which both ΔI1 and ΔI2 would be connected.

[0027] Note that though the present operational amplifier has been illustrated as implemented exclusively with field-effect transistors (FETs), the invention is equally applicable to an implementation in which some or all of the transistors are bipolar.

[0028] Further note that the implementation shown in FIG. 3 is merely one possible way of implementing the invention. A number of mechanisms could be employed to ensure that ΔI1 is generated only when V_cm<V_th, and that ΔI2 is generated only when V_cm>V_th. In addition, the invention can be used with other load topologies: the implementation of load stage 18 shown in FIGS. 1-3 is merely exemplary.

[0029] The implementation shown in FIG. 3 can be a single-stage operational amplifier, or the first stage of a multi-stage operational amplifier.

[0030] While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.