US 6,693,468 B2Grant
Fractional-N synthesizer with improved noise performance
Issue Date:2004-02-17
•10 Claims
•3 Drawing Sheets
Abstract
A fractional sequence generator having a plurality of cascaded accumulators whose carry-outs-upon-overflow are provided over a plurality of recombination paths and selective delays to an adder, the pattern of selective delays being modified by the addition of delay elements in all recombination paths except the last to reduce the number of quantization error terms in the transfer function of the sequence generator. Illustrative embodiments may have any number (greater than one) of accumulators and recombination paths, while continuing to exhibit desired simplified frequency response characteristics.
Metadata
Assignee
- RF Micro Devices, Inc.
Inventors
- Scott Robert Humphreys
- Alex Wayne Hietala
Application Information
Application Number:US 09/879,672
Filing Date:2001-06-12
Priority Date:2001-06-12
Art Unit:7
Classifications
IPC:
H03B 2100
Field of Search:
327100327105327106327107331 1 A331 10
Patent Drawings (3 sheets)
Description
Related Applications
[0002] The present application is related to concurrently filed non-provisional applications:
[0003] (i) 09/879,806 by A. W. Hietala entitled Fractional-N Modulation with Analog IQ Interface having been flied on Jun. 12, 2001;
[0004] (ii) 09/879,670 by B. T. Hunt and S. R. Humphreys entitled Dual-Modulus Prescaler having been filed on Jun. 12, 2001;
[0005] (iii) 09/879,808 by S. R. Humphreys and A. W. Hietala entitled Accumulator with Programmable Full-Scale Range having been filed on Jun. 12, 2001; and
[0006] (iv) 09/879,671 by B. T. Hunt and S. R. Humphreys entitled True Single-Phase Flip-Flop having been flied on Jun. 12, 2001;
[0007] which non-provisional applications are assigned to the assignee of the present invention, and are hereby incorporated in the present application as if set forth in theft entirety herein.
Field of the Invention
[0008] The present invention relates to frequency synthesizers. More particularly, the present invention relates to fractional-N (F-N) frequency synthesizers for use in radio frequency (RF) applications, such as mobile radiotelephones. Still more particularly, the present invention relates to RF F-N frequency synthesizers with improved noise performance.
Background of the Invention
[0009] Phase-locked loop (PLL) frequency synthesis is a well-known technique for generating a variety of signals of predetermined frequency in many applications, e.g., digital radiotelephone systems. Briefly, the output of a voltage-controlled oscillator (VCO) is coupled to a frequency divider for providing one input to a phase detector. Another input to the phase detector is a reference signal from a fixed frequency source having high stability over a range of operating conditions. Differences in phase determined by the phase detector (typically reflected as charge pulses) are then filtered and applied to the VCO to control changes to the frequency of the VCO of such magnitude and sign as to reduce the detected phase difference.
[0010] Fractional-N (F-N) synthesizers based on the above-described PLL frequency synthesis techniques have been in favor for some time because, inter alia, they provide for non-integer division of the VCO output, thereby providing greater flexibility in choosing VCO output frequencies, and allowing the use of higher frequency reference sources with the concomitant potential for wider bandwidth and faster loop locking times. Other background aspects of RF synthesizers (and, in particular, F-N synthesizers), and their implementation and use, are presented in B. Razavi, RF Microelectronics, Prentice-Hall PTR, 1998, especially pp. 269-297, and in incorporated related patent applications (i-iv) cited above.
[0011] FIG. 1 shows a prior art F-N synthesizer arrangement in which a reference signal, e.g., from stable frequency source is applied on input 135 as one input to a phase detector 130. The other input to phase detector 130 is a frequency divided output from programmable divider 120 on path 125. Divider 120, in turn, receives an input from the output of VCO 100, which output is the frequency-controlled output of the synthesizer of FIG. 1. The integer part of the division ratio is applied on line 175 and input reflecting the fractional part of the division ratio is applied on line 155. More specifically, fractional sequence generator 150 responds to an applied fractional divisor input on lead 170 to provide a time-variable sequence of integer values, which, when applied through adder 160 allow a variable divisor to be realized in divider 120. Typically, fractional sequence generator 150 is clocked by the output of divider 120, and a new integer divisor value is provided for each such clock cycle. The overall effect of the application of this time-variable control of the integer divisor in divider 120 is to apply a divisor to divider 120 that has an average value equal to the sum of the integer and fractional inputs on 175 and 170, respectively.
[0012] In operation, the prior art synthesizer of FIG. 1 controls the frequency of VCO 100 in response to varying integer divisors by applying a time-variable frequency divided version of the output from VCO 100 to phase detector 130. In comparing phase information for the frequency divided input from divider 120 with the reference signal on input 135, phase detector 130 develops an error signal that is smoothed in low pass loop filter 140 and applied to VCO 100 in such manner as to reduce the phase error between the reference signal and the frequency divided signal from divider 120. In doing so, the output from VCO 100 tracks the desired frequency variations specified by fractional inputs on input 170.
[0013] As will be appreciated by those skilled in the art, F-N synthesizers using varying integer divisors to provide an effective fractional divisor produces undesired signal components characterized as quantization noise or spurious frequency tones. A number of techniques have been proposed and implemented that seek to minimize or mitigate effects of such spurious noise components. Among such remedial techniques are some for introducing correction signals tending to cancel spurious signals. Razavi, supra at pp. 282-283, describes techniques for reducing quantization noise by using a sigma-delta modulator to control division in a F-N synthesizer. An ideal sigma-delta-controlled fractional sequence generator has a z-domain noise transfer function given by
[0014] Y(z)=Qn(z)(1−z−1)n, (Eq. 1)
[0015] where Q(z) is white noise and n is the order of the sigma-delta modulator. Such an ideal sigma-delta modulator-controlled fractional sequence generator has a signal transfer function having the form
[0016] Y(z)=X(z)z−n, (Eq. 2)
[0017] where X(z) is the input. Likewise, U.S. Pat. No. 4,965,531 issued Oct. 23, 1990 to T. A. D. Riley, discloses use of a second or higher sigma-delta modulator to control the division ratio in a F-N synthesizer in seeking to reduce quantization noise. These and other sequence generator techniques offer stability, optimal noise shaping, power consumption and other implementation difficulties in some applications.
[0018] FIG. 2 shows a prior art fractional sequence generator 200 having improved control of spurious signals. The fractional sequence generator of FIG. 2, is based generally on aspects of a F-N synthesizer circuit arrangement shown in U.S. Pat. No. 4,609,881 issued Sep. 2, 1986 to J. N. Wells, which patent is hereby incorporated by reference as if set forth in its entirety herein. The sequence generator of FIG. 2 includes an accumulator structure 210 having a plurality of accumulators—each accumulator comprising an n-bit bank of D flip-flops (an n-bit register), 230-i,i=1, 2, and 3 and a respective n-bit adder 225-i,i=1, 2, and 3. Adder 225-1 receives a fractional divisor value 𝑓 (the least significant bits of a divisor of the form N.𝑓, where N is an integer) on the C input path 215 during a current clock cycle of the output of divider 120. Clock signals corresponding to the output of divider 120 are provided as inputs on Fvinput 220. The value 𝑓 on input 215 is added to the previous contents of n-bit register 230-1 and the result is stored in register 230-1. In addition, when register 230-1 overflows (provides a carry-out indication on recombination output CO1), that signal is immediately applied to adder 240 at an input labeled +1. The set of recombination paths is conveniently referred to as recombination network 205.
[0019] As further shown in FIG. 2, the sum generated by adder 225-1 is also provided as an input to adder 225-2, where it is combined with the prior contents of register 230-2 during the following clock cycle. Again, the result of the addition is stored back in register 230-2 and a carry indication is provided on recombination path CO2 when overflow of adder 225-2 occurs. This carry indication is applied to an input to adder 240 labeled +1. In addition, the same overflow signal on CO2 is applied to a −1 input to adder 240 after a delay of one additional clock cycle. Such additional delay of one clock cycle is provided by delay flip-flop 250.
[0020] In similar fashion, adder 225-3 receives the result of the addition performed at adder 225-2 and adds it to the prior contents of register 230-3. Again, the result of the addition is stored back to register 230-3, and, when a carry-out occurs from adder 225-3, recombination path CO3 supplies the carry-out signal to a +1 input to adder 240. In addition, the CO3 recombination path provides the carry-out indication to delay flip-flop 260, thereby providing the carry out signal to a −2 input to adder 240 after an additional clock cycle. Further, the delayed CO3 signal on the output of flip-flop 260 is also provided as an input to delay flip-flop 270 where it provides the carry-out signal to a +1 input to adder 240 after yet another clock cycle (a total delay of two clock cycles).
[0021] Each of the carry-out signals from adders 225-icauses adder 240 to provide an output on SEQ path 245 to temporarily increment or decrement the integer divisor applied through adder 160 to divider 120 in FIG. 1. The magnitude and sign of an increment or decrement during any clock cycle is determined as the sum of increments and decrements indicated by the weights for all recombination paths supplying a carry-out signal, the weights being associated with a Pascal's Triangle. These integer divisor changes advantageously average to the desired fractional portion over time, and, in so doing, provide reduced quantization noise compared with prior F-N techniques. See further the discussion of Pascal sequence coefficients in incorporated U.S. Pat. No. 4,609,881. Further, the structures illustrated in FIG. 2 offer desirable implementation characteristics for many applications. Such characteristics include robust stability for any number of accumulators (the order of the sequence generator).
[0022] However, a z-domain frequency response, Y(z), of fractional sequence generators of the type shown in FIG. 2, for an input of X(z) can be shown to assume the form
[0023] Y(z)=X(z)(3z−1−3z−2+z−3)+Q1(z)(1−z−1)3+Q2(z)(1−z−1)3+Q3(z)(1−z−1)3 (Eq.3)
[0024] where Qj(z) terms represent quantization noise terms associated with the jth accumulator. Further, it can readily be determined that the resulting noise components Qjcontribute noise to the output signal that does not have preferred sigma-delta-like noise characteristics.
[0025] It is therefore desired to realize advantages of the circuit arrangements of FIG. 2 while simplifying its frequency response characteristics to more nearly resemble those of sigma-delta sequence generators.
Summary of the Invention
[0026] Limitations of the prior art are overcome and a technical advance is made in accordance with the present invention, typical embodiments of which are described below.
[0027] In accordance with one illustrative embodiment of the present invention, a fractional sequence generator of the type shown in FIG. 2 is modified by the addition of delay elements to better align carry-outs from accumulators other than the last accumulator. Using this modification, a sequence generator is realized that retains low circuit complexity and power consumption characteristic of some cascaded-accumulator sequence generator implementations while exhibiting a desired sigma-delta-like quantization noise spectrum.
[0028] In accordance with an aspect of illustrative embodiments of the present invention improved structures will be realized for sequence generators having a higher number of recombination paths, while continuing to exhibit simplified frequency response characteristics.
Brief Description of the Drawing Figures
[0029] The above-summarized invention will be more fully understood upon consideration of the following detailed description and the attached drawing wherein:
[0030] FIG. 1 shows a prior art F-N frequency synthesizer.
[0031] FIG. 2 shows a prior art fractional sequence generator for use in F-N synthesizers such as that shown in FIG. 1.
[0032] FIG. 3 shows an improved fractional sequence generator in accordance with an illustrative embodiment of the present invention.
[0033] FIG. 4 shows a linearized equivalent representation of the fractional sequence generator of FIG. 3 that proves useful for deriving the improved frequency response of the sequence generator of FIG. 3.
Detailed Description
[0034] The following detailed description and accompanying drawing figures depict illustrative embodiments of the present invention. Those skilled in the art will discern alternative system and method embodiments within the spirit of the present invention, and within the scope of the attached claims, from consideration of the present inventive teachings.
[0035] FIG. 3 shows a modified version 300 of the fractional sequence generator 200 of FIG. 2. Once again, an accumulator structure in FIG. 3 presents a 3-accumulator configuration by way of illustration, with each accumulator again comprising a bank of n-bit D flip-flops (an n-bit register), 330-i, i=1, 2, and 3 and corresponding n-bit adders 325-i, i=1, 2, and 3. These accumulators perform in the same fashion as corresponding accumulators described above in connection with FIG. 2. Further carry-out signals from adders 325-i(e.g., one-bit signals) are clocked during the next clock interval over recombination paths within recombination network 305 to an adder 340 having adder weights of the same kind as in the circuit of FIG. 2. Delay elements 350, 360 and 370 provide the same one-clock cycle delays as corresponding elements 250, 260 and 270 provide in the circuit of FIG. 2.
[0036] In accordance with one aspect of an illustrative embodiment of the present invention, additional delay elements 345 and 355 are added to the circuit arrangement of FIG. 2. Thus, carry-out signals from all adders 325-iin accumulator structure 310, other than the last such adder (325-3, for the example shown in FIG. 3), experience an additional delay in their respective recombination paths to adder 340. As will now be demonstrated, this augmentation of the sequence generator of FIG. 2 gives rise to the desired frequency response.
[0037] FIG. 4 is a linearized equivalent representation of the improved frequency sequence generator of FIG. 3. In FIG. 4 accumulators in the accumulator structure 310 of FIG. 3 are replaced by non-delaying integrators (adder 410 with delay 415, adder 445 with delay 452, and adder 485 with delay 495); register flip-flops of FIG. 3 appear as unit delays 415, 452 and 495. Adders 405, 440 and 480 perform adjustments to stored accumulator totals when a carry-out signal is generated on respective recombination paths COj, j=1, 2, 3. Quantization noise Qj, j=1, 2, 3, contributed at each of the accumulators of FIG. 3 is shown as added at adders 420, 455 and 497. Other delays in recombination paths in FIG. 3, and input weightings to adder 340 in FIG. 3, are reflected in elements 425, 465 and 473. That is, the Pascal triangle coefficients taught in the above-cited U.S. patent Outputs from the several recombination paths (outputs from delay elements 425, 465 and 473 are summed in adders 470 and 450 to produce the fractional sequence generator output Y on 471 corresponding to the input X applied at 401.
[0038] Application of well-known z-domain analysis techniques yields a frequency response function for the circuit of FIG. 3 in terms of its linearized equivalent shown in FIG. 4 that may be represented as
[0039] Y(z)=X(z)z−3+Q(z)(1−z−1)3 (Eq. 4)
[0040] A comparison of the frequency response function of Eq. 4 for the improved sequence generator circuit of FIGS. 3 and 4 with the frequency response function of Eq. 3 for the prior art sequence generator of FIG. 2 shows the simplified, improved response for the circuit of FIGS. 3 and 4. Thus, advantages of sigma-delta sequence generators are realized in accordance with present inventive teachings while maintaining desirable structural aspects (e.g., robust stability, and lower circuit complexity, implementation area, and power consumption) of sequence generators of the type shown in FIG. 2.
[0041] While the above describes illustrative embodiment of the present invention includes three accumulators, it is well known to include only two or to include more than three accumulators, and corresponding recombination paths, while also scaling weights for adder 340 in accordance with sequential rows of Pascal's triangle. Thus, for example, a four-accumulator sequence generator will apply adder increments (decrements when negative) of +1, −3, +3, and −1 in response to carry-out indications from such a fourth accumulator, with such increments (decrements) being applied after respective delays of 0, 1, 2, and 3 clock cycles.
Claims
What is claimed is:
1. A fractional sequence generator comprising
a first n-bit accumulator, A1, for adding a fractional multi-bit input word to a previously accumulated total to provide a new n-bit total, N1, and a carry-out signal, CO1, when said N1overflows said n-bit accumulator,
an ordered plurality of additional n-bit accumulators, Aj, j=2, 3, . . . , K, each Ajadding an n-bit input word to a previously accumulated total to provide a respective new n-bit total, Nj, and a respective carry-out signal COjwhen said, Njoverflows said Aj, A2receiving said N1as an input word, and each Aj, j>1 receiving Nj−1 as an input word, and
a recombination network comprising
an adder providing an output equal to the sum of weighted increments and decrements, each increment and decrement associated with a respective selectively delayed one of said COj, and
a plurality of delay elements for selectively delaying said COj, COKexperiencing K−1 units of delay, COj, j<K, experiencing delays of 1, . . . , j units of delay, for j=1, 2, 3, . . . , K−1.
2. The sequence generator of claim 1 further comprising means for applying said output of said adder to adjust a divisor of a divider.
3. The sequence generator of claim 2 wherein said units of said delay comprise cycles of the output of said divider.
4. The sequence generator of claim 3 wherein each of said accumulators performs an addition during each of said cycles of the output of said divider.
5. The sequence generator of claim 2 wherein said divider controls the output frequency of a F-N synthesizer.
6. The sequence generator of claim 1 wherein each increment and decrement associated with one of said COjcomprises increments and decrements associated with the jth row of Pascal's triangle.
7. The sequence generator of claim 6 wherein said jth row of Pascal's triangle comprises j weights, and wherein the least-delayed COjsignal causes said adder to increment said output of said adder by one.
8. A F-N synthesizer comprising
a phase detector receiving inputs from a frequency divider and a reference source and generating an output based on phase differences between said inputs,
a voltage controlled oscillator (VCO) for generating output signals based on said output of said phase detector,
a divider receiving said output signals from said VCO as an input and providing a divided version of said output signals from said VCO as an output,
a divisor control circuit for supplying a time-varying integer divisor signal to said divider, said divisor control circuit comprising means for successively combining at least one integer input with a time sequence of integer increment and decrement inputs to form said time-varying integer divisor signal,
a fractional sequence generator for supplying said time sequence of integer increment and decrement inputs to said divisor control circuit, said fractional sequence generator comprising
a first n-bit accumulator, A1, for adding a fractional multi-bit input word to a previously accumulated total to provide a new n-bit total, N1, and a carry-out signal, CO1, when said N1overflows said n-bit accumulator,
an ordered plurality of additional n-bit accumulators, Aj, j=2, 3, . . . , K, each Ajadding an n-bit input word to a previously accumulated total to provide a respective new n-bit total, Nj, and a respective carry-out signal COjwhen said Njoverflows said, Aj, A2receiving said N1as an input word, and each Aj, j>1 receiving Nj−1 as an input word, and
a recombination network comprising
an adder providing an output equal to the sum of weighted increments and decrements, each increment and decrement associated with a respective selectively delayed one of said COj, and
a plurality of delay elements for selectively delaying said COj, COKexperiencing K−1 units of delay, COj, j<K, experiencing delays of 1, . . . , j units of delay, for j=1, 2, 3, . . . , K−1.
9. The F-N synthesizer of claim 8 wherein said units of delay comprise cycles of said output to said driver.
10. The F-N synthesizer of claim 8 wherein each of said accumulators performs an addition during each of said cycles of the output of said divider.
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