Dual mode USB-PS/2 device

[0002] The present invention relates to a method and/or architecture for peripheral devices generally and, more particularly, to a method and/or architecture for a dual mode USB-PS/2 device.

[0003] A peripheral device can be added to a personal computer (PC) to provide input or to enhance functionality. Peripheral devices communicate with the PC using a signaling protocol. Two signaling protocols commonly used to interface a peripheral device (i.e., a mouse) are the Universal Serial Bus (USB) protocol (e.g., the USB Specification 1.1, published September 1998 or the USB Specification 2.0, published April 2000, etc., which are hereby incorporated by reference in their entirety) and the Personal System 2(PS/2) protocol (e.g., see IBM Personal System/2 Hardware Interface Technical Reference—Common Interfaces, October 1990 and the IBM Personal System/2 Mouse Technical Reference, June 1989, which are hereby incorporated by reference in their entirety). In the example of a mouse, support for both the USB and the PS/2 protocols is desirable to maximize connectivity.

[0004] In order to support both protocols, conventional peripheral devices incorporate a micro-controller connected to a set of external components that support the USB protocol and a set of external components that support the PS/2 protocols. A number of I/O pins of the micro-controller must be dedicated to selecting the proper component set for supporting the active signaling protocol. Conventional peripheral devices that support both protocols can compromise performance of one or both of the signaling modes. The micro-controllers in the conventional peripheral devices require complex firmware to manage the external components and both protocols.

[0005] Conventional peripheral devices that support both USB and PS/2 protocols can have one or more of the following disadvantages: (i) requiring higher cost due to additional external components, (ii) using more circuit board space required to support the extra components, (iii) dedicating valuable I/O pins on the micro-controller, (iv) requiring additional firmware to manage the external components, (v) requiring additional firmware to manage both protocols, and (vi) compromising the performance of one or both protocols made to support the dual modes.

[0006] A single chip solution that eliminates the need for extra components and extra I/O pins to support dual mode operation would be desirable.

[0007] The present invention concerns an apparatus comprising an integrated circuit configured to operate in a plurality of signaling protocols. The integrated circuit may be configured to automatically select one of the plurality of signaling protocols in response to a signaling protocol of a connected bus.

[0008] The objects, features and advantages of the present invention may include a method and/or architecture that may provide a dual mode device (e.g., USB-PS/2) that may (i) require no external components for dual mode (e.g., USB-PS/2) operation, (ii) share integrated circuit pins for both protocols, (iii) enable simplified firmware, (iv) eliminate polling of data lines for detecting long initial both-lines-LOW state, (v) combine both protocol features into a single chip, (vi) control signal edge rate for slow-slew rate, low-emissions operation in both modes, (v) simplify peripheral design, (vi) provide an interrupt that changes behavior depending on a selected signaling mode, and/or (vii) provide a regulator pin that may be tri-stated generally simplifying switching between modes.

[0009] These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

[0010] FIG. 1 is a block diagram illustrating a preferred embodiment of the present invention; and

[0011] FIG. 2 is a detailed block diagram illustrating a preferred embodiment of the present invention.

[0012] Referring to FIG. 1, a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 may be implemented, in one example, as an interface circuit of a dual mode device (e.g., USB-PS/2). The circuit 100 may have an input/output 102 that may receive/present a signal (e.g., DP/SCLK), an input/output 104 that may receive/present a signal (e.g., DM/SDATA), an input 106 that may receive a signal (e.g., MODE), an output 108 that may present a signal (e.g., INT), an output 110 that may present the signal DM/SDATA, and an output 112 that may present the signal DP/SCLK. The circuit 100 may have a number of other inputs and outputs 114 that may receive and present other signals (e.g., USB driver speed for selecting between low speed and full speed USB operation, clock, etc.). The signals DP/SCLK and DM/SDATA may be used, in one example, as differential signals (e.g., DP/D+ and DM/D−, respectively) in accordance with the Universal Serial Bus (USB) protocol. In another example, the signals DP/SCLK and DM/SDATA may be used as a clock and data signals (e.g., SCLK and SDATA, respectively) in accordance with the PS/2 protocol.

[0013] When the circuit 100 is in a first mode (e.g., the USB protocol mode), the circuit 100 may be configured to generate and/or receive the signals DP and DM. When the circuit 100 is in a second mode (e.g., the PS/2 mode), the circuit 100 may be configured to generate and/or receive the signals SCLK and SDATA. The signal MODE may be, in one example, a control signal. The signal MODE may have a first state and a second state.

[0014] The circuit 100 may be configured to automatically select (e.g., without user input) the USB mode in response to a first state of the signal MODE or the PS/2 mode in response to a second state of the signal MODE. The signal INT may be, in one example, an interrupt signal. The signal INT may be generated, in one example, in response to the signals DM/SDATA and DP/SCLK both presenting a long low state. In another example, the signal INT may be generated in response to the signal DM/SDATA presenting a long low state. The duration of the low state before an interrupt is recognized may be different for the USB and PS/2 protocols. When the circuit 100 is in the USB mode, the signal INT may be asserted when the dual-low condition terminates. When the circuit 100 is in the PS/2 mode, the signal INT may be asserted in response to expiration of a target time. The circuit 100 may be configured to control an edge rate of the signals DP/SCLK and DM/SDATA. By controlling the edge rate of the signals, the circuit 100 may provide slow-slew rate low-emissions operation.

[0015] The circuit 100 may comprise a circuit 120 and a circuit 122. The circuit 120 may be implemented, in one example, as a dual mode interrupt detection circuit. The circuit 122 may be implemented, in one example, as a dual mode driver circuit. In one example, the dual modes may include USB and PS/2 protocols. The signal MODE may be presented to an input of the circuit 120. The circuit 120 may have an input 124 that may receive the signal DP/SCLK, an input 126 that may receive the signal DM/SDATA, and a number of outputs 128a-128nthat may present a number of signals (e.g., DRCA-DRCN) to a number of inputs 130a-130nof the circuit 122. The signals DRCA-DRCN may be used, in one example, as control signals. The signals DRCA-DRCN may control, in one example, the protocol (e.g., USB or PS/2) and/or operation of the circuit 122. The signals DRCa-DRCn may be generated in response to the signal MODE. The circuit 120 may be configured to generate the signal INT in response to the signals DP/SCLK and DM/SDATA.

[0016] The circuit 122 may have an input/output 132 that may receive/present the signal DP/SCLK and an input/output 134 that may receive/present the signal DM/SDATA. The circuit 122 may be configured to provide communication between the peripheral device and a connected bus. The circuit 122 may be configured, in one example, to control the edge rate of the signals DP/SCLK and DM/SDATA. The circuit 122 may provide slow-slew rate, low-emissions operation.

[0017] Referring to FIG. 2, a detailed block diagram illustrating the circuit 100 implemented in the context of an integrated circuit 140 is shown. The integrated circuit 140 may be implemented as, in one example, a dual mode USB-PS/2 controller chip. The integrated circuit 140 may be used, in one example, to interface a peripheral device (e.g., a mouse) to a USB or PS/2 bus. The integrated circuit 140 may further comprise a circuit 142 and a circuit 144. The circuit 142 may be, in one example, a pull-up circuit and may pull up the signals DP/SCLK and DM/SDATA in accordance with the PS/2 signaling protocol. The circuit 144 may be, in one example, a voltage regulator circuit and may be used to pull up the signal DM/SDATA (or alternatively, the signal DP/SCLK, not shown) in accordance with the USB signaling protocol.

[0018] The integrated circuit 140 may have an I/O pin 146 and an I/O pin 148 that may be connected to the input/outputs 102 and 104 of the circuit 100, respectively. The signals DP/SCLK and DM/SDATA may be presented at the pins 146 and 148, respectively. The output 110 of the circuit 100 may present the signal DM/SDATA to an input of a buffer circuit 150. The output 112 of the circuit 100 may present the signal DP/SCLK to an input of a buffer circuit 152. The buffer circuits 150 and 152 may be implemented, in one example, with hysteresis. In one example, the buffer circuits 150 and 152 may be implemented using Schmitt trigger gates. The buffer 150 may have an output that may present a signal (e.g., DM/SDATA_BUF) in response to the signal DM/SDATA. The buffer 152 may have an output that may present a signal (e.g., DP/SCLK_BUF) in response to the signal DP/SCLK.

[0019] The circuit 142 may have an input 154 that may receive a control signal (e.g., PS/2_EN), an output 156 that may be connected to the pin 146, and an output 158 that may be connected to the pin 148. The circuit 142 may be configured to pull up the pins 146 and 148 to a supply voltage (e.g., VCC) in response to the signal PS/2_EN. The signal PS/2_EN may be, in one example, an enable signal. The signal PS/2_EN may be asserted when the circuit 140 is in the PS/2 mode and de-asserted otherwise. The circuit 142 may comprise, in one example, a switch 160, a resistor 162, a switch 164, and a resistor 166. The switches 160 and 164 may be implemented, in one example, as one or more transistors, a CMOS switch, or other appropriate circuit. The resistors 162 and 166 may be implemented, in one example, as resistors having a predetermined resistance value or as transistors configured to operate as resistors.

[0020] The resistance value of the resistors 162 and 166 may be selected to meet the pull-up criteria of the PS/2 signaling protocol. The signal PS/2_EN may be presented to a control input of the switches 160 and 164. The switch 160 may have a first terminal that may be connected to the supply voltage VCC and a second terminal that may be connected to a first terminal of the resistor 162. A second terminal of the resistor 162, may be connected to the output 156. The switch 164 may have a first terminal that may be connected to the supply voltage VCC and a second terminal that may be connected to a first terminal of the resistor 166. A second terminal of the resistor 166 may be connected to the output 158.

[0021] The circuit 144 may have an input 168 that may receive a control signal (e.g., VREG_EN), an output 170 that may present a regulated supply voltage (e.g., VREG) to an I/O pin 172 of the integrated circuit 140, and an output 174 that may present the state of the pin 172 to an input of a buffer 176. The buffer circuit 176 may be implemented, in one example, having a hysteresis characteristic. In one example, the buffer circuit 176 may be implemented using a Schmitt trigger gate. The buffer 176 may have an output that may present a status signal (e.g., VREG_STAT) in response to the state of the pin 172. The circuit 144 may be configured to present either the supply voltage VREG or a high impedance to the pin 172 in response to the signal VREG_EN.

[0022] The circuit 144 may comprise a voltage regulator 178 and a switch 180. The voltage regulator 178 may be configured, in one example, to generate the regulated supply voltage VREG. The regulated supply voltage VREG may be used to pull up the signal DM/SDATA (or alternatively, the signal DP/SCLK) in accordance with the USB signaling protocol. In one example, the voltage regulator 178 may be configured to present the regulated supply voltage VREG that may be nominally 3.3V or within a range of 2.8V to 3.6V. However, other voltages may be implemented accordingly to meet the design criteria of a particular implementation. The switch 180 may be implemented, in one example, as one or more transistors, a CMOS switch, or other appropriate circuit. The switch 180 may have a control input that may receive the signal VREG_EN, a first terminal that may receive the regulated supply voltage VREG , and a second terminal that may be coupled to the output 170 of the circuit 144. In one example, the second terminal of the switch 180 may be coupled to the output 170 by a resistor 182. The resistor 182 may be used, in one example, as a current limiting resistor.

[0023] The pin 172 may be coupled to the pin 148 by a resistor 184. The resistor 184 may have a predetermined resistance value selected to provide a pull-up of the signal DM/SDATA (or alternatively, the signal DP/SCLK) in accordance with the USB signaling protocol. When the integrated circuit 140 is in a first mode (e.g., the USB mode), the signal VREG_EN may be asserted to enable the regulated supply voltage VREG to pull up the signal DM/SDATA via the resistor 184. When the integrated circuit 140 is in a second mode (e.g., the PS/2 mode), the signal VREG EN may be de-asserted, generally preventing the circuit 144 from affecting the signal DM/SDATA.

[0024] The integrated circuit 140 may also comprise a controller circuit (not shown). The controller circuit may be implemented, in one example, as a microprocessor, micro-controller, digital signal processor (DSP), or other appropriate control circuit. In one example, the controller circuit may be configured to generate the signals VREG_EN, PS/2_EN, and MODE. The signals INT, VREG STAT, DP/SCLK_BUF, and DM/SDATA_BUF may be presented to the controller circuit. In one example, the signals VREG_STAT, DP/SCLK_BUF, and DM/SDATA_BUF may be presented via an input register. In one example, the controller circuit may contain an interrupt controller circuit. The signal INT may be presented, in one example, to the interrupt controller circuit.

[0025] The circuit 100 may be configured to operate using the USB protocol mode when connected to a USB bus or the PS/2 protocol mode when connected to a PS/2 bus. The circuit 120 may be configured to generate interrupt signals in response to bus signals. The circuit 120 may be configured to control the circuit 122. The integrated circuit 140 may be configured to provide PS/2 pull-up signals to both bus lines when the PS/2 mode is selected and a USB pull-up signal to the data line when the USB mode is selected.

[0026] The circuit 120 may determine the duration of the time of a digital LOW state before a signal interrupt for the signals presented to the pins 146 and 148. The duration of the digital LOW state before interrupt may be different for USB and PS/2 protocol modes. The duration of the digital LOW state before interrupt may be less for the PS/2 protocol mode than for the USB protocol mode. The circuit 120 may be configured to detect the desired state and time condition for each mode (possibly at the same time) and assert the corresponding interrupt signal. When a predetermined target time for the duration of the digital LOW state has expired, the circuit 120 may present the signal INT. The circuit 120 may present the signals DRCA-DRCN that may enable the circuit 122 to operate in a PS/2 protocol mode. The predetermined target time may be established by the USB and PS/2 protocol specifications.

[0027] Firmware may be implemented in the integrated circuit 140 that may determine or control determination of the signaling protocol of a connected bus, control selection of a signaling protocol by the circuit 122, and/or control/respond to interrupt timing parameters of a particular signaling protocol.

[0028] The various signals are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation.

[0029] The present invention may provide a dual mode USB-PS/2 device that may (i) require no external components for dual mode USB-PS/2 operation, (ii) share integrated circuit pins for both USB and PS/2 protocols, (iii) enable simplified firmware, (iv) eliminate polling of data lines for detecting long initial both-lines-LOW state, (v) combine both USB and PS/2 features into a single chip, (vi) control signal edge rate for slow-slew rate, low-emissions operation in both USB and PS/2 modes, (v) simplify peripheral design, (vi) provide an interrupt that changes behavior depending on a selected signaling mode, and/or (vii) provide a regulator pin that may be tri-stated generally simplifying switching between PS/2 and USB mode

[0030] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.