Digital wave generating apparatus and the method thereof

[0002] This application claims the priority benefit of Taiwan application Ser. No. 090122164, filed Sep. 6, 2001.

[0003] 1. Field of the Invention

[0004] This invention relates in general to an apparatus for generating a digital wave and the method thereof. More specifically, this invention relates to an apparatus for generating a digital wave and the method thereof, in which a low frequency clock is used for generating a highly accurate digital wave.

[0005] 2. Description of Related Art

[0006] As the demand for high-capacity storage increases, so does the use of the optical information recording apparatus, such as a rewritable or recordable optical drive. When a writable optical drive writes data to a compact disc rewritable (CD-RW), a laser diode emits the energy required for the data recording. During the entire writing process, the laser diode has to be capable of providing three optical signals of different powers. When the optical signal of a different power illuminates the optical disc, the data area on the optical disc will create a corresponding status due to the different power.

[0007] FIG. 1 is a diagram showing the variation of the power of the optical signal for recording corresponding to a data area of the optical disc. The data area of a rewritable optical disc has a space area and a mark area. The data stored in the mark area is constituted by logic “1” and logic “0”. When the laser beam passes the space area, an optical signal having an erase power P_ERASEgenerated by the laser diode must be used to illuminate the optical disc. When the laser beam passes the mark area, an optical signal, alternatively having a write power P_WRITEand a bias power P_BIASgenerated by the laser diode must be used to illuminate the optical disc.

[0008] When writing to the mark area, the required times of the optical signal having the write power P_WRITEand the bias power P_BIASare determined by the characteristic of the optical disc and the specification of the data to be written. One writing period comprises at least one writing power P_WRITEand at least one bias power P_BIAS. Therefore, in one writing period T, the writing power P_WRITEand the bias power P_BIASare generated according to a highly accurate digital wave W. In general, the digital wave W has to be toggled once or twice within one writing period.

[0009] FIG. 2 is an example of a highly accurate digital wave. If a writing period T is divided into n time points, the digital wave W needs to be toggled once or twice within the writing period T. The time point for the toggle state is selected from the n time points. Referring to FIG. 2, the time points for the toggle state are time point 4 and time point 12, FIG. 3 is a block diagram of a conventional apparatus for generating a digital wave. Referring to FIG. 3, the digital wave generating apparatus 300 comprises a counter 310, comparators C1, C2, a multiplexer 312 and flip-flop 314. The counter 310 is used for receiving a high frequency clock signal CLKn. When the high frequency clock signal CLKn finishes one periodic cycle, the counting value C to be outputted from the counter 310 is added by 1. The period of the high frequency clock signal CLKn is one-nth of the writing period T. The comparator C1 is coupled to the counter 310 for receiving the counting value C and the select signal S1 and outputting a comparison signal P1. The comparator C2 is coupled to the counter 310 for receiving the counting value C and the select signal S2 and outputting a comparison signal P2.

[0010] The select signal S1 is used for determining the time point at which the digital wave W is toggled from the low level to the high level. The select signal S2 is used for determining the time point that the digital wave W is toggled from the high level to the low level. The multiplexer 312 is coupled to the comparators C1 and C2 for receiving the comparison signals P1 and P2, and then outputting the multiplexing signal m. When the digital wave W is at the low level, the multiplexer 312 outputs the comparison signal P1. When the digital wave W is at the high level, the multiplexer 312 outputs the comparison signal P2. The flip-flop 314 is coupled to the multiplexer 312 for receiving the multiplexing signal m and outputting the digital wave W. When the multiplexing signal m is toggled from the low level to the high level, the digital wave W to be outputted from the flip-flop 314 is also toggled.

[0011] Accordingly, the conventional apparatus for generating the highly accurate digital wave requires a high frequency clock signal, having the disadvantages of high cost and being difficult to control the accuracy.

[0012] According to the foregoing description, an object of this invention is to provide an apparatus for generating a highly accurate digital wave by using a low frequency clock signal and the method thereof.

[0013] Therefore, the invention is to provide an apparatus for generating a digital wave. A period of a basic clock signal is divided into a plurality of time points, and the level of the highly accurate digital wave is toggled at these time points. The apparatus comprises a delay phase lock loop, for generating a plurality of delayed clock signals according to the basic clock signal. The apparatus further comprises a first multiplexer and a second multiplexer, each for outputting one of the delayed clock signals according to the first and the second select signals, respectively. The apparatus further comprises the first and the second edge-triggered flip-flops, for receiving output signals of the first and the second multiplexer respectively. The apparatus further comprises a logic gate for outputting the digital wave according to the outputs of the first and the second edge-toggled flip-flops. The digital wave is toggled according to the first select signal, and then further toggled according to the second select signal.

[0014] While the specification concludes with claims particularly pointing out the subject matter which is regarded as the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:

[0015] FIG. 1 is a diagram showing the variation of the power of the optical signal for recording corresponding to a data area of the optical disc;

[0016] FIG. 2 is an example of a highly accurate digital wave;

[0017] FIG. 3 is a block diagram of a conventional apparatus for generating a digital wave;

[0018] FIG. 4 is a block diagram of an apparatus for generating a digital wave according to one preferred embodiment of the invention; and

[0019] FIG. 5 is a timing diagram for the apparatus for generating a digital wave in FIG. 4.

[0020] Referring to FIG. 4, it is a block diagram of an apparatus for generating a digital wave according to one preferred embodiment of the invention. The apparatus 400 for generating a digital wave is used for generating a highly accurate digital wave W. A basic period of a basic wave can be divided into n time points, and the level of the digital wave W is toggled at these time points, in which n is an integral and has a value 20 as an example in this embodiment. The apparatus 400 for generating a digital wave comprises a delay phase lock loop (DLL) 402, multiplexers M1 and M2, logic gates 404 and 405, FIFOs 406 and 408, edge-triggered flip-flops F1 and F2, and a logic gate 409 (such as an XOR gate). The DLL 402 is used for generating n clock signals CK0˜CKn−1 according to a basic clock signal CK0. The phase difference between adjacent clock signals is 2×π/n (or the basic period/n), i.e., the phase difference between the clock signal CKm and the clock signal CKm+1 is 2×π/n, in which m is an integral small than n. The multiplexer M1 is coupled to the DLL 402 for receiving the clock signals CK0˜CKn−1, and then selects one of these clock signals CK0˜CKn−1 as an output signal OUT1 according to a select signal SSet. The select signal SSet is used for determining a time point at which the digital wave W is toggled from a low level to a high level. According to FIG. 4, the logic gate 405 is composed of an inverter and an AND gate, which is understood to those skilled in the art and their descriptions are omitted. The logic gate 405 receives the output signal OUT1 and the digital wave W that is feedback to the logic gate 405, to generate a first triggering signal S. The edge-triggered flip-flop F1 is triggered by the first triggering signal S, and outputs an output signal Q_F1 at the terminal Q to the logic gate 409 (such as the XOR gate), wherein the input terminal D of the flip-flop F1 is connected to its output terminal QN.

[0021] Similarly, the multiplexer M2 is coupled to the DLL 402 for receiving the clock signals CK0˜CKn−1, and selects one of these clock signals CK0˜CKn−1 as an output signal OUT2 according to a select signal RSet, in which the select signal is used for determining a time point that the digital wave W is toggled from a high level to a low level. The logic gate 404 receives the output signal OUT2 and the digital wave W that is fed back to the logic gate 404, to generate a second triggering signal R. The edge-triggered flip-flop F2 is triggered by the second triggering signal R, and outputs an output signal Q_F2 at the terminal Q to the logic gate 409 (such as the XOR gate), wherein the input terminal D of the flip-flop F2 is connected to its output terminal QN.

[0022] According to the invention, trigger points at the rising edge and the falling edge of the digital wave W can be set. Referring to FIG. 4, the FIFO 408 and the FIFO 406 receive the S_DATA (for setting the trigger point at the rising edge of the digital wave W) and the R_DATA (for setting the trigger point at the falling edge of the digital wave W) respectively. The FIFO 408 further receives the clock signal CK0 and the first triggering signal S output from the logic gate 405. The clock signal CK0 is used for triggering the FIFI 408 to receive the S_DATA, and the first triggering signal S is used for triggering the FIFO 408 to output the select signal SSet to the multiplexer M1. For example, if the digital wave W is required to be triggered at the rising edge at CK1 and CK3 respectively, the S_DATA is 1 and 3 respectively, wherein 1 and 3 represent the clock signals CK1 and CK3. Similarly, the FIFO 406 further receives the clock signal CK0 and the second triggering signal R output from the logic gate 404. The clock signal CK0 is used for triggering the FIFI 406 to receive the R_DATA, and the second triggering signal R is used for triggering the FIFO 406 to output the select signal RSet to the multiplexer M2. For example, if the digital wave W is required to be triggered at the falling edge at CK5 and CK19 respectively, the R_DATA is 5 and 19 respectively, wherein 5 and 19 represent the clock signals CK5 and CK19.

[0023] Next, the following describes how the digital wave W is generated. Referring to FIG. 5, it is a timing diagram for the apparatus 400 for generating a digital wave in FIG. 4. The phase difference between adjacent two of the clock signals CK0˜CKn−1 output from the DLL 402 is 2×π/n. In the following description, in certain one period, the digital wave W needs to be toggled to a high level at time point 1 and toggled to a low level at time point 5. In the next period, the digital wave W needs to be toggled to a high level at time point 3 and toggled to a low level at time point 19.

[0024] First, when no clock signals are outputted from the multiplexers M1 and M2, the signals S and R are low levels, so that the digital wave W is a low level. When the multiplexer M1 outputs the clock signal CK1 according to the select signal SSet and after being processed by the logic gate 405, the first triggering signal S becomes a high level. According to the invention, in order to prevent the accuracy of the digital wave W from being affected, the FIFO 408 will transmit the next select signal SSet to the multiplexer M1 after the first triggering signal S becomes the high level. The high level of the signal S makes the output Q_F1 of the edge triggered flip-flop F1 change to the high level. Next, the digital wave W will be toggled from the low level to the high level because the output Q_F1 is toggled. The high level of the digital wave W is then feedback to the logic gate 405 so that the first triggering signal S is toggled to the low level again.

[0025] Similarly, when the multiplexer M2 outputs the clock signal CK5 according to the select signal RSet and after being processed by the logic gate 404, the second triggering signal R becomes a high level. According to the invention, in order to prevent the accuracy of the digital wave W from being affected, the FIFO 406 will transmit the next select signal RSet to the multiplexer M2 after the second triggering signal R becomes the high level. The high level of the signal R makes the output Q_F2 of the edge triggered flip-flop F2 toggled to the high level. Next, the digital wave W will be toggled from the high level to the low level because the output Q_F2 is toggled. The low level of the digital wave W is then feedback to the logic gate 404 so that the second triggering signal R is toggled to the low level again.

[0026] Similarly, the next cycle is proceeded in the same way so that the digital wave W can be toggled to a high level at time point 3, and toggled to a low level at time point 19.

[0027] The aforementioned embodiment is the best embodiment according to the invention, but the embodiment without the FIFO 406, 408, logic gate 404 and 405 can also generate the digital wave W. The edge-triggered flip-flop F1 receives a delayed clock signal, which determines the rising time of the digital wave. At the rising time, the edge-triggered flip-flop F1 is triggered to change the state of the digital wave W. The edge-triggered flip-flop F2 receives another delayed clock signal, which determines the falling time of the digital wave W. At the falling time, the edge-triggered flip-flop F2 is triggered to change the state of the digital wave W.

[0028] The logic gate 405, edge-triggered flip-flop F1 and the FIFO 408 can be considered as a first processing apparatus; the logic gate 404, edge-triggered flip-flop F2 and FIFO 406 can be considered as a second processing apparatus. The first processing apparatus and the second apparatus output Q_F1 and Q_F2 respectively for outputting the digital wave W via the logic gate 409.

[0029] In the above embodiment, other devices can be used for replacing the DLL 402, such as a voltage controlled oscillator (VCO). Additionally, if the digital wave W requires to be triggered more than twice within one period of the basic clock signal CK0, the frequency of the basic clock signal CK0 can be properly divided and the phase of the frequency-divided basic clock signal CK0 is then delayed on demand.

[0030] According to the invention, the apparatus for generating the digital wave uses the low frequency clock signal to generate a highly accurate digital wave, so that the cost can be saved in comparison with the conventional apparatus that uses the high frequency clock signal.

[0031] While the present invention has been described with a preferred embodiment, this description is not intended to limit our invention. Various modifications of the embodiment will be apparent to those skilled in the art. Therefore the appended claims should be accorded the broadest interpretation so as to cover any such modifications or embodiments within the scope of the invention.