Reliability monitor for a memory array

[0002] A memory cell may be a flash memory cell made of field effect transistors (FETs) that each include a select gate, a floating gate, a drain, and a source. Each memory cell may be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched “on” and “off.” Each memory cell in an array of memory cells store a “1” or a “0. ” Multi-level cells can store more than a single bit of data.

[0003] Programming a cell includes trapping excess electrons in the floating gate to increase the voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the cell current is less than a reference current and the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.

[0004] A memory array may include multiple pages that are individually accessible. For example, a memory array may contain 64 pages and each page may contain 1 KB of memory cells. Each memory cell may be accessed by making the page that contains the memory cell the active memory page, then accessing the memory cell by selecting the row and column in the memory page that corresponds to the memory cell. The latency of making a memory page active is generally much larger than the access time of a memory cell. For example the page latency may be 3 microseconds while the cell access time may be only 50 nanoseconds.

[0005] A error may occur in a memory cell due to internal defects, normal use over a long period of time, non-use for a long period of time, or other factors. Two of the primary data reliability issues for memory cells are the “data retention” effect and “read disturb” effect. The “data retention” effect is a shift in the stored voltage level toward the erase state that results from the normal passage of time. The “read disturb” effect is a shift in the stored voltage level that results from reading the memory cell. For the read disturb effect to be appreciable, many reads must occur. When the stored voltage level shifts too far in either direction, it will be interpreted as representing the next higher or lower voltage level and thus the data will be misread.

[0006] An error checking and correction (ECC) circuit detects and optionally corrects errors in a memory array. An ECC circuit typically partitions a memory page into groups of memory cells and checks each group of memory cells independently and then generates a syndrome that indicates which memory cells had errors in each group. For example, a page of memory with 1 KB of memory cells may have 64 groups each containing 16 bytes of memory cells. Based on the algorithm of the ECC circuit and the size of the group, the memory cells in the group can be corrected if the total number of errors in the group is below a threshold. An ECC circuit typically generates a syndrome for each group that indicates which memory cells have errors. A syndrome that contains all zeros indicates that no errors were detected. If the number of errors in a group exceeds the threshold, none of the errors can be repaired. For example, the maximum number of errors that can be corrected in a memory array may be:

[0007] The reliability of a memory array is dependent on many factors, some of which are process-dependent. Therefore, it is desirable to periodically test memory arrays to ensure that the manufacturing processes is functioning properly. Currently, complex and expensive test equipment must be connected with the memory array to test the reliability of the memory array. Also, the external test equipment typically cause delays during testing. These delays significantly lengthen the testing period for tests such as “read disturb” tests.

[0008] An integrated reliability monitor automatically tests a memory device until a threshold number of errors are detected. The integrated reliability monitor eliminates the need for sophisticated external test equipment by automatically testing the memory cells in the memory array and providing the results. Optional programmable registers may store the error threshold value. The programmable registers may also store a time-out value or the reliability monitor may be externally interrupted.

[0009] The present invention is described with reference to the accompanying figures. In the figures, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears.

[0010] FIG. 1 is a block diagram of a memory device that includes a reliability monitor;

[0011] FIG. 2 is a flow diagram of a method of testing a memory device; and

[0012] FIG. 3 is a circuit diagram of the reliability monitor.

[0013] In order to reduce the complexity of external test equipment and speed up memory testing, it is desirable to have an integrated mechanism to automatically test a memory array. Certain memory tests require a large number of iterations to complete. Such tests are best performed by an integrated and automated test controller. An example of such a test is a “read disturb” test that tests how many times a memory array can be read before an error is detected. Alternatively, the “read disturb” test may be executed until a threshold number of errors are detected. For example, the error threshold may be 1, 2, 4, 8, 16, 64, or some other value. Alternatively, the error threshold may be a percentage of the memory array, such as 1 % or the error threshold can be dynamic and vary over time. The error threshold may decrease over time to zero and thus act as a timeout mechanism. A write-read test repeatedly writes and reads the memory array until the number of detected errors reaches or exceeds an error threshold. Other tests may also be used to test the memory array.

[0014] FIG. 1 is a block diagram of a memory device 100 that includes a memory array 102 and a reliability monitor 104. The memory array 102 may include flash memory cells, DRAM memory cells, SRAM memory cells, or other types of memory cells. In one embodiment, the memory array 102 includes pages of memory cells.

[0015] The reliability monitor 104 is an integrated and automated test controller that may include an ECC circuit 106, a counter circuit 108 and optional registers 110. The ECC circuit 106 checks the memory array for errors and optionally repairs any detected error. The ECC circuit 106 may operate autonomously or under the control of the counter circuit 108. The ECC circuit 106 preferably checks the memory array 102 on a group-by-group basis where the memory array 102 is divided into memory pages that are subdivided into groups. The ECC circuit 102 may use one or more error detection methods to determine if an error has occurred. For example, a cyclic redundancy check (CRC) using a Reed-Solomon algorithm may be used. The ECC circuit 106 may test a single group of memory or all the groups in page or the entire memory array 102. In one embodiment, the entire memory array 102 is tested sequentially one group at a time. Alternative, the entire memory array 102 can be tested following a non-sequential pattern such as a random or pseudorandom pattern. Other testing patterns can also be used such as testing each group sequentially but running the test several times on each group before proceeding to the next test. Once an error is detected, that memory cell or group can optionally be omitted from subsequent testing. Such a test determines the number of cycles before the error threshold is reached due to errors in different memory cells. This test may require a more sophisticated testing algorithm and consequentially may be slower. Other variations and combinations of such tests may also be used to test the memory array 102.

[0016] The counter circuit 108 counts the number of errors detected by the ECC circuit 106. Optionally, the number of errors may be stored in one of the registers 110. The counter circuit 108 may control the ECC circuit 106 such that the counter circuit 108 All begins and ends the memory testing. The counter circuit 108 may compare the number of errors counted to an error threshold stored in one of the registers 110. In another embodiment, the counter circuit 108 is configured with the error threshold built-in. Alternatively, the counter circuit 108 may be integrated with the ECC circuit 106.

[0017] The reliability monitor 104 may have various external interfaces, for example, “Interrupt” and “Ready/Busy” signals are received at interface nodes 112 and 114, respectively. In one embodiment, the interfaces nodes 112 and 114 are connected with the counter circuit 108. The Ready/Busy signal, also called the “Ready” signal, is an output signal transmitted at interface node 114. The reliability monitor 104 can lower the Ready/Busy signal to indicate a test is in progress then raise the signal once the test has terminated. In an embodiment that includes such a Ready/Busy signal, the Ready/Busy signal may be used to measure the duration of the test. It is preferred that the length of the test is a known constant value, such that the number of cycles completed in the test can be calculates by Eqn. 3.

[0018] #Cycles=Test Duration/Test Length  Eqn. 3

[0019] The optional Interrupt signal is received at interface nodes 112 and interrupts the reliability monitor 104 during a memory test. The Interrupt signal can be used as a timeout mechanism to stop a memory test that has not detected enough errors to automatically terminate. In another embodiment, the Interrupt and Ready/Busy signals are received and transmitted at a single interface node. A timeout mechanism can be used in conjunction with or in place of the Interrupt signal. The timeout mechanism would terminate the testing after a timeout threshold is reached.

[0020] FIG. 2 is a flow diagram of a method 200 of testing a memory device. In 202, the memory cells in a memory array are tested for errors. One such test is the read disturb test that is performed sequentially across the entire memory array. The testing may be performed by an ECC circuit. Optionally, the errors detected are corrected.

[0021] In 204, the number of errors detected are counted. Since the cells are normally tested in groups, the number of errors detected can increase by one or more for each group tested.

[0022] In 206, the number of errors detected is compared to the error threshold. If the number of errors is less than the error threshold then the testing continues. If the number of errors is equal to or greater than the error threshold then the testing is terminated.

[0023] In 208, an indication that the test has ended is optionally transmitted. Alternatively, the length of the test in time or cycle count can be stored in a register for later access by external test equipment.

[0024] FIG. 3 is a circuit diagram of an embodiment of an ECC error counter 300. An error signal indicating an error has been detected is received at the input node 302 and the counter output is transmitted from output node 304. The ECC error counter 300 may include four registers 310-316 connected with a look ahead circuit 318. A second set of four registers 320-326 are connected to a second look ahead circuit 328. The ECC error counter 300 may be implemented in Verilog as follows:

[0025] While preferred embodiments have been shown and described, it will be understood that they are not intended to limit the disclosure, but rather it is intended to cover all modifications and alternative methods and apparatuses falling within the spirit and scope of the invention as defined in the appended claims or their equivalents.