Audio signal processing apparatus

[0002] This application is a divisional of U.S. application Ser. No. 09/394,688, filed Sep. 13, 1999 now U.S. Pat. No. 6,463,410.

[0003] 1. Field of the Invention

[0004] This invention relates to an audio signal encoding apparatus. This invention also relates to an optical recording medium. In addition, this invention relates to an audio signal decoding apparatus. Furthermore, this invention relates to a method of transmitting an audio signal.

[0005] 2. Description of the Related Art

[0006] Highly efficient encoding of an audio signal includes a step of compressing the audio signal. Highly efficient encoding techniques are classified into two types; the lossy encoding techniques and the lossless encoding techniques. Among the lossy encoding techniques, the “acoustic encoding” is well known as a technique which renders the data deterioration acoustically undetectable. On the other hand, according to the lossless encoding and decoding techniques, the recovered data are exactly the same as the original data.

[0007] In general, a sampled or uniformly quantized audio signal has significant redundancy. During the encoding of such an audio signal, the degree of the compression of the audio signal rises as redundancy is more effectively removed therefrom.

[0008] It is a first object of this invention to provide an audio signal encoding apparatus having a higher compression performance.

[0009] It is a second object of this invention to provide an improved optical recording medium.

[0010] It is a third object of this invention to provide an improved audio signal decoding apparatus.

[0011] It is a fourth object of this invention to provide an improved method of transmitting an audio signal.

[0012] A first aspect of this invention provides an audio signal encoding apparatus comprising means for adding a first audio signal and a second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals.

[0013] A second aspect of this invention is based on the first aspect thereof, and provides an audio signal encoding apparatus further comprising means for generating a variable-rate bit stream in response to the first minimum prediction-error signal and the second minimum prediction-error signal.

[0014] A third aspect of this invention provides an audio signal decoding apparatus for processing a first minimum prediction-error signal and a second minimum prediction-error signal which are generated by an audio signal encoding apparatus comprising means for adding a first audio signal and a second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals. The audio signal decoding apparatus comprises means for recovering the addition-result signal from the first minimum prediction-error signal; means for recovering the subtraction-result signal from the second minimum prediction-error signal; and means for recovering the first audio signal and the second audio signal from the recovered addition-result signal and the recovered subtraction-result signal.

[0015] A fourth aspect of this invention provides a method comprising the steps of adding a first audio signal and a second audio signal into an addition-result signal; subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; generating a first difference signal representing a difference in the addition-result signal; generating a second difference signal representing a difference in the subtraction-result signal; generating first different prediction signals for the first difference signal, respectively; generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; generating second different prediction signals for the second difference signal, respectively; generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals; and transmitting the first minimum prediction-error signal and the second minimum prediction-error signal to a communication line.

[0016] A fifth aspect of this invention provides an optical recording medium storing formatted information of a first minimum prediction-error signal and a second minimum prediction-error signal which are generated by an audio signal encoding apparatus comprising means for adding a first audio signal and a second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals.

[0017] A sixth aspect of this invention provides a method of network-based transmission which comprises the steps of adding a first audio signal and a second audio signal into an addition-result signal; subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; generating a first difference signal representing a difference in the addition-result signal; generating a second difference signal representing a difference in the subtraction-result signal; generating first different prediction signals for the first difference signal, respectively; generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; generating second different prediction signals for the second difference signal, respectively; generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals; and transmitting the first minimum prediction-error signal and the second minimum prediction-error signal to a communication line.

[0018] A seventh aspect of this invention provides an audio signal encoding apparatus comprising means for selecting a first audio signal and a second audio signal from among signals composing a multi-channel audio signal; means for adding the first audio signal and the second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals.

[0019] An eighth aspect of this invention is based on the seventh aspect thereof, and provides an audio signal encoding apparatus further comprising means for generating a variable-rate bit stream in response to the first minimum prediction-error signal and the second minimum prediction-error signal.

[0020] A ninth aspect of this invention provides an audio signal decoding apparatus for processing a first minimum prediction-error signal and a second minimum prediction-error signal which are generated by an audio signal encoding apparatus comprising means for selecting a first audio signal and a second audio signal from among signals composing a multi-channel audio signal; means for adding the first audio signal and the second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals. The audio signal decoding apparatus comprises means for recovering the addition-result signal from the first minimum prediction-error signal; means for recovering the subtraction-result signal from the second minimum prediction-error signal; and means for recovering the first audio signal and the second audio signal from the recovered addition-result signal and the recovered subtraction-result signal.

[0021] A tenth aspect of this invention provides a method comprising the steps of selecting a first audio signal and a second audio signal from among signals composing a multi-channel audio signal; adding the first audio signal and the second audio signal into an addition-result signal; subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; generating a first difference signal representing a difference in the addition-result signal; generating a second difference signal representing a difference in the subtraction-result signal; generating first different prediction signals for the first difference signal, respectively; generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; generating second different prediction signals for the second difference signal, respectively; generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals; and transmitting the first minimum prediction-error signal and the second minimum prediction-error signal to a communication line.

[0022] An eleventh aspect of this invention provides an optical recording medium storing formatted information of a first minimum prediction-error signal and a second minimum prediction-error signal which are generated by an audio signal encoding apparatus comprising means for selecting a first audio signal and a second audio signal from among signals composing a multi-channel audio signal; means for adding the first audio signal and the second audio signal into an addition-result signal; means for subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; means responsive to the addition-result signal for generating a first difference signal representing a difference in the addition-result signal; means responsive to the subtraction-result signal for generating a second difference signal representing a difference in the subtraction-result signal; a plurality of first predictors having different prediction characteristics respectively and being responsive to the first difference signal for generating first different prediction signals for the first difference signal, respectively; a plurality of first subtracters for generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; means for selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; a plurality of second predictors having different prediction characteristics respectively and being responsive to the second difference signal for generating second different prediction signals for the second difference signal, respectively; a plurality of second subtracters for generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; and means for selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals.

[0023] A twelfth aspect of this invention provides a method of network-based transmission which comprises the steps of selecting a first audio signal and a second audio signal from among signals composing a multi-channel audio signal; adding the first audio signal and the second audio signal into an addition-result signal; subtracting the first audio signal from the second audio signal, and generating a subtraction-result signal; generating a first difference signal representing a difference in the addition-result signal; generating a second difference signal representing a difference in the subtraction-result signal; generating first different prediction signals for the first difference signal, respectively; generating first prediction-error signals representing differences between the first difference signal and the first different prediction signals, respectively; selecting a first minimum prediction-error signal representative of a smallest difference from among the first prediction-error signals; generating second different prediction signals for the second difference signal, respectively; generating second prediction-error signals representing differences between the second difference signal and the second different prediction signals, respectively; selecting a second minimum prediction-error signal representative of a smallest difference from among the second prediction-error signals; and transmitting the first minimum prediction-error signal and the second minimum prediction-error signal to a communication line.

[0024] FIG. 1 is a block diagram of a system including an audio signal encoding apparatus and an audio signal decoding apparatus according to a first embodiment of this invention.

[0025] FIG. 2 is a block diagram of a lossless encoder in FIG. 1.

[0026] FIG. 3 is a diagram of the format of a 1-frame-corresponding segment of a variable-rate bit stream generated by the audio signal encoding apparatus in FIG. 1.

[0027] FIG. 4 is a block diagram of a lossless decoder in FIG. 1.

[0028] FIG. 5 is a block diagram of a lossless encoder in a second embodiment of this invention.

[0029] FIG. 6 is a block diagram of a lossless decoder in the second embodiment of this invention.

[0030] FIG. 7 is a block diagram of an audio signal encoding apparatus in a third embodiment of this invention.

[0031] FIG. 8 is a block diagram of an audio signal decoding apparatus in the third embodiment of this invention.

[0032] FIG. 9 is a block diagram of a system according to a fourth embodiment of this invention.

[0033] FIG. 10 is a diagram of the structure of an audio pack.

[0034] FIG. 11 is a diagram of the structure of the audio pack.

[0035] FIG. 12 is a block diagram of a system according to a fifth embodiment of this invention.

[0036] FIG. 13 is a flowchart of a segment of a control program for a packeting processor in FIG. 12.

[0037] FIG. 14 is a flowchart of a segment of a control program for a de-packeting processor in FIG. 12.

[0038] FIG. 15 is a block diagram of a system including an audio signal encoding apparatus and an audio signal decoding apparatus according to a sixth embodiment of this invention.

[0039] FIG. 16 is a diagram of the format of a 1-frame-corresponding segment of a variable-rate bit stream generated in the system of FIG. 15.

[0040] FIG. 17 is a block diagram of a system including an audio signal encoding apparatus and an audio signal decoding apparatus according to a seventh embodiment of this invention.

[0041] FIG. 18 is a diagram of the format of a 1-frame-corresponding segment of a variable-rate bit stream generated in the system of FIG. 17.

[0042] FIG. 19 is a block diagram of a system including an audio signal encoding apparatus and an audio signal decoding apparatus according to an eighth embodiment of this invention.

[0043] FIG. 20 is a block diagram of a system including an audio signal encoding apparatus and an audio signal decoding apparatus according to a ninth embodiment of this invention.

[0044] With reference to FIG. 1, an audio signal encoding apparatus 100 includes a channel correlation circuit “A” and a lossless encoder 2D. An audio signal decoding apparatus 200 includes a channel correlation circuit “B” and a lossless decoder 3D. The audio signal encoding apparatus 100 and the audio signal decoding apparatus 200 are connected via a transmission line 250.

[0045] The audio signal encoding apparatus 100 receives stereophonic 2-channel digital audio signals, that is, a left-channel digital audio signal “L” and a right-channel digital audio signal “R”. The stereophonic 2-channel digital audio signals are reproduced from a digital recording medium such as a DVD-audio (a digital versatile disc audio). The audio signal encoding apparatus 100 encodes the left-channel digital audio signal “L” and the right-channel digital audio signal “R” into encoding-resultant digital audio signals. The audio signal encoding apparatus 100 outputs the encoding-resultant digital audio signals to the transmission line 250. The encoding-resultant digital audio signals are propagated to the audio signal decoding apparatus 200 via the transmission line 250. The audio signal decoding apparatus 200 decodes the encoding-resultant digital audio signals into the original left-channel digital audio signal “L” and the original right-channel digital audio signal “R”. In other words, the audio signal decoding apparatus 200 recovers the original left-channel digital audio signal “L” and the original right-channel digital audio signal “R”. The audio signal decoding apparatus 200 outputs the recovered left-channel digital audio signal “L” and the recovered right-channel digital audio signal “R” to an external apparatus.

[0046] The channel correlation circuit “A” in the audio signal encoding apparatus 100 includes an addition circuit 1aand a subtraction circuit 1b. The addition circuit 1areceives the left-channel digital audio signal “L” and the right-channel digital audio signal “R”. The left-channel digital audio signal “L” results from quantization of a left-channel analog audio signal at a predetermined sampling frequency and a predetermined quantization bit number. The predetermined sampling frequency is equal to, for example, 192 kHz. The predetermined quantization bit number is equal to, for example, 24. Similarly, the right-channel digital audio signal “R” results from quantization of a right-channel analog audio signal at the predetermined sampling frequency and the predetermined quantization bit number. The addition circuit la adds the left-channel digital audio signal “L” and the right-channel digital audio signal “R” into an addition-result signal (L+R). The addition-result signal (L+R) is a PCM (pulse code modulation) signal. The addition circuit la outputs the addition-result signal (L+R) to the lossless encoder 2D. The subtraction circuit 1breceives the left-channel digital audio signal “L” and the right-channel digital audio signal “R”. The subtraction circuit 1bsubtracts the right-channel digital audio signal “R” from the left-channel digital audio signal “L”, thereby generating a subtraction-result signal (L−R). The subtraction-result signal (L−R) is a PCM signal. The subtraction circuit 1boutputs the subtraction-result signal (L−R) to the lossless encoder 2D.

[0047] As shown in FIG. 2, the lossless encoder 2D includes a buffer (a memory) 10. A sequence of samples of the addition-result signal (L+R) and a sequence of samples of the subtraction-result signal (L−R) are applied to the buffer 10. The addition-result signal (L+R) and the subtraction-result signal (L−R) are stored into the buffer 10 frame by frame. Every frame is composed of a predetermined number of successive samples.

[0048] Samples of the addition-result signal (L+R) are sequentially transmitted from the buffer 10 to a difference calculation circuit 11D1. The difference calculation circuit 11D1 generates a signal Δ(L+R) representing the difference between the current sample of the addition-result signal (L+R) and the immediately preceding sample thereof. The difference calculation circuit 11D1 outputs the difference signal Δ(L+R) to a prediction circuit 15D1 sample by sample. In other words, the differential calculation circuit 11D1 implements differential pulse code modulation (DPCM) of the addition-result signal (L+R), and outputs the resultant DPCM signal Δ(L+R).

[0049] Samples of the subtraction-result signal (L−R) are sequentially transmitted from the buffer 10 to a difference calculation circuit 11D2. The difference calculation circuit 11D2 generates a signal Δ(L−R) representing the difference between the current sample of the subtraction-result signal (L−R) and the immediately preceding sample thereof. The difference calculation circuit 11D2 outputs the difference signal Δ(L−R) to a prediction circuit 15D2 sample by sample. In other words, the differential calculation circuit 11D2 implements differential pulse code modulation (DPCM) of the subtraction-result signal (L−R), and outputs the resultant DPCM signal Δ(L−R).

[0050] For every frame, the first sample of the addition-result signal (L+R) and the first sample of the subtraction-result signal (L−R) are transmitted from the buffer 10 to a multiplexer 19.

[0051] The prediction circuit 15D1 includes predictors 12a-1, 12a-2, . . . , and 12a-n, and subtracters 13a-1, 13a-2, . . . , and 13a-n, where “n” denotes a predetermined natural number equal to or greater than 2. The predictors 12a-1, 12a-2, . . . , and 12a-nreceive every sample of the difference signal Δ(L+R) from the difference calculation circuit 11D1. Also, the subtracters 13a-1, 13a-2, . . . , and 13a-nreceive every sample of the difference signal Δ(L+R) from the difference calculation circuit 11D1. The predictors 12a-1, 12a-2, . . . , and 12a-nhave different prediction characteristics, respectively. Specifically, the predictors 12a-1, 12a-2, . . . , and 12a-nare different from each other in prediction coefficients. Each of the predictors 12a-1, 12a-2, . . . , and 12a-npredicts a current sample of the difference signal Δ(L+R) from preceding samples thereof in response to the related prediction coefficients. Thus, the predictors 12a-1, 12a-2, . . . , and 12a-ngenerate prediction-result signals for the difference signal Δ(L+R) in response to the prediction coefficients, respectively. The predictors 12a-1, 12a-2, . . . , and 12a-noutput the prediction-result signals to the subtracters 13a-1, 13a-2, . . . , and 13a-nrespectively. For every sample, each of the subtracters 13a-1, 13a-2, . . . , and 13a-nsubtracts the related prediction-result signal from the difference signal Δ(L+R), and hence generates a signal representing the prediction error between the prediction-result signal and the difference signal Δ(L+R). The subtracters 13a-1, 13a-2, . . . , and 13a-noutput the respective prediction-error signals to a buffer and selector 16D1.

[0052] The prediction-error signals, that is, the output signals of the subtracters 13a-1, 13a-2, . . . , and 13a-n, are temporarily stored in a memory within the buffer and selector 16D1. A selection signal generator 17 produces a first selection signal. The selection signal generator 17 outputs the first selection signal to the buffer and selector 16D1. The first selection signal is designed to select the smallest one from among the prediction-error signals in the memory of the buffer and selector 16D1 as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D1 for the smallest prediction-error signal. In more detail, for every sub-frame, the sums of the values represented by samples of the respective prediction-error signals are calculated. The calculated sums are compared to determine the smallest one which corresponds to the smallest prediction-error signal to be selected. The selection signal generator 17 enables the buffer and selector 16D1 to output the smallest prediction-error signal from the memory to a packing circuit 18 as the selected (L+R)-related prediction-error signal for every sub-frame.

[0053] Every sub-frame is composed of a predetermined number of successive samples. Several tens of successive sub-frames compose one frame. For example, 80 successive sub-frames compose one frame.

[0054] The prediction circuit 15D2 includes predictors 12b-1, 12b-2, . . . , and 12b-n, and subtracters 13b-1, 13b-2, . . . , and 13b-n. The predictors 12b-1, 12b-2, . . . , and 12b-nreceive every sample of the difference signal Δ(L−R) from the difference calculation circuit 11D2. Also, the subtracters 13b-1, 13b-2, . . . , and 13b-nreceive every sample of the difference signal Δ(L−R) from the difference calculation circuit 11D2. The predictors 12b-1, 12b-2, . . . , and 12b-nhave different prediction characteristics, respectively. Specifically, the predictors 12b-1, 12b-2, . . . , and 12b-nare different from each other in prediction coefficients. Each of the predictors 12b-1, 12b-2, . . . , and 12b-npredicts a current sample of the difference signal Δ(L−R) from preceding samples thereof in response to the related prediction coefficients. Thus, the predictors 12b-1, 12b-2, . . . , and 12b-ngenerate prediction-result signals for the difference signal Δ(L−R) in response to the prediction coefficients, respectively. The predictors 12b-1, 12b-2, . . . , and 12b-noutput the prediction-result signals to the subtracters 13b-1, 13b-2, . . . , and 13b-nrespectively. For every sample, each of the subtracters 13b-1, 13b-2, . . . , and 13b-nsubtracts the related prediction-result signal from the difference signal Δ(L−R), and hence generates a signal representing the prediction error between the prediction-result signal and the difference signal Δ(L−R). The subtracters 13b-1, 13b-2, . . . , and 13b-noutput the respective prediction-error signals to a buffer and selector 16D2.

[0055] The prediction-error signals, that is, the output signals of the subtracters 13b-1, 13b-2, , and 13b-n, are temporarily stored in a memory within the buffer and selector 16D2. The selection signal generator 17 produces a second selection signal. The selection signal generator 17 outputs the second selection signal to the buffer and selector 16D2. The second selection signal is designed to select the smallest one from among the prediction-error signals in the memory of the buffer and selector 16D2 as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D2 for the smallest prediction-error signal. In more detail, for every sub-frame, the sums of the values represented by samples of the respective prediction-error signals are calculated. The calculated sums are compared to determine the smallest one which corresponds to the smallest prediction-error signal to be selected. The selection signal generator 17 enables the buffer and selector 16D1 to output the smallest prediction-error signal from the memory to the packing circuit 18 as the selected (L−R)-related prediction-error signal for every sub-frame.

[0056] In addition, the selection signal generator 17 produces a first flag, for example, a first 5-bit flag representing the maximum number among the numbers of effective bits in respective samples of the selected (L+R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the first flag to the packing circuit 18 and the multiplexer 19 as an (L+R)-related bit-number flag.

[0057] Similarly, the selection signal generator 17 produces a second flag, for example, a second 5-bit flag representing the maximum number among the numbers of effective bits in respective samples of the selected (L−R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the second flag to the packing circuit 18 and the multiplexer 19 as an (L−R)-related bit-number flag.

[0058] Numerals “1”, “2”, . . . , and “n” are assigned to the predictors 12a-1, 12a-2, . . . , and 12a-n(or the subtracters 13a-1, 13a-2, . . . , and 13a-n) as identification numbers therefor, respectively. For every sub-frame, the selection signal generator 17 produces a third flag representing the optimal predictor among the predictors 12a-1, 12a-2, . . . , and 12a-n, that is, the predictor causing the selected (L+R)-related prediction-error signal. When the predetermined number “n” is equal to 9, the third flag has 3 bits. The selection signal generator 17 outputs the third flag to the multiplexer 19 as an (L+R)-related predictor-selection flag.

[0059] Similarly, numerals “1”, “2”, . . . , and “n” are assigned to the predictors 12b-1, 12b-2, . . . , and 12b-n(or the subtracters 13b-1, 13b-2, . . . , and 13b-n) as identification numbers therefor, respectively. For every sub-frame, the selection signal generator 17 produces a fourth flag representing the optimal predictor among the predictors 12a-1, 12a-2, . . . , and 12a-n, that is, the predictor causing the selected (L−R)-related prediction-error signal. When the predetermined number “n” is equal to 9, the fourth flag has 3 bits. The selection signal generator 17 outputs the fourth flag to the multiplexer 19 as an (L−R)-related predictor-selection flag.

[0060] For every sub-frame, the packing circuit 18 packs each of samples of the selected (L+R)-related prediction-error signal into bits, the number of which is equal to the maximum bit number represented by the (L+R)-related bit-number flag. The packing circuit 18 outputs every packing-resultant sample of the selected (L+R)-related prediction-error signal to the multiplexer 19. In addition, for every sub-frame, the packing circuit 18 packs each of samples of the selected (L−R)-related prediction-error signal into bits, the number of which is equal to the maximum bit number represented by the (L−R)-related bit-number flag. The packing circuit 18 outputs every packing-resultant sample of the selected (L−R)-related prediction-error signal to the multiplexer 19.

[0061] A signal generator 20 periodically produces a signal representing a predetermined frame header having, for example, 40 bits. The signal generator 20 outputs the frame-header signal to the multiplexer 19.

[0062] The multiplexer 19 receives the frame-header signal from the signal generator 20 for every frame. The multiplexer 19 receives the first sample of the addition-result signal (L+R) and the first sample of the subtraction-result signal (L−R) from the buffer 10 for every frame. The multiplexer 19 receives the (L+R)-related predictor-selection flag and the (L−R)-related predictor-selection flag from the selection signal generator 17 for every sub-frame. The multiplexer 19 receives the (L+R)-related bit-number flag and the (L−R)-related bit-number flag from the selection signal generator 17 for every sub-frame. The multiplexer 19 receives every packing-resultant sample of the selected (L+R)-related prediction-error signal and every packing-resultant sample of the selected (L−R)-related prediction-error signal from the packing circuit 18. The multiplexer 19 multiplexes the received signals and flags into a variable-rate bit stream on a time sharing basis. The multiplexer 19 outputs the variable-rate bit stream to the transmission line 250 (see FIG. 1). The variable-rate bit stream represents a sequence of variable-bit-number frames.

[0063] FIG. 3 shows the format of every frame of the variable-rate bit stream outputted from the multiplexer 19. As shown in FIG. 3, a starting portion of every frame has the 40-bit frame header. The 40-bit frame header is successively followed by the 25-bit first sample of the addition-result signal (L+R), the 25-bit first sample of the subtraction-result signal (L−R), a set of the 80 (L+R)-related predictor-selection flags each having 3 bits, a set of the 80 (L−R)-related predictor-selection flags each having 3 bits, a set of the 80 (L+R)-related bit-number flags each having 5 bits, and a set of the 80 (L−R)-related bit-number flags each having 5 bits. A set of the 80 (L−R)-related bit-number flags is successively followed by a 1-frame-corresonding set of the packing-resultant samples of the selected (L+R)-related prediction-error signal, and a 1-frame-corresponding set of the packing-resultant samples of the selected (L−R)-related prediction-error signal. Since 80 sub-frames compose one frame and the number of bits of every packing-resultant sample varies from sub-frame to sub-frame, a 1-frame-corresponding set of the packing-resultant samples of the selected (L+R)-related prediction-error signal has a variable bit number. Also, a 1-frame-corresponding set of the packing-resultant samples of the selected (L−R)-related prediction-error signal has a variable bit number.

[0064] The rate of compression of the variable-rate bit stream relative to the pair of the left-channel digital audio signal “L” and the right-channel digital audio signal “R” is equal to, for example, 59%.

[0065] As shown in FIG. 4, the lossless decoder 3D includes a demultiplexer 21 which receives the variable-rate bit stream from the transmission line 250 (see FIG. 1). A first portion of the demultiplexer 21 detects every frame header in the received variable-rate bit stream. For every frame, a second portion of the demultiplexer 21 demultiplexes, in response to the detected frame header, the received variable-rate bit stream into the first sample of the addition-result signal (L+R), the first sample of the subtraction-result signal (L−R), a set of the 80 (L+R)-related predictor-selection flags, a set of the 80 (L−R)-related predictor-selection flags, a set of the 80 (L+R)-related bit-number flags, a set of the 80 (L−R)-related bit-number flags, a 1-frame-corresponding set of the packing-resultant samples of the selected (L+R)-related prediction-error signal, and a 1-frame-corresponding set of the packing-resultant samples of the selected (L−R)-related prediction-error signal.

[0066] In the lossless decoder 3D, the demultiplexer 21 outputs the first sample of the addition-result signal (L+R) to an accumulation circuit 25afor every frame. The demultiplexer 21 outputs the first sample of the subtraction-result signal (L−R) to an accumulation circuit 25bfor every frame. The demultiplexer 21 outputs every (L+R)-related predictor-selection flag to predictors 24a-1, 24a-2, . . . , and 24a-n. The demultiplexer 21 outputs every (L−R)-related predictor-selection flag to predictors 24b-1, 24b-2, . . . , and 24b-n. The demultiplexer 21 outputs every (L+R)-related bit-number flag and every (L−R)-related bit-number flag to a de-packing circuit 22. The demultiplexer 21 outputs every packing-resultant sample of the selected (L+R)-related prediction-error signal and every packing-resultant sample of the selected (L−R)-related prediction-error signal to the de-packing circuit 22.

[0067] For every sub-frame, the de-packing circuit 22 implements the unpacking of the packing-resultant samples of the selected (L+R)-related prediction-error signal in response to the (L+R)-related bit-number flag. The de-packing circuit 22 outputs the resultant (L+R)-related prediction-error signal to an addition circuit 23a. For every sub-frame, the de-packing circuit 22 implements the unpacking of the packing-resultant samples of the selected (L−R)-related prediction-error signal in response to the (L−R)-related bit-number flag. The de-packing circuit 22 outputs the resultant (L−R)-related prediction-error signal to an addition circuit 23b.

[0068] The predictors 24a-1, 24a-2, . . . , and 24a-nhave the same characteristics as those of the predictors 12a-1, 12a-2, . . . , and 12a-nin the lossless encoder 2D, respectively. For every sub-frame, one of the predictors 24a-1, 24a-2, . . . , and 24a-nis selected in response to the (L+R)-related predictor-selection flag. Specifically, one of the predictors 24a-1, 24a-2, . . . , and 24a-nis selected which has the same characteristic as the encoder-side predictor used for the sub-frame of interest. The selected predictor generates a prediction-result signal in response to an output signal of the addition circuit 23a. The selected predictor is enabled to output the prediction-result signal to the addition circuit 23a. The addition circuit 23aadds the (L+R)-related prediction-error signal and the prediction-result signal into the difference signal Δ(L+R) which is equal to the DPCM signal Δ(L+R) outputted from the difference calculation circuit 11D1 in the lossless encoder 2D. The addition circuit 23aoutputs the difference signal Δ(L+R) to the accumulation circuit 25aand the predictors 24a-1, 24a-2, . . . , and 24a-n.

[0069] The predictors 24b-1, 24b-2, . . . , and 24b-nhave the same characteristics as those of the predictors 12b-1, 12b-2, . . . , and 12b-nin the lossless encoder 2D, respectively. For every sub-frame, one of the predictors 24b-1, 24b-2, . . . , and 24b-nis selected in response to the (L−R)-related predictor-selection flag. Specifically, one of the predictors 24b-1, 24b-2, . . . , and 24b-nis selected which has the same characteristic as the encoder-side predictor used for the sub-frame of interest. The selected predictor generates a prediction-result signal in response to an output signal of the addition circuit 23b. The selected predictor is enabled to output the prediction-result signal to the addition circuit 23b. The addition circuit 23badds the (L−R)-related prediction-error signal and the prediction-result signal into the difference signal Δ(L−R) which is equal to the DPCM signal Δ(L−R) outputted from the difference calculation circuit 11D2 in the lossless encoder 2D. The addition circuit 23boutputs the difference signal Δ(L−R) to the accumulation circuit 25band the predictors 24b-1, 24b-2, . . . , and 24b-n.

[0070] The accumulation circuit 25aaccumulates samples of the difference signal Δ(L+R) with respect to the first sample of the addition-result signal (L+R) in a frame, thereby reproducing a sequence of samples of the addition-result signal (L+R) which is equal to the output signal of the addition circuit la in the channel correlation circuit “A” of the audio signal encoding apparatus 100. The accumulation circuit 25aoutputs the reproduced addition-result signal (L+R) to the channel correlation circuit “B” (see FIG. 1).

[0071] The accumulation circuit 25baccumulates samples of the difference signal Δ(L−R) with respect to the first sample of the subtraction-result signal (L−R) in a frame, thereby reproducing a sequence of samples of the subtraction-result signal (L−R) which is equal to the output signal of the subtraction circuit 1bin the channel correlation circuit “A” of the audio signal encoding apparatus 100. The accumulation circuit 25boutputs the reproduced subtraction-result signal (L−R) to the channel correlation circuit “B” (see FIG. 1).

[0072] With reference back to FIG. 1, the channel correlation circuit “B” includes an addition circuit 4a, a subtraction circuit 4b, and ½ dividers 5aand 5b. The addition circuit 4areceives the addition-result signal (L+R) and the subtraction-result signal (L−R) from the lossless decoder 3D. The addition circuit 4aadds the addition-result signal (L+R) and the subtraction-result signal (L−R) into a signal 2L. The addition circuit 4aoutputs the signal 2L to the divider 5a. The divider 5ahalves the signal 2L, thereby reproducing the original left-channel digital audio signal “L”. The divider 5aoutputs the reproduced left-channel digital audio signal “L”. The subtraction circuit 4breceives the addition-result signal (L+R) and the subtraction-result signal (L−R) from the lossless decoder 3D. The subtraction circuit 4bsubtracts the subtraction-result signal (L−R) from the addition-result signal (L+R), thereby generating a signal 2R. The subtraction circuit 4boutputs the signal 2R to the divider 5b. The divider 5bhalves the signal 2R, thereby reproducing the original right-channel digital audio signal “R”. The divider 5boutputs the reproduced right-channel digital audio signal “R”.

[0073] A second embodiment of this invention is similar to the first embodiment thereof except for design changes mentioned later.

[0074] FIG. 5 shows a lossless encoder in the second embodiment of this invention which is a modification of the lossless encoder 2D in the first embodiment of this invention.

[0075] The lossless encoder of FIG. 5 includes prediction circuits 15A and 15S, a buffer and selector 16A, and a buffer and selector 16S. The prediction circuit 15A is similar in structure to the prediction circuit 15D1. The prediction circuit 15S is similar in structure to the prediction circuit 15D2. The buffer and selector 16A is similar in structure to the buffer and selector 16D1. The buffer and selector 16S is similar in structure to the buffer and selector 16D2.

[0076] The prediction circuit 15A receives the PCM addition-result signal (L+R) from the buffer 10. The prediction circuit 15A generates a set of PCM prediction-error signals in response to the PCM addition-result signal (L+R). The prediction circuit 15A outputs the PCM prediction-error signals to the buffer and selector 16A. The PCM prediction-error signals are temporarily stored in a memory within the buffer and selector 16A. The selection signal generator 17 outputs a selection signal to the buffer and selector 16A. The selection signal is designed to select the smallest one from among the PCM prediction-error signals in the memory of the buffer and selector 16A as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16A for the smallest PCM prediction-error signal. The smallest PCM prediction-error signal is the selected PCM (L+R)-related prediction-error signal.

[0077] In addition, the selection signal generator 17 produces an (L+R)-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected PCM (L+R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the (L+R)-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an (L+R)-related predictor-selection flag representing the optimal predictor causing the selected PCM (L+R)-related prediction-error signal. The selection signal generator 17 outputs the (L+R)-related predictor-selection flag to the multiplexer 19.

[0078] The prediction circuit 15S receives the PCM subtraction-result signal (L−R) from the buffer 10. The prediction circuit 15S generates a set of PCM prediction-error signals in response to the PCM subtraction-result signal (L−R). The prediction circuit 15S outputs the PCM prediction-error signals to the buffer and selector 16S. The PCM prediction-error signals are temporarily stored in a memory within the buffer and selector 16S. The selection signal generator 17 outputs a selection signal to the buffer and selector 16S. The selection signal is designed to select the smallest one from among the PCM prediction-error signals in the memory of the buffer and selector 16S as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16S for the smallest PCM prediction-error signal. The smallest PCM prediction-error signal is the selected PCM (L−R)-related prediction-error signal.

[0079] In addition, the selection signal generator 17 produces an (L−R)-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected PCM (L−R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the (L−R)-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an (L−R)-related predictor-selection flag representing the optimal predictor causing the selected PCM (L−R)-related prediction-error signal. The selection signal generator 17 outputs the (L−R)-related predictor-selection flag to the multiplexer 19.

[0080] For every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D1 for the smallest DPCM prediction-error signal. The smallest DPCM prediction-error signal is the selected DPCM (L+R)-related prediction-error signal. Also, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D2 for the smallest DPCM prediction-error signal. The smallest DPCM prediction-error signal is the selected DPCM (L−R)-related prediction-error signal.

[0081] Furthermore, for every sub-frame, the selection signal generator 17 decides which of the pair of the selected PCM (L+R)-related prediction-error signal and the selected PCM (L−R)-related prediction-error signal, and the pair of the selected DPCM (L+R)-related prediction-error signal and the selected DPCM (L−R)-related prediction-error signal is higher in compression rate by comparing the values represented thereby. The selection signal generator 17 selects the higher-compression pair of the (L+R)-related prediction-error signal and the (L−R)-related prediction-error signal. The selection signal generator 17 enables the higher-compression pair of the (L+R)-related prediction-error signal and the (L−R)-related prediction-error signal to be outputted to the packing circuit 18.

[0082] For every sub-frame, the selection signal generator 17 produces a prediction-circuit-selection flag representing which of the PCM prediction-error signal pair and the DPCM prediction-error signal pair is selected. The selection signal generator 17 outputs the prediction-circuit-selection flag to the multiplexer 19. The multiplexer 19 adds the prediction-circuit-selection flag into the variable-rate bit stream.

[0083] FIG. 6 shows a lossless decoder in the second embodiment of this invention which is a modification of the lossless decoder 3D in the first embodiment of this invention. The lossless decoder of FIG. 6 includes selectors 26aand 26b. The demultiplexer 21 separates every prediction-circuit-selection flag from the variable-rate bit stream. The demultiplexer 21 feeds the prediction-circuit-selection flag to the selectors 26aand 26b. When the prediction-circuit-selection flag indicates that the DPCM prediction-error signal pair is selected, the selector 26aselects the output signal of the accumulation circuit 25aand the selector 26bselects the output signal of the accumulation circuit 25b. When the prediction-circuit-selection flag indicates that the PCM prediction-error signal pair is selected, the selector 26aselects the output signal of the addition circuit 23aand the selector 26bselects the output signal of the addition circuit 23b. The signal selected by the selector 26aconstitutes the reproduced addition-result signal (L+R). The signal selected by the selector 26bconstitutes the reproduced subtraction-result signal (L−R).

[0084] A third embodiment of this invention is similar to the first embodiment thereof except for design changes mentioned later. FIG. 7 shows an audio signal encoding apparatus in the third embodiment of this invention which is a modification of the audio signal encoding apparatus 100 in the first embodiment of this invention.

[0085] The audio signal encoding apparatus of FIG. 7 includes a buffer in which a left-channel digital audio signal “L” and a right-channel digital audio signal “R” are temporarily stored. The left-channel digital audio signal “L” is fed from the buffer 10 to a prediction circuit 15L and a channel correlation circuit “A”. The right-channel digital audio signal “R” is fed from the buffer 10 to a prediction circuit 15R and the channel correlation circuit “A”. For every frame, the first sample of the left-channel digital audio signal “L” and the first sample of the right-channel digital audio signal “R” are transmitted from the buffer 10 to the multiplexer 19.

[0086] An addition circuit la in the channel correlation circuit “A” adds the left-channel digital audio signal “L” and the right-channel digital audio signal “R” into a PCM addition-result signal (L+R). The addition circuit la outputs the PCM addition-result signal (L+R) to a prediction circuit 15A and a difference calculation circuit 11D1. For every frame, the first sample of the PCM addition-result signal (L+R) is transmitted from the addition circuit 1ato the multiplexer 19. A subtraction circuit 1bin the channel correlation circuit “A” subtracts the right-channel digital audio signal “R” from the left-channel digital audio signal “L”, thereby generating a PCM subtraction-result signal (L−R). The subtraction circuit 1boutputs the PCM subtraction-result signal (L−R) to a prediction circuit 15S and a difference calculation circuit 11D2. For every frame, the first sample of the PCM subtraction-result signal (L−R) is transmitted from the subtraction circuit 1bto the multiplexer 19.

[0087] The difference calculation circuit 11D1 generates a DPCM signal Δ(L+R) from the PCM addition-result signal (L+R). The difference calculation circuit 11D1 outputs the DPCM signal Δ(L+R) to a prediction circuit 15D1. The difference calculation circuit 11D2 generates a DPCM signal Δ(L−R) from the PCM subtraction-result signal (L−R). The difference calculation circuit 11D2 outputs the DPCM signal Δ(L−R) to a prediction circuit 15D2.

[0088] The prediction circuits 15A and 15L are similar in structure to the prediction circuit 15D1. The prediction circuits 15R and 15S are similar in structure to the prediction circuit 15D2. The prediction circuit 15A is followed by a buffer and selector 16A. The prediction circuit 15L is followed by a buffer and selector 16L. The prediction circuit 15R is followed by a buffer and selector 16R. The prediction circuit 15S is followed by a buffer and selector 16S. The prediction circuit 15D1 is followed by a buffer and selector 16D1, the prediction circuit 15D2 is followed by a buffer and selector 16D2. The buffer and selector 16A is similar in structure to the buffer and selector 16D1. The buffer and selector 16L is similar in structure to the buffer and selector 16D1. The buffer and selector 16R is similar in structure to the buffer and selector 16D2. The buffer and selector 16S is similar in structure to the buffer and selector 16D2.

[0089] The prediction circuit 15A receives the PCM addition-result signal (L+R) from the addition circuit la in the channel correlation circuit “A”. The prediction circuit 15A generates a set of PCM prediction-error signals in response to the PCM addition-result signal (L+R). The prediction circuit 15A outputs the PCM prediction-error signals to the buffer and selector 16A. The PCM prediction-error signals are temporarily stored in a memory within the buffer and selector 16A. The selection signal generator 17 outputs a selection signal to the buffer and selector 16A. The selection signal is designed to select the smallest one from among the PCM prediction-error signals in the memory of the buffer and selector 16A as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16A for the smallest PCM prediction-error signal. The smallest PCM prediction-error signal is the selected PCM (L+R)-related prediction-error signal.

[0090] In addition, the selection signal generator 17 produces an (L+R)-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected PCM (L+R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the (L+R)-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an (L+R)-related predictor-selection flag representing the optimal predictor causing the selected PCM (L+R)-related prediction-error signal. The selection signal generator 17 outputs the (L+R)-related predictor-selection flag to the multiplexer 19.

[0091] The prediction circuit 15S receives the PCM subtraction-result signal (L−R) from the subtraction circuit 1bin the channel correlation circuit “A”. The prediction circuit 15S generates a set of PCM prediction-error signals in response to the PCM subtraction-result signal (L−R). The prediction circuit 15S outputs the PCM prediction-error signals to the buffer and selector 16S. The PCM prediction-error signals are temporarily stored in a memory within the buffer and selector 16S. The selection signal generator 17 outputs a selection signal to the buffer and selector 16S. The selection signal is designed to select the smallest one from among the PCM prediction-error signals in the memory of the buffer and selector 16S as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16S for the smallest PCM prediction-error signal. The smallest PCM prediction-error signal is the selected PCM (L−R)-related prediction-error signal.

[0092] In addition, the selection signal generator 17 produces an (L−R)-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected PCM (L−R)-related prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the (L−R)-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an (L−R)-related predictor-selection flag representing the optimal predictor causing the selected PCM (L−R)-related prediction-error signal. The selection signal generator 17 outputs the (L−R)-related predictor-selection flag to the multiplexer 19.

[0093] The prediction circuit 15L receives the left-channel digital audio signal “L” from the buffer 10. The prediction circuit 15L generates a set of original-L prediction-error signals in response to the left-channel digital audio signal “L”. The prediction circuit 15L outputs the original-L prediction-error signals to the buffer and selector 16L. The original-L prediction-error signals are temporarily stored in a memory within the buffer and selector 16L. The selection signal generator 17 outputs a selection signal to the buffer and selector 16L. The selection signal is designed to select the smallest one from among the original-L prediction-error signals in the memory of the buffer and selector 16L as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16L for the smallest original-L prediction-error signal. The smallest original-L prediction-error signal is the selected original-L prediction-error signal.

[0094] In addition, the selection signal generator 17 produces an L-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected original-L prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the L-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an L-related predictor-selection flag representing the optimal predictor causing the selected original-L prediction-error signal. The selection signal generator 17 outputs the L-related predictor-selection flag to the multiplexer 19.

[0095] The prediction circuit 15R receives the right-channel digital audio signal “R” from the buffer 10. The prediction circuit 15R generates a set of original-R prediction-error signals in response to the right-channel digital audio signal “R”. The prediction circuit 15R outputs the original-R prediction-error signals to the buffer and selector 16R. The original-R prediction-error signals are temporarily stored in a memory within the buffer and selector 16R. The selection signal generator 17 outputs a selection signal to the buffer and selector 16R. The selection signal is designed to select the smallest one from among the original-R prediction-error signals in the memory of the buffer and selector 16R as an output signal of an optimum subtracter (an optimum predictor) for every sub-frame. Specifically, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16R for the smallest original-R prediction-error signal. The smallest original-R prediction-error signal is the selected original-R prediction-error signal.

[0096] In addition, the selection signal generator 17 produces an R-related bit-number flag representing the maximum number among the numbers of effective bits in respective samples of the selected original-R prediction-error signal which compose one sub-frame. For every sub-frame, the selection signal generator 17 outputs the R-related bit-number flag to the packing circuit 18 and the multiplexer 19. Also, for every sub-frame, the selection signal generator 17 produces an R-related predictor-selection flag representing the optimal predictor causing the selected original-R prediction-error signal. The selection signal generator 17 outputs the R-related predictor-selection flag to the multiplexer 19.

[0097] For every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D1 for the smallest DPCM prediction-error signal. The smallest DPCM prediction-error signal is the selected DPCM (L+R)-related prediction-error signal. Also, for every sub-frame, the selection signal generator 17 searches the memory within the buffer and selector 16D2 for the smallest DPCM prediction-error signal. The smallest DPCM prediction-error signal is the selected DPCM (L−R)-related prediction-error signal.

[0098] Furthermore, for every sub-frame, the selection signal generator 17 decides which of the pair of the original-L prediction-error signal and the original-R prediction-error signal, the pair of the selected PCM (L+R)-related prediction-error signal and the selected PCM (L−R)-related prediction-error signal, and the pair of the selected DPCM (L+R)-related prediction-error signal and the selected DPCM (L−R)-related prediction-error signal is the highest in compression rate by comparing the values represented thereby. The selection signal generator 17 selects the highest-compression pair of the prediction-error signals. The selection signal generator 17 enables the highest-compression pair of the prediction-error signals to be outputted to the packing circuit 18.

[0099] For every sub-frame, the selection signal generator 17 produces a prediction-circuit-selection flag representing which of the original prediction-error signal pair, the PCM prediction-error signal pair, and the DPCM prediction-error signal pair is selected. The selection signal generator 17 outputs the prediction-circuit-selection flag to the multiplexer 19. The multiplexer 19 adds the prediction-circuit-selection flag into the variable-rate bit stream.

[0100] FIG. 8 shows an audio signal decoding apparatus in the third embodiment of this invention which is a modification of the audio signal decoding apparatus 200 in the first embodiment of this invention. The audio signal decoding apparatus of FIG. 8 includes selectors 26a, 26b, 27a, and 27b. The demultiplexer 21 separates every prediction-circuit-selection flag from the variable-rate bit stream. The demultiplexer 21 feeds the prediction-circuit-selection flag to the selectors 26a, 26b, 27a, and 27b. When the prediction-circuit-selection flag indicates that the DPCM prediction-error signal pair is selected, the selector 26aselects the output signal of the accumulation circuit 25aand the selector 26bselects the output signal of the accumulation circuit 25b. When the prediction-circuit-selection flag indicates that the PCM prediction error signal pair is selected, the selector 26aselects the output signal of the addition circuit 23aand the selector 26bselects the output signal of the addition circuit 23b. The signal selected by the selector 26aconstitutes the reproduced addition-result signal (L+R). The signal selected by the selector 26bconstitutes the reproduced subtraction-result signal (L−R). The reproduced addition-result signal (L+R) and the reproduced subtraction-result signal (L−R) are fed to the channel correlation circuit “B”.

[0101] When the prediction-circuit-selection flag indicates that the original prediction-error signal pair is selected, the selector 27aselects the output signal of the addition circuit 23aand the selector 27bselects the output signal of the addition circuit 23b. Otherwise, the selector 27aselects the output signal of the divider 5ain the channel correlation circuit “B” and the selector 27bselects the output signal of the divider 5bin the channel correlation circuit “B”. The signal selected by the selector 27aconstitutes the reproduced left-channel digital audio signal “L”. The signal selected by the selector 27bconstitutes the reproduced right-channel digital audio signal “R”.

[0102] A fourth embodiment of this invention is similar to one of the first, second, and third embodiments thereof except for design changes mentioned later.

[0103] With reference to FIG. 9, the fourth embodiment of this invention includes a DVD-audio encoder 300 which follows the audio signal encoding apparatus 100. The DVD-audio encoder 300 converts the output signal of the audio signal encoding apparatus (that is, the variable-rate bit stream) into a DVD-audio-format signal. The DVD-audio encoder 300 outputs the DVD-audio-format signal to a DVD drive 302. A writer in the DVD drive 302 records the DVD-audio-format signal on a DVD-audio disc 304.

[0104] A reader in the DVD drive 302 reproduces the DVD-audio-format signal from the DVD-audio disc 304. The reader in the DVD drive 302 outputs the reproduced signal to a DVD-audio decoder 306. The DVD-audio decoder 306 recovers the variable-rate bit stream from the reproduced signal. The DVD-audio decoder 306 outputs the recovered variable-rate bit stream to the audio signal decoding apparatus 200.

[0105] The DVD-audio-format signal generated by the DVD-audio encoder 300 has a stream of packs including audio packs. As shown in FIG. 10, each audio pack has a sequence of 4-byte pack start information, 6-byte SCR (system clock reference) information, 3-byte mux rate information, 1-byte stuffing data, and 2,034-byte packet-form user data. Thus, each audio pack has 2,048 bytes. In each audio pack, pack start information, SCR information, mux rate information, and stuffing data compose a 14-byte pack header. SCR information in each audio pack serves as a time stamp. In each audio pack, 2,034-byte packet-form user data contains a portion of the variable-rate bit stream.

[0106] A time stamp in a first audio pack among audio packs related to one title is set to “1”. Time stamps in second and later audio packs related to the same title are set to serial numbers “2”, “3”, “4”, . . . , respectively. The serially-numbered time stamps make it possible to manage times of audio packs related to the same title.

[0107] As shown in FIG. 11, one audio pack has a 14-byte pack header and an audio packet. The pack header is followed by the audio packet. The audio packet has a sequence of a packet header, a private header, and audio data (linear PCM audio data). The packet header has 9 bytes, 14 bytes, or 17 bytes. The audio data has 1 byte to 2,011 bytes. The audio data is a portion of the variable-rate bit stream.

[0108] As shown in FIG. 11, the private header has a sequence of 1-byte sub stream ID (identification) information, 2-byte information of an UPC/EAN-ISRC (Universal Product Code/European Article Number-International Standard Recording Code) number and UPC/EAN-ISRC data, 1-byte information of the private header length, a 2-byte first access unit pointer, 8-byte audio data information ADI, and 0 to 7 stuffing bytes.

[0109] A fifth embodiment of this invention is similar to one of the first, second, and third embodiments thereof except for design changes mentioned later.

[0110] With reference to FIG. 12, the fifth embodiment of this invention includes a packeting processor 350 which follows the audio signal encoding apparatus 100. The packeting processor 350 encodes the output signal of the audio signal encoding apparatus (that is, the variable-rate bit stream) into a packet stream. The packeting processor 350 transmits the packet stream to a communication network (or a communication line) 360.

[0111] A de-packeting processor 370 receives the packet stream from the communication network 360. The de-packeting processor 370 decodes the packet stream into the variable-rate bit stream. The de-packeting processor 370 outputs the variable-rate bit stream to the audio signal decoding apparatus 200.

[0112] The packeting processor 350 operates in accordance with a control program stored in its internal ROM or another memory. FIG. 13 is a flowchart of a segment of the control program. As shown in FIG. 13, a first step S41 of the program segment divides the variable-rate bit stream into basic packets each having a predetermined number of bits. A step S42 following the step S41 adds headers to the starting ends of the basic packets to change the basic packets to final packets respectively. Generally, the added headers include destination addresses. A step S43 subsequent to the step S42 sequentially transmits the final packets to the communication network 360.

[0113] The de-packeting processor 370 operates in accordance with a, control program stored in its internal ROM or another memory. FIG. 14 is a flowchart of a segment of the control program. As shown in FIG. 14, a first step S51 of the program segment removes headers from received packets. A step S52 following the step S51 recovers the variable-rate bit stream from the header-less packets. A step S53 subsequent to the step S52 stores the recovered variable-rate bit stream into a buffer memory provided in the de-packeting processor 370. The variable-rate bit stream is transmitted from the buffer memory to the audio signal decoding apparatus 200.

[0114] FIG. 15 shows a sixth embodiment of this invention which is similar to the first embodiment thereof except for design changes indicated hereinafter.

[0115] The embodiment of FIG. 15 includes a lossless encoder 2E and a lossless decoder 3E which replace the lossless encoder 2D and the lossless decoder 3D (see FIG. 1) respectively. The lossless encoder 2E follows a channel correlation circuit “A”. The lossless decoder 3E precedes a channel correlation circuit “B”.

[0116] The embodiment of FIG. 15 includes a channel correlation circuits A2 and B2. The channel correlation circuit A2 precedes the lossless encoder 2E. The channel correlation circuit B2 follows the lossless decoder 3E.

[0117] An encoder side of the embodiment of FIG. 15 receives a multi-channel digital audio signal composed of a left-channel digital audio signal “L”, a right-channel digital audio signal “R”, a left surround signal “SL”, and a right surround signal “SR”. The multi-channel digital audio signal is reproduced from a digital recording medium such as a DVD-audio (a digital versatile disc audio). The left-channel digital audio signal “L” and the right-channel digital audio signal “R” are processed by the channel correlation circuit “A” into an addition-result signal (L+R) and a subtraction-result signal (L−R). The addition-result signal (L+R) and the subtraction-result signal (L−R) are fed to the lossless encoder 2E. The left surround signal “SL” and the right surround signal “SR” are processed by the channel correlation circuit A2 into an addition-result signal (SL+SR) and a subtraction-result signal (SL−SR). The addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) are fed to the lossless encoder 2E.

[0118] The channel correlation circuit A2 includes an addition circuit 1a2 and a subtraction circuit 1b2. The addition circuit 1a2 receives the left surround signal “SL” and the right surround signal “SR”. The addition circuit 1a2 adds the left surround signal “SL” and the right surround signal “SR” into an addition-result signal (SL+SR). The addition circuit 1a2 outputs the addition-result signal (SL+SR) to the lossless encoder 2E. The subtraction circuit 1b2 receives the left surround signal “SL” and the right surround signal “SR”. The subtraction circuit 1b2 subtracts the right surround signal “SR” from the left surround signal “SL”, thereby generating a subtraction-result signal (SL−SR). The subtraction circuit 1b2 outputs the subtraction-result signal (SL−SR) to the lossless encoder 2E.

[0119] The lossless encoder 2E encodes the addition-result signal (L+R) and the subtraction-result signal (L−R) into a first encoding-resultant signal as the lossless encoder 2D in FIG. 1 does. Similarly, the lossless encoder 2E encodes the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) into a second encoding-resultant signal. The lossless encoder 2E combines the first encoding-resultant signal and the second encoding-resultant signal into a variable-rate bit stream representing a sequence of variable-bit-number frames. The lossless encoder 2E outputs the variable-rate bit stream to a transmission line 250.

[0120] FIG. 16 shows the format of every frame of the variable-rate bit stream outputted from the lossless encoder 2E. As shown in FIG. 16, a starting portion of every frame has a frame header. The frame header is successively followed by a first data section and a second data section. The first data section is loaded with information related to the addition-result signal (L+R) and the subtraction-result signal (L−R). The second data section is loaded with information related to the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR).

[0121] With reference back to FIG. 15, the lossless decoder 3E receives the variable-rate bit stream from the transmission line 250. The lossless decoder 3E divides the variable-rate bit stream into first information related to the addition-result signal (L+R) and the subtraction-result signal (L−R), and second information related to the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR). The lossless decoder 3E decodes the first information into the addition-result signal (L+R) and the subtraction-result signal (L−R) as the lossless decoder 3D in FIG. 1 does. The lossless decoder 3E outputs the addition-result signal (L+R) and the subtraction-result signal (L−R) to the channel correlation circuit “B”. Similarly, the lossless decoder 3E decodes the second information into the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR). The lossless decoder 3E outputs the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) to the channel correlation circuit B2.

[0122] The channel correlation circuit B includes an addition circuit 4a2, a subtraction circuit 4b2, and ½ dividers 5a2 and 5b2. The addition circuit 4a2 receives the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) from the lossless decoder 3E. The addition circuit 4a2 adds the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) into a signal 2SL. The addition circuit 4a2 outputs the signal 2SL to the divider 5a2. The divider 5a2 halves the signal 2SL, thereby reproducing the original left surround signal “SL”. The divider 5a2 outputs the reproduced left surround signal “SL”. The subtraction circuit 4b2 receives the addition-result signal (SL+SR) and the subtraction-result signal (SL−SR) from the lossless decoder 3E. The subtraction circuit 4b2 subtracts the subtraction-result signal (SL−SR) from the addition-result signal (SL+SR), thereby generating a signal 2SR. The subtraction circuit 4b2 outputs the signal 2SR to the divider 5b2. The divider 5b2 halves the signal 2SR, thereby reproducing the original right surround signal “SR”. The divider 5b2 outputs the reproduced right surround signal “SR”.

[0123] FIG. 17 shows a seventh embodiment of this invention which is similar to the first embodiment thereof except for design changes indicated hereinafter.

[0124] The embodiment of FIG. 17 includes a lossless encoder 2F and a lossless decoder 3F which replace the lossless encoder 2D and the loss decoder 3D (see FIG. 1) respectively. The lossless encoder 2F follows a channel correlation circuit “A”. The lossless decoder 3F precedes a channel correlation circuit “B”.

[0125] An encoder side of the embodiment of FIG. 17 receives a multi-channel digital audio signal composed of a left-channel digital audio signal “L”, a right-channel digital audio signal “R”, a center signal “C”, a left surround signal “SL”, a right surround signal “SR”, and a low frequency effect signal “LFE”. The multi-channel digital audio signal is reproduced from a digital recording medium such as a DVD-audio (a digital versatile disc audio). The left-channel digital audio signal “L” and the right-channel digital audio signal “R” are processed by the channel correlation circuit “A” into an addition-result signal (L+R) and a subtraction-result signal (L−R). The addition-result signal (L+R) and the subtraction-result signal (L−R) are fed to the lossless encoder 2F. The center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE” are directly applied to the lossless encoder 2F.

[0126] The lossless encoder 2E encodes the addition-result signal (L+R) and the subtraction-result signal (L−R) into a first encoding-resultant signal as the lossless encoder 2D in FIG. 1 does. Also, the lossless encoder 2F encodes the center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE” into second, third, fourth, and fifth encoding-resultant signals, respectively. The lossless encoder 2F combines the first, second, third, fourth, and fifth encoding-resultant signals into a variable-rate bit stream representing a sequence of variable-bit-number frames. The lossless encoder 2F outputs the variable-rate bit stream to a transmission line 250.

[0127] FIG. 18 shows the format of every frame of the variable-rate bit stream outputted from the lossless encoder 2F. As shown in FIG. 18, a starting portion of every frame has a frame header. The frame header is successively followed by a first data section and a second data section. The first data section is loaded with information related to the addition-result signal (L+R) and the subtraction-result signal (L−R). The second data section is loaded with information related to the center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE”.

[0128] With reference back to FIG. 17, the lossless decoder 3F receives the variable-rate bit stream from the transmission line 250. The lossless decoder 3F divides the variable-rate bit stream into first information related to the addition-result signal (L+R) and the subtraction-result signal (L−R), and second information related to the center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE”. The lossless decoder 3F decodes the first information into the addition-result signal (L+R) and the subtraction-result signal (L−R) as the lossless decoder 3D in FIG. 1 does. The lossless decoder 3F outputs the addition-result signal (L+R) and the subtraction-result signal (L−R) to the channel correlation circuit “B”. Similarly, the lossless decoder 3F decodes the second information into the center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE”. The lossless decoder 3F outputs the center signal “C”, the left surround signal “SL”, the right surround signal “SR”, and the low frequency effect signal “LFE”.

[0129] FIG. 19 shows an eighth embodiment of this invention which is similar to the first embodiment thereof except for design changes indicated hereinafter.

[0130] The embodiment of FIG. 19 includes channel correlation circuits A3 and B3 which replace the channel correlation circuits “A” and “B” (see FIG. 1) respectively, The channel correlation circuit A3 includes a ½ divider 5a3 connected between an addition circuit 1aand a lossless encoder 2D. Also, the channel correlation circuit A3 includes a ½ divider 5b3 connected between a subtraction circuit 1band the lossless encoder 2D. The ½ dividers 5aand 5b(see FIG. 1) are removed from the channel correlation circuit B3.

[0131] FIG. 20 shows a ninth embodiment of this invention which is similar to the seventh embodiment thereof except for design changes indicated hereinafter.

[0132] The embodiment of FIG. 20 includes channel correlation circuits A3 and B3 which replace the channel correlation circuits “A” and “B” (see FIG. 17) respectively. The channel correlation circuit A3 includes a ½ divider 5a3 connected between an addition circuit 1aand a lossless encoder 2F. Also, the channel correlation circuit A3 includes a ½ divider 5b3 connected between a subtraction circuit 1band the lossless encoder 2F. On the other hand, ½ dividers 5aand 5b(see FIG. 17) are removed from the channel correlation circuit B3.