Temperature sensing circuit

[0002] 1. Field of the Invention

[0003] The invention relates to a temperature sensing circuit, more particularly to a temperature sensing circuit having relatively high accuracy that is not easily affected by component manufacturing tolerances.

[0004] 2. Description of the Related Art

[0005] In recent years, rapid developments in integrated circuit technology have reached the stage where a single-packaged chip may contain millions of transistors. As such, when an integrated circuit configured with a large number of transistors operates at a clock rate of several hundred MHz, the amount of heat dissipated will be enormous to the extent that the operating temperature may exceed 100 degrees centigrade.

[0006] Due to the change in temperature, all components in the chip will be adversely affected, since temperature and conductivity have an inversely proportional relationship. Therefore, when temperature rises, the electrical characteristics of components will change accordingly. The most evident effect is that operating speed and overall efficiency are reduced.

[0007] Referring to FIG. 1, a conventional temperature sensing circuit 7 is shown to comprise a current mirror 71 and a Widlar current source 72 coupled thereto. As known to those skilled in the art, by matching transistors in the current mirror 71, the temperature sensing circuit 7 will have equal currents I₁, I₂, I₃, i.e., I₁==I₂=I₃. When the transistor (Q₂) of the Widlar current source 72 operates in the forward active region, the current (I₂) flowing through the transistor (Q₂) will be: $\begin{array}{cc}{I}_2=\frac{1}{R_{13}}{V}_T\ln \left(n\right)& \left(1\right)\end{array}$

[0008] wherein n is the emitter-base junction ratio between the transistor (Q₂) and the transistor (Q₁), and the thermal voltage (V_T) is equal to 26 mV·T/300° K. Since the voltage (V_TEMP)=I₃×R₁₄=I₂×R₁₃, the following equation can be obtained: $\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{TEMP}}=\frac{R_{14}}{R_{13}}{V}_T\ln \left(n\right)\\ =\frac{R_{14}}{R_{13}}\left(\frac{26\mathrm{mV}·T}{300°K}\right)\ln \left(n\right)\end{array}& \left(2\right)\end{array}$

[0009] Therefore, the amount of change in the voltage (V_TEMP) is determined by the values of n and (R₁₄/R₁₃). In order to facilitate monitoring of the temperature change, it is preferable that when the temperature rises by 1° K, the voltage (V_TEMP) rises by 1 mV accordingly. In other words,. (R₁₄/RL₃)·(26)·ln(n) must have a value of about 300. The relevant parameters in wide use to meet the above condition are: n=4, R₁₃=3.6 K, and R₁₄=30 K. By substituting these parameters into equation (2), the following equation can be obtained: $\begin{array}{cc}{V}_{\mathrm{TEMP}}=300\mathrm{mV}\times \frac{T}{300°K}& \left(3\right)\end{array}$

[0010] Therefore, when the temperature rises by 1° K, the voltage (V_TEMP) rises by 1 mV. As such, when the temperature sensing circuit 7 is coupled to a main circuit (not shown) the operating temperature of the main circuit can be monitored by observing the voltage (V_TEMP) from the temperature sensing circuit 7 so that thermal protection of the main circuit can be activated when appropriate.

[0011] However, the foregoing analysis was made under ideal conditions in practice, due to manufacturing constraints, the actual output of the temperature sensing circuit 7 usually differs from the original design. It is noted that the accuracy of the voltage (V_TEMP) depends on the actual values of n and (R₁₄/R₁₃) Therefore, during manufacturing, if a lower value of (R₁₄/R₁₃) is desired, a higher value of n must be provided for compensation. For example, if (R₁₄/R₁₃) is set as 2, the value of n must be as high as 320 to satisfy the condition that when the temperature rises by 1° K, the voltage (V_TEMP) rises by 1 mV. Nevertheless, the value of n is determined by the physical characteristics of the transistors (Q₂) and (Q₁) and cannot be adjusted. If manufacture of the transistors (Q₂) and (Q₁) is based simply on the calculated values, the outcome will be a mismatch in the current gains of the transistors (Q₂) and (Q₁), thereby resulting in failure of the temperature sensing circuit 7 to operate normally and inability of the temperature sensing circuit 7 to serve the purpose of temperature measuring. Thus, to ensure the accuracy of the characteristic curve of the circuit, a value smaller than 10 is usually adopted for n. This introduces another design problem since the value of (R₁₄/R₁₃) must be correspondingly increased to satisfy the aforesaid requirement. However, in view of manufacturing constraints, it is known that the resistance values of resistors cannot be accurately controlled. Due to the requirement of a high resistance ratio, the resultant error tends to be too high. As such, the measured result of the temperature sensing circuit 7 is imprecise.

[0012] Therefore, the main object of the present invention is to provide a temperature sensing circuit having relatively high accuracy that is not easily affected by component manufacturing tolerances.

[0013] Accordingly, a temperature sensing circuit of this invention comprises a current source for providing a bias current, a first transistor pair coupled to the current source, and a cascaded set of second transistor pairs.

[0014] The first transistor pair includes first and second transistors. The first transistor has a first collector, a first base coupled to the first collector, and a first emitter. The second transistor has a second collector, a second base coupled to the first base of the first transistor, and a second emitter. The first transistor pair has a first emitter-base junction ratio between the first transistor and the second transistor.

[0015] A first one of the second transistor pairs in the cascaded set is coupled to the first transistor pair. Each of the second transistor pairs includes third and fourth transistors. The third transistor has a third collector, a third base and a third emitter. The fourth transistor has a fourth collector coupled to the third base of the third transistor, a fourth base coupled to the third collector of the third transistor, and a fourth emitter. The third and fourth emitters of the third and fourth transistors of each of the first through a second to a last one of the second transistor pairs in the cascaded set are coupled to the third and fourth collectors of an adjacent one of the second transistor pairs in the cascaded set, respectively. Each of the second transistor pairs has a respective second emitter-base junction ratio between the third transistor and the fourth transistor thereof. A voltage output, which corresponds to temperature sensed by the temperature sensing circuit and which is a function of the first emitter-base junction ratio of the first transistor pair and the second emitter-base junction ratios of the second transistor pairs, is obtained from the third and fourth emitters of the last one of the second transistor pairs in the cascaded set.

[0016] Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:

[0017] FIG. 1 is a circuit diagram illustrating a conventional temperature sensing circuit;

[0018] FIG. 2 is a circuit diagram illustrating a preferred embodiment of a temperature sensing circuit according to the present invention;

[0019] FIG. 3 is a schematic diagram illustrating an equivalent circuit of a transistor having an N-times emitter-base junction;

[0020] FIG. 4 is a circuit diagram illustrating the temperature sensing circuit according to the present invention embodied with one example of a current source;

[0021] FIG. 5 is a circuit diagram illustrating the temperature sensing circuit according to the present invention embodied with another example of a current source; and

[0022] FIG. 6 is a circuit diagram illustrating another preferred embodiment of a temperature sensing circuit according to the present invention.

[0023] Referring to FIG. 2, the preferred embodiment of a temperature sensing circuit 1 according to the present invention is shown to include a current source (I_REF) a first transistor pair 11, and a cascaded set of second transistor pairs 12.

[0024] The current source (I_REF) is used to provide a bias current (I₁), which is a constant DC current. The first transistor pair 11 is coupled to the current source (I_REF) and includes a first transistor (Q₁) and a second transistor (Q₂). The first transistor (Q₁) has a first collector, a first base coupled to the first collector, and a first emitter. The second transistor (Q₂) has a second collector, a second base coupled to the first base of the first transistor (Q₁), and a second emitter. The first transistor pair 11 has a first emitter-base junction ratio (N₁) between the first transistor (Q₁) and the second transistor (Q₂).

[0025] In this embodiment, the cascaded set of second transistor pairs 12 includes five second transistor pairs 12. Each of the second transistor pairs 12 includes a third transistor having a third collector, a third base and a third emitter, and a fourth transistor having a fourth collector coupled to the third base of the third transistor, a fourth base coupled to the third collector of the third transistor, and a fourth emitter. For convenience of illustration, the third and fourth transistors of the second transistor pairs 12 are designated using an increasing order of reference numerals, i.e., Q₃, Q₄, Q₅. . . Q₁₂. In FIG. 2, from top to bottom, the third transistors are disposed on the left side of the cascaded set and are designated as Q₃, Q₅, Q₇, Q₉, Q₁₁, while the fourth transistors are disposed on the right side of the cascaded set and are designated as Q₄, Q₆, Q₈, Q₁₀, Q₁₂. The third and fourth collectors of the third and fourth transistors (Q₃, Q₄) of a first one of the second transistor pairs 12 in the cascaded set are coupled to the first and second emitters of the first and second transistors (Q₁, Q₂) of the first transistor pair 11, respectively. The third and fourth emitters of the third and fourth transistors of each of the first through a second to a last one of the second transistor pairs 12 in the cascaded set are coupled to the third and fourth collectors of an adjacent one of the second transistor pairs 12 in the cascaded set, respectively. Taking the second one of the second transistor pairs 12 in the cascaded set as an example, the third base of the third transistor (Q₅) is coupled to the fourth collector of the fourth transistor (Q₆) the fourth base of the fourth transistor (Q₆) is coupled to the third collector of the third transistor (Q₅), the third emitter of the third transistor (Q₅) is coupled to the third collector of the third transistor (Q₇), and the fourth emitter of the fourth transistor (Q₆) is coupled to the fourth collector of the fourth transistor (Q₈). The other ones of the second transistor pairs 12 are coupled to each other in a similar manner. Finally, an output resistor (R) has a first terminal coupled to the fourth emitter of the fourth transistor (Q₁₂) of a last one of the second transistor pairs 12 in the cascaded set, and a grounded second terminal. The third emitter of the third transistor (Q₁₁) of the last one of the second transistor pairs 12 in the cascaded set is grounded. A voltage output (V_TEMP) is measured across the output resistor (R), and is the emitter voltage difference between the fourth and third transistors (Q₁₂), (Q₁₁).

[0026] Furthermore, each of the five second transistor pairs 12 has a respective second emitter-base junction ratio between the third transistor and the fourth transistor thereof. As shown in FIG. 2, the second emitter-base junction ratios of the second transistor pairs 12 are designated using an increasing order of reference numerals, i.e., N₂, N₃, N₄, N₅and N₆from top to bottom. N₂is the second emitter-base junction ratio between the transistors (Q₄), (Q₃). N₃is the second emitter-base junction ratio between the transistors (Q₅), (Q₆). N₄is the second emitter-base junction ratio between the transistors (Q₈) (Q₇). N₅is the second emitter-base junction ratio between the transistors (Q₉), (Q₁₀). N₆is the second emitter-base junction ratio between the transistors (Q₁₂) (Q₁₁). When the emitter-base junctions of the transistor (Q₃), (Q₆), (Q₇), (Q₁₀), (Q₁₁) are set to 1, the emitter-base junctions of the transistors (Q₄), (Q₅), (Q₈), (Q₉), (Q₁₂) are selected so that the magnitudes of the second emitter-base junction ratios of the second transistor pairs 12 are arranged in the following sequence: N₂, N₃, N₄, N₅, N₆.

[0027] Therefore, by virtue of KVL, the following equation can be obtained:

[0028] V_BE11+V_BE10+V_BE7+V_BE6+V_BE3+V_BE2−V_BE1−V_BE4−V_BE5−V_BE8−V_BE9−V_BE12=V_TEMP  (4)

[0029] It is known that when a bipolar junction transistor operates in the forward active region, the base-emitter voltage thereof is as follows: $V_{\mathrm{BE}}=V_T\ln \left(\frac{I_C}{I_S}\right).$

[0030] wherein I_Cis the transistor collector current, and I_Sis the transistor saturation current and is proportional to the size of the emitter-base junction of the transistor.

[0031] Therefore, equation (4) can be rewritten as follows: $V_{\mathrm{TEMP}}=V_T\ln \left(\frac{I_{\mathrm{C11}}}{I_{\mathrm{S11}}}\times \frac{I_{\mathrm{C10}}}{I_{\mathrm{S10}}}\times \frac{I_{\mathrm{C7}}}{I_{\mathrm{S7}}}\times \frac{I_{\mathrm{C6}}}{I_{\mathrm{S6}}}\times \frac{I_{\mathrm{C3}}}{I_{\mathrm{S3}}}\times \frac{I_{\mathrm{C2}}}{I_{\mathrm{S2}}}\times \frac{I_{\mathrm{S1}}}{I_{\mathrm{C1}}}\times \frac{I_{\mathrm{S4}}}{I_{\mathrm{C4}}}\times \frac{I_{\mathrm{S5}}}{I_{\mathrm{C5}}}\times \frac{I_{\mathrm{S8}}}{I_{\mathrm{C8}}}\times \frac{I_{\mathrm{S9}}}{I_{\mathrm{C9}}}\times \frac{I_{\mathrm{S12}}}{I_{\mathrm{C12}}}\right)$

[0032] wherein I_C1, I_C2, . . . I_C12are the collector currents of the transistors (Q₁), (Q₂), . . . (Q₁₂), respectively, and I_S1˜IS₁₂are the saturation currents of the transistors (Q₁)˜(Q₁₂) respectively. Since the current gain of each transistor (Q₁), (Q₂), . . . (Q₁₂) is relatively large, the base currents thereof can be considered to be negligible. Therefore, the first current (I₁) flows through the transistors (Q₁, Q₃, Q₅, Q₇, Q₉, Q₁₁). Assuming that the current flowing through the transistors (Q₂, Q₄, Q₆, Q₈, Q₁₀) is a second current (I₂) then I_C1=I_C3=I_C5=I_C7=I_C9=I_C11=I₁, and I_C2=I_C4=I_C6=I_C8=I_C10=I₂.

[0033] Thus, equation (4) can be further rewritten as $V_{\mathrm{TEMP}}=V_T\ln \left(\frac{I_1}{I_{\mathrm{S11}}}\times \frac{I_2}{I_{\mathrm{S10}}}\times \frac{I_1}{I_{\mathrm{S7}}}\times \frac{I_2}{I_{\mathrm{S6}}}\times \frac{I_1}{I_{\mathrm{S3}}}\times \frac{I_2}{I_{\mathrm{S2}}}\times \frac{I_{\mathrm{S1}}}{I_1}\times \frac{I_{\mathrm{S4}}}{I_2}\times \frac{I_{\mathrm{S5}}}{I_1}\times \frac{I_{\mathrm{S8}}}{I_2}\times \frac{I_{\mathrm{S9}}}{I_1}\times \frac{I_{\mathrm{S12}}}{I_2}\right)$

[0034] and is equivalent to: $\begin{array}{cc}{V}_{\mathrm{TEMP}}=V_T\ln \left(\frac{I_{\mathrm{S1}}}{I_{\mathrm{S2}}}\times \frac{I_{\mathrm{S4}}}{I_{\mathrm{S3}}}\times \frac{I_{\mathrm{S5}}}{I_{\mathrm{S6}}}\times \frac{I_{\mathrm{S8}}}{I_{\mathrm{S7}}}\times \frac{I_{\mathrm{S9}}}{I_{\mathrm{S10}}}\times \frac{I_{\mathrm{S12}}}{I_{\mathrm{S11}}}\right)& \left(5\right)\end{array}$

[0035] Since the saturation current of a transistor is proportional to the size of the emitter-base junction as mentioned hereinabove, (I_S1/I_S2) is equal to (N₁) which is the first emitter-base junction ratio between the first transistor (Q₁) and the second transistor (Q₂) (I_S4/I_S3) is equal to (N₂), which is the second emitter-base junction ratio between the fourth transistor (Q₄) and the third transistor (Q₁). Accordingly, the other saturation current ratios in equation (5) can be expressed in terms of the ratios (N₃) to (N₆). Thus, equation (5) can be rewritten as follows: $\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{TEMP}}=V_T\ln \left(N_1\times N_2\times N_3\times N_4\times N_5\times N_6\right)\\ =26\mathrm{mV}·\left(\frac{T}{300°K}\right)·\ln \left(N_1\times N_2\times N_3\times N_4\times N_5\times N_6\right)\end{array}& \left(6\right)\end{array}$

[0036] Therefore, the emitter voltage (V_TEMP) at the fourth transistor (Q₁₂) is a function of the first emitter-base junction ratio (N₁), the second emitter-base junction ratios (N₂, N₃, N₄, N₅, N₆), and the value of the temperature (T) to be measured, and is not affected by inaccuracies in the resistance of the resistor (R). Furthermore, since the emitter voltage (V_TEMP) is a natural logarithm of the product of all of the emitter-base junction ratios, and since the rate of change of ln(X) is 1/X, when X becomes bigger, the rate of change of ln(X) becomes smaller accordingly. Therefore, errors attributed to improperly matched transistors can be effectively lowered. As the emitter-base junction ratio of each transistor pair can be controlled during manufacturing, the change in the output voltage (V_TEMP) in response to the measured temperature (T) can be controlled as well. The temperature sensing circuit 1 is thus capable of accurate temperature measurement.

[0037] As an example of this embodiment, it is assumed that N₁=N₂=N₃=8 and N₄=N₅=N₆=6. Equation (6) thus becomes: $\begin{array}{c}{V}_{\mathrm{TEMP}}=26\mathrm{mV}·\left(\frac{T}{300°K}\right)\\ =302\mathrm{mV}\left(\frac{T}{300°K}\right)\end{array}·\ln \left(8\times 8\times 8\times 6\times 6\times 6\right)$

[0038] It is therefore evident that the temperature sensing circuit 1 according to the present invention can be configured such that, under the condition that the emitter-base junction ratio of each transistor pair is smaller than 10, the output voltage (V_TEMP) can rise by lmv in response to a rise of 1 degree kelvin in the measured temperature (T).

[0039] While only five second transistor pairs 12 are presented in the foregoing embodiment, in actual practice, the number of second transistor pairs 12 in the cascaded set may be more than five. Under such a situation, V_TEMP=V_Tln(N₁×N₂×N₃×N₄×N₅×N₆×N₇× . . . ).

[0040] Therefore, if the design requires that the output voltage (V_TEMP) should change by a larger value, such as 5 mv, in response to a rise of 1 degree kelvin in the measured temperature (T), the number of the second transistor pairs 12 in the cascaded set can be increased accordingly. As such, while maintaining matching current gains of the transistors (N<10) so as not to lose the characteristics thereof, appropriate adjustment of the emitter-base junction ratio of each transistor pair and the number of the second transistor pairs 12 in the cascaded set can result in a large product of the emitter-base junction ratios.

[0041] Referring to FIG. 3, in practice, a transistor with an N-times emitter-base junction is equivalent to a number (N) of transistors with unity emitter-base junctions and having collectors that are coupled together, emitters that are coupled together, and bases that are coupled together. In this manner, transistors having emitter-base junctions of different sizes can be easily obtained. Furthermore, the current source (I_REF) may be implemented in many ways. As shown in FIG. 4, the current source may include a source resistor (R₁) coupled to the first collector and adapted to be coupled to a voltage source. As shown in FIG. 5, the current source may include a known current mirror 13 coupled to the first and second collectors and adapted to be coupled to a voltage source.

[0042] In the previous embodiments, the transistors are npn bipolar junction transistors. FIG. 6 illustrates another embodiment of the temperature sensing circuit of this invention. In the embodiment of FIG. 6, the transistors between the voltage source (Vss) and the ground point are pnp bipolar junction transistors. The effect achieved in this embodiment is the same as that in the previous embodiments.

[0043] In summary, the temperature sensing circuit 1 of this invention eliminates inaccuracies attributed to incorrect resistance values, greatly lowers errors due to transistor mismatch, and reduces the adverse effect of errors inherent in the manufacturing process. Furthermore, by controlling the emitter-base junction ratio of each transistor pair and the number of the second transistor pairs in the cascaded set, the change in the output voltage (V_TEMP) in response to a rise of 1 degree kelvin in the measured temperature (T) can be flexibly controlled. The design and range of use of this invention are therefore highly flexible.

[0044] While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.