Dynamic floating SCR (semiconductor-controlled-rectifier) ESD protection

[0002] 1. Field of the Invention

[0003] This invention relates to a circuit and a method for protecting circuits from electrostatic discharge ESD. More particularly this invention relates to a circuit and a method which utilizes a dynamic floating circuit in conjunction with a silicon-controlled rectifier SCR in order to provide ESD protection for electronic circuits.

[0004] 2. DESCRIPTION OF RELATED ART

[0005] Today, conventional electrostatic protection circuits utilize capacitors and silicon-controlled-rectifiers SCRs. FIGS. 1aand 1bshow a lateral SCR (LSCR) ESD structure. This is the most basic SCR structure. In FIG. 1a, the SCR is imade up of P-N-P-N structure. The circuit model in fig. 1bshows the anode 110 attached to a PNP transitor 115 and a resistor 125. FIG. 1bfurther shows an NPN transistor 145 and another resistor 135 attached to the cathode of the SCR 140.

[0006] FIGS. 1cand 1dshow a low-voltage trigger SCR (LVTSCR) ESD structure. This structure is described in U.S. Pat. No. 5,465,189. This structure is popular due to the low-voltage trigger. In FIG. 1c, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 1dshows the anode 150 attached to a PNP transitor 155 and a resistor 165. FIG. 1dfurther shows an NPN transistor 185 and another resistor 175 attached to the cathode of the SCR 180. In addition, an FET trigger device 195 is shown in FIG. 1d.

[0007] FIGS. 2aand 2bshow a floating-well SCR (FWSCR) ESD structure. This structure is exhibited in U.S. Pat. 5,945,714. In FIG. 2a, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 2bshows the anode 210 attached to a PNP transitor 215. FIG. 2bfurther shows an NPN transistor 245 and another resistor 235 attached to the cathode of the SCR 240.

[0008] FIGS. 2cand 2dshow a MOS-incorporated-triggering SCR (MITSCR) ESD structure. This structure is exhibited in U.S. Pat. No. 5,986,307. In FIG. 2c, the SCR is made up of P-N-P-N structure. The circuit model in FIG. 2dshows the anode 210 attached to a PNP transitor 215 and a resistor 225. FIG. 2dfurther shows an NPN transistor 245 and another resistor 235 attached to the cathode of the SCR 240.

[0009] U.S. Pat. No. 6,011,420 (Watt, et al.) “ESD Protection Apparatus Having Floating ESD Bus and Semiconductor Structure” discloses an ESD protection scheme where a single ESD protection structure is connected to multiple pads. The circuit uses an FET-triggered SCR.

[0010] U.S. Pat. No. 5,959,821 (Voogel) “Triple-Well Silicon Controlled Rectifier with Dynamic Holding Voltage” describes a triple-well SCR with a circuit to control the voltage of the p-well. The triple-well structure is used for isolation from ground and to allow insertion of a control circuit for controlling the holding voltage of the SCR.

[0011] U.S. Pat. No. 5,400,202 (Metz, et al.) “Electrostatic Discharge Protection Circuit for Integrated Circuits” discloses an FET-triggered SCR to provide ESD protection for circuits. A trigger circuit which is activated by an ESD event triggers SCR latch-up.

[0012] It is the objective of this invention to provide a circuit and a method to protect electronic circuits from electrostatic discharge ESD damage.

[0013] It is further an object of this invention to provide this ESD circuit protection by using a control circuit and a silicon-controlled rectifier SCR to dynamically isolate the electronic circuits during ESD events.

[0014] In addition, it is further the object of this invention to place the control circuit between the supply voltage and the SCR in order provide better immunity from permanent SCR latch-up during the return to normal operation after an electrostatic event.

[0015] The objects of this invention are achieved by a circuit which includes a floating-well circuit connected between the supply voltage Vdd and the N-well of a silicon-controlled rectifier, (SCR). In addition, the floating-well circuit contains a transistor switch which is turned on during normal operation effectively connecting the N-well of the SCR to the supply voltage (Vdd). Alternatively, the transistor switch is turned on to allow the SCR to provide isolation from ground and circuit protection during ESD events. This transistor control circuit also provides latch-up immunity by incorporating a discharge resistor which allows the SCR to revert back to its non-latched state after the occurrence of an electrostatic event.

[0016] The objects of this invention are achieved by a method of designing ESD protection circuits which provides for the connection of a floating-well circuit between the power supply voltage VCC and the N-well of an SCR. This method of protecting circuits from ESD damage also provides for the switching of a field effect transistor FET On during normal operation to effectively connect the N-well of the SCR to the supply voltage VCC. The circuit design method includes a capacitor attached from the supply voltage Vdd to the gate of the FET. During electrostatic events where the supply voltage contains spikes which momentarily increase the supply voltage beyond Vdd, the capacitor charges. The charging of this capacitor causes the FET switching transistor to turn Off. The switching Off of an FET during ESD events makes the SCR change into a FWSCR (floating-well SCR) to provide better ESD performance. However, in normal operation, the FET will be turned On so that the N-well will be reconnected to Vdd. Thus, the invention becomes a conventional SCR (Not FWSCR) to provide better latch-up immunity during normal operation. In addition, the method of designing ESD protection circuits provides latch-up immunity for the SCR by including a discharge resistor attached to the said capacitor. Once the ESD event has passed, the above capacitor discharges through the resistor during a pre-designed time constant. This allows the SCR to return to its non-latched state and allows the FET transistor to switch back On, effectively reconnecting the SCR to the supply voltage Vdd. Therefore, this method prevents the protection circuit from remaining in an SCR latched up state after the occurrence of an ESD event. This is what is known as latch-up immunity.

[0017] FIG. 1ashows prior art lateral (LSCR) SCR ESD CMOS cross-section.

[0018] FIG. 1bshows prior art lateral (LSCR) SCR ESD protection circuit.

[0019] FIG. 1cshows prior art voltage trigger (LVTSCR) SCR ESD CMOS cross-section.

[0020] FIG. 1dshows prior art voltage trigger (LVTRSCR) SCR ESD protection circuit.

[0021] FIG. 2ashows prior art floating well (FWSCR) SCR ESD CMOS cross-section.

[0022] FIG. 2bshows prior art floating well (FWSCR) SCR ESD protection circuit.

[0023] FIG. 2cshows prior art MOS incorporated triggering (MIT-SCR) SCR ESD CMOS cross-section.

[0024] FIG. 2dshows prior art MOS incorporated triggering (MIT-SCR) SCR ESD protection circuit.

[0025] FIG. 3ashows the CMOS structure of the floating well circuit of the invention.

[0026] FIG. 3bshows the circuit diagram of the floating well structure of the invention.

[0027] FIG. 3cshows the current-time graph during HBM-ESD pulse of the circuit given in FIG. 3b.

[0028] FIG. 4ashows the current-voltage characteristic of the SCR of the invention.

[0029] FIG. 4bshows the integrated circuit layout of the circuit of the invention.

[0030] FIG. 5 shows the CMOS cross-section of the circuit layout of FIG. 4b.

[0031] FIG. 6ashows floating well invention variation #1.

[0032] FIG. 6bshows floating well invention variation #2.

[0033] FIG. 6cshows floating well invention variation #3.

[0034] FIG. 3ashows a cross-section of a CMOS SCR circuit (PNPN). The embodiment of this invention shown by the floating-well (FW) circuit 310 placed between the supply voltage Vdd and the N well 320 of the SCR. FIG. 3bshows a schematic of one embodiment of the FW circuit.

[0035] The supply voltage Vdd is now attached to FW node 360 instead of to the N+N well of the SCR. A capacitor 340 is connected between the Vdd node 360 and node 380. A resistor 350 is connected between node 380 and 390 that is ground. A p-channel metal-oxide semiconductor field effect transistor (MOSFET) 370 has its drain connected to Vdd 360, its source connected to 320 in FIG. 3b, the N-well of the SCR and its gate connected to 380. During normal operation without electrostatic discharge ESD events, FET 370 is ON and the N-well of the SCR 320 is at the Vdd voltage level. With this voltage level, the SCR is OFF and the electronic circuits on the same semiconductor dye operate normally. The well-connected SCR will provide better latch-up immunity. That is, the SCR should not be turned ON.

[0036] When there is an ESD event, the capacitor 340 in FIG. 3bcharges up due to the ESD voltage spike. This capacitive charge causes FET 370 to turn OFF. This causes the voltage at node 320 at the N-well to increase effectively latching up the SCR in its low impedance ON stateThis low impedance SCR state will conduct or bypass ESD current effectively so that it will provide better ESD performance during ESD events.

[0037] The R 350 and C 340 in FIG. 3bform a time constant RC which cane be specified to allow the charge on C 340 to discharge as a function of the RC time constant. After C discharge, the p-charged FET turns back on to allow Vdd voltage level to reach the N-well 320 once again. The RC discharge part of the FW circuit of FIG. 3b is an important feature of this invention. It allows the ESD protection circuit to have latch-up immunity.

[0038] FIG. 3cillustrates voltage vs. time. The voltages shown are the voltage at the gate of the FET 370 in FIG. 3band the supply voltage Vdd. The solid line 375 is the HBM-ESD waveform. The dashed line 385 is the current waveform at node G 370 in FIG. 3b.

[0039] FIG. 4ashows laboratory results of current vs. voltage for an SCR 410 and for a floating-well SCR (FWSCR) 420. The data plotted with squares 410 shows a well-connected SCR. This SCR data shows poor ESD performance (It=0.75 A). The data plotted with circles 420 shows a floating-well SCR. This SCR data shows the better ESD performance of the floating-well SCR (It=2.5 A).

[0040] FIG. 4bshows a top view of the layout of an NMOS+FWSCR circuit. The cross-section line 430 is a point of reference for the semiconductor side view given in FIG. 5.

[0041] FIG. 5 shows a typical input/output semiconductor pad 510. FIG. 6ashows the same floating-well SCR (FWSCR) circuit block as the one given in FIG. 3b. This is the first embodiment of the FWSCR of this invention. This first embodiment is described above in the description of FIG. 3. FIG. 6bgives the second embodiment of the FWSCR. The FET device 670 has its drain connected to Vdd 660, its source connected to the N-well of the SCR 620, and its gate connected to 680. The capacitor 640 is attached between Vdd 660 and the gate of FET 680. A second FET 675 has its drain attached to node 680, its source attached to ground 690, and its gate attached to 685. The resistor is attached between Vdd 660 and noded 685. A second capacitor 645 is attached between node 685 and ground 690.

[0042] FIG. 6cgives the third embodiment of the FWSCR. The FET device 672 has its drain connected to Vdd 662, its source connected to the N-well of the SCR 622, and its gate connected to 682. The capacitor 642 is attached between Vdd 662 and the gate of FET 682. A second FET 677has its drain attached to node 682, its source attached to ground 692, and its gate attached to 682. There is no resistor in this third embodiment. Also, there is no second capacitor in this third embodiment.

[0043] This invention has the advantage of better ESD perfomance during ESD events. It also has the advantage of better latch-up immunity during normal operation.

[0044] While this invention has been particularly shown and described with Reference to the preferred embodiments thereof, it will be understood by those Skilled in the art that various changes in form and details may be made without Departing from the spirit and scope of this invention.