Demodulation method and demodulator

[0002] 1. Field of the Invention

[0003] The present invention relates to a demodulation method for demodulation by converting analog signal obtained by reading information memorized in a recording medium to digital signal so as to generate data representing the information and a demodulator.

[0004] 2. Description of the Related Art

[0005] Since before, there has been an information recording/reproducing apparatus for recording information in a recording medium and reproducing information by reading it from that recording medium. The information recording/reproducing apparatus includes, for example, a magnetic disc unit in which information is recorded on a magnetic disc and the information is reproduced by reading out from the magnetic disc.

[0006] FIG. 9 is an outline diagram showing a magnetic disc unit, which is an example of such an information recording/reproducing apparatus.

[0007] A magnetic disc 10 is rotated in a direction indicated by an arrow A around a center shaft 11 by a spindle motor (not shown).

[0008] An actuator 20 is rotated around a rotation shaft 21 so as to move a magnetic head 30 provided on a front end thereof in a radius direction (a direction of arrow B) of the magnetic disc 10 along the surface of the magnetic disc 10. The magnetic head 30 records information based on signal sent from a signal recording/reproducing portion 40 into the magnetic disc 10 and picks up information recorded in the magnetic disc 10 and sends it to the signal recording/reproducing portion 40.

[0009] The signal recording/reproducing portion 40 receives data signal carrying recording information form outside when the information is recorded to the magnetic disc 10 and carries out a predetermined processing including run length limited (RLL) coding. The magnetic head 30 is driven according to a signal after the processing, so as to record information in the magnetic disc 10. On the other hand, when the information is reproduced from the magnetic disc 10, error correction processing and RLL decoding processing are carried out on signal picked up by the magnetic head 30 and sent out of this magnetic disc unit.

[0010] Servo information for controlling the position of the magnetic head 30 with respect to the magnetic disc 10 as well as ordinary information for read/write are recorded in the magnetic disc 10. This servo information is picked up by the magnetic head 30 and sent to the position control portion 50 through the signal recording/reproducing portion 40. The position control portion 50 controls an operation of the actuator 20 for the magnetic head 30 provided at a front end of the actuator 20 to move with respect to the magnetic disc 10 to a desired position based on the information.

[0011] FIG. 10 is a block diagram of a conventional demodulator which composes a signal reproducing portion for reproducing data indicating information recorded in the magnetic disc 30 from signal picked up by the magnetic head 30, in the signal recording/reproducing portion 40 of the magnetic disc unit shown in FIG. 9.

[0012] Analog signal obtained by a signal pickup of the magnetic head 30 is inputted to gain control amplifier (GCA) 101 capable of changing amplification factor in the demodulator 100 and amplified appropriately. Output analog signal from the GCA 101 is inputted to an analog equalizer 102 and equalized by this equalizer. After that, this signal is converted to digital signal by the A/D converter 103 and maximum likelihood is detected by a maximum likelihood detector 102. A result of maximum likelihood detection is RLL decoded by a RLL decoder. Then, an error is corrected by error correction code (ECC)106 so as to reproduce right data.

[0013] Here, the digital signal outputted from the A/D converter 103 is also inputted to an automatic gain control (AGC) 107 and phase locked loop (PLL) 108.

[0014] Prior to description of an operation of the AGC 107 and PLL 108, first, data structure of information to be picked up from the magnetic disc 30 will be described.

[0015] FIG. 11 is a diagram showing data structure of information to be picked up from the magnetic disc.

[0016] First, acquisition portion GAP is disposed and next, sync byte portion SB for indicating a start of proper data is disposed followed by the proper data.

[0017] The AGC 107 and PLL 108 shown in FIG. 10 use signal from the acquisition portion GAP. The AGC 107 adjusts amplification factor of the GCA 101 based on the output digital signal from the A/D converter 103 of the acquisition portion GAP so that appropriately amplified signal is outputted from the GCA 101. The PLL 108 generates a clock signal which is a reproduction of a clock upon recording of information, based on the output digital signal from the A/D converter 103. Signal amplified appropriately depending on the size of signal picked up by the magnetic head is outputted from the GCA 101 to the sync byte portion SB at a timing in which actual data is inputted. A/D conversion is carried out by the A/D converter 103 at a clock reproduced to be same as the clock upon recording information.

[0018] Because in recent years, high density recording has been accelerated in information recording/reproducing apparatus such as magnetic disc unit, noise increases in the acquisition portion GAP resulting therefrom, so that a minute defect in a recording medium affects relatively largely. If the defects in the recording medium are accumulated in the recording portion of the acquisition portion GAP, adjustment of the amplification factor and reproduction of the clock by the AGC 107 and PLL 108 are not carried out excellently. Consequently, so-called cycle skip and A/D converter clamp occur so that a long burst error may occur. If the burst error occurs, correction is disabled even if a high performance ECC 106 is employed, so that accurate data reproduction is disabled. Thus, the performance of the demodulator is determined depending on how accurately the AGC and PLL are operated.

[0019] In views of the above-described problem, the present invention intends to provide a demodulation method and a demodulator capable of obtaining correct data even if S/N ratio is lower than conventional.

[0020] To achieve the above object, according to an aspect of the present invention, there is provided a demodulation method for demodulation by converting analog signal carrying a first clock of a predetermined first frequency obtained by reading information recorded in a recording medium to digital signal so as to generate data representing the information, wherein

[0021] the analog signal is converted to a first digital signal by over-sampling synchronous with a second clock of a second frequency higher than the frequency of the first clock and

[0022] a phase error of the first clock with respect to the second clock is obtained based on the first digital signal.

[0023] According to another aspect of the present invention, there is provided a demodulator for demodulation by converting analog signal carrying a first clock of a predetermined first frequency obtained by reading information recorded in a recording medium to digital signal so as to generate data representing the information, the demodulator comprising:

[0024] an A/D converter for converting the analog signal to a first digital signal by over-sampling synchronous with a second clock of a second frequency higher than the frequency of the first clock;

[0025] a buffer for storing the first digital signal; and

[0026] an operating portion for obtaining a phase error of the first clock with respect to the second clock based on the first digital signal stored in the buffer.

[0027] According to the demodulation method and demodulator of the present invention, over-sampling is carried out synchronously with a clock (second clock) having a higher frequency (second frequency). A first digital signal obtained by the over-sampling is converted to a second digital signal synchronous with a clock (first clock) of a proper frequency (first frequency). Then, the second digital signal obtained in that way is decoded. Therefore, the necessity of the acquisition portion is eliminated thereby formatting efficiency being improved.

[0028] According to the present invention, the clock frequency (first frequency) of the first clock and phase are extracted by computation on data. Therefore, even if the S/N ratio is low, it is possible to eliminate a burst error which is generated conventionally when leading into the PLL (arrival to proper operation) is incomplete, so as to achieve normal operation of the demodulator.

[0029] Meanwhile, the AGC and GCA shown in FIG. 10 can be adjusted by adjusting data value corresponding to an amplification factor of the GCA on data because the present invention depends on mainly computation on data. Therefore, for example, the amplification factor of the GCA can be maintained at a fixed value while omitting the AGC, instead of changing the amplification factor of the GCA largely.

[0030] Preferably, in the demodulator of the present invention, the operating portion comprises:

[0031] a Fourier transforming portion for Fourier-transforming the first digital signal;

[0032] a clock extracting portion for obtaining the first frequency and an initial phase of the first clock with respect to the second clock from Fourier transformation signal obtained from the Fourier transformation by the Fourier transforming portion; and

[0033] a phase error computing portion for obtaining a phase error of each clock pulse of the first clock with respect to the second clock based on the first frequency and the initial phase obtained by the clock extracting portion.

[0034] In this case, the clock extracting portion may obtain the first frequency by linear estimation of amplitude values of frequencies before and after the first frequency based on amplitude information of the amplitude information and phase information composing the Fourier transformation signal, and may obtain the initial phase by linear interpolation using the phases of frequencies before and after the first frequency based on the phase information.

[0035] Further, the operating portion may further comprise an interpolation computing portion for obtaining a second digital signal synchronous with the first clock by interpolating the first digital signal based on phase error information obtained by the phase error computing portion.

[0036] For example, by this computation, the first clock can be obtained at a sufficient accuracy, and the second digital signal, which is a proper signal, can be generated from the first digital signal obtained by over-sampling at a sufficient accuracy.

[0037] Further, preferably, the demodulator of the present invention is provided with an equalizer for equalizing analog signal obtained by reading information stored in the recording medium at a pre-stage of the A/D converter. Further, it is permissible to provide a low-pass filter portion for carrying out low-pass filtering on the analog signal obtained by reading information stored in a recording medium, at a pre-stage of the A/D converter. Further, it is also permissible to provide a FIR filter conforming to the second clock between the A/D converter and buffer so as to progress the equalization. Further, it is permissible to provide a FIR filter conforming to the first clock between the operating portion and demodulating portion so as to progress the equalization.

[0038] In any case, demodulation to correct data is urged.

[0039] Further, in the demodulator of the present invention, the above-described demodulating portion may be provided with an error correction code portion which acts as a buffer at the same time.

[0040] Sharing the buffer leads to reduction of the circuit size.

[0041] As described above, according to the present invention, it is possible to raise a probability that correct data can be obtained from signal having low S/N ratio, as compared to the conventional technology.

[0042] FIG. 1 is a block diagram showing a demodulator according to the first embodiment of the present invention.

[0043] FIG. 2 is a diagram showing data structure employed when the demodulator of FIG. 1 is applied to a magnetic disc unit shown in FIG. 9.

[0044] FIG. 3 is an explanatory diagram showing a method for obtaining the frequency of a proper clock in a clock extracting portion of FIG. 1.

[0045] FIG. 4 is a diagram showing a relation between a mth clock sampling point of a proper clock and nth and n+1th clock sampling points of over-sampling clocks sandwiching the former clock on time axis.

[0046] FIG. 5 is a block diagram showing a demodulator according to the second embodiment of the present invention.

[0047] FIG. 6 is a block diagram showing a demodulator according to the third embodiment of the present invention.

[0048] FIG. 7 is a block diagram showing a demodulator according to the fourth embodiment of the present invention.

[0049] FIG. 8 is a block diagram showing a demodulator according to the fifth embodiment of the present invention.

[0050] FIG. 9 is an outline diagram of a magnetic disc unit.

[0051] FIG. 10 is a block diagram of a conventional demodulator.

[0052] FIG. 11 is a diagram showing the data structure of information picked up from the magnetic disc.

[0053] Hereinafter, the preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0054] FIG. 1 is a block diagram showing a demodulator according to the first embodiment of the present invention.

[0055] Conceptually, a demodulator 100A shown in FIG. 1 can be incorporated in a signal recording/reproducing portion 40 of a magnetic disc unit shown in FIG. 9 instead of a conventional demodulator 100 shown in FIG. 10. In FIG. 1 and other figures describing various demodulators, which will be referred to, like reference numerals shown in FIG. 10 are attached to the same components as the demodulator 100 shown in FIG. 10 and mainly a different point will be described.

[0056] FIG. 2 is a diagram showing data structure employed when the demodulator 100A of FIG. 1 is applied to the magnetic disc unit shown in FIG. 9.

[0057] The data structure shown in FIG. 2 indicates a type in which acquisition portion GAP is omitted as compared with the data structure employed conventionally shown in FIG. 11 and comprises sync byte portion SB and actual data.

[0058] Analog signal carrying the data structure shown in FIG. 2, which was picked up by the magnetic head 30 (see FIG. 9), is inputted into the GCA 101 of the demodulator 100A shown in FIG. 1 and amplified appropriately. Here, the amplification factor of the GCA 101 is fixed.

[0059] An analog signal outputted from the GCA 101 is equalized by an equalizer 102 and converted to digital signal by an A/D converter 103A. The A/D converter 103A carries out quick A/D conversion by over-sampling using an over-sampling clock (equivalent to a second clock mentioned in the present invention) having a higher frequency (equivalent to a second frequency mentioned in the present invention) than a frequency (equivalent to a first frequency mentioned in the present invention) of a clock (equivalent to a first clock mentioned in the present invention) upon recording of information. Digital signal (equivalent to a first digital signal mentioned in the present invention) obtained from the over-sampling in the A/D converter 103A is stored in a buffer 111 temporarily. Digital signal stored in this buffer 111 is inputted into an operating portion 110. A detailed operation algorithm will be described later. This operating portion 110 obtains the frequency of a proper clock (first clock) and a phase of the proper clock with respect to the over-sampling clock (second clock). A digital signal (equivalent to a second digital signal mentioned in the present invention) equivalent to a digital signal obtained from sampling synchronous with the proper clock is generated by linear interpolation operation by a linear interpolating portion 115 which is a component of the operating portion 110.

[0060] According to this embodiment, as described above, the over-sampling is carried out and then, a digital signal equivalent to a digital signal synchronous with the proper clock is reproduced by an operation on the digital signal. Consequently, first, as shown in FIG. 2, the acquisition portion GAP (see FIG. 11) becomes unnecessary thereby format efficiency being improved. Second, the PLL 108, which is employed in the conventional demodulator 100 of FIG. 10, becomes unnecessary and it is possible to eliminate a burst error, which occurs when the PLL is not operated properly because S/N of an analog signal picked up by the magnetic head is poor, so that a high precision data demodulation can be expected.

[0061] According to this embodiment, signals of a sector are stored in the buffer 111 all at once. In the operating portion 110 and subsequent processings, the signals of a sector are processed as a batch simultaneously.

[0062] Subsequent operation processing of a digital signal (second digital signal) obtained from interpolation in the linear interpolating portion 115 of the demodulator 100A of the first embodiment shown in FIG. 1 is the same as a processing explained with reference to FIG. 10. A processed digital signal is inputted to a maximum likelihood detector 104 so as to detect maximum likelihood. Its maximum detection result is RLL decoded by PLL decoder 105 and then, an error is corrected by an ECC 106 so as to reproduce new data.

[0063] According to this embodiment, as described above, the amplitude factor of the GCA 101 is fixed. Thus, if the frequency or phase of the proper clock (first clock) cannot be extracted by the operating portion 110 or a proper operation is not carried out in the maximum likelihood detectors 104, RLL 105, and ECC 106, the digital signal stored temporarily in the buffer 111 is amplified or attenuated and then, by operating again, a proper operation is enabled. The conventional demodulator shown in FIG. 10 includes AGC 107 so as to control the amplification factor of the GCA 101. The reason is that because the conventional demodulator cannot repeat the operation unless the analog signal is picked up from the magnetic head, the amplification factor of the GCA 101 has to be controlled to be optimum. Although an excellent effect is produced when the amplification factor of the GCA 101 is controlled to be optimum, if the amplification factor shifts largely as described above, a clamp occurs in the A/D converter so that a long burst error may occur.

[0064] Next, the operating portion 110 of the demodulator 100A shown in FIG. 1 will be described. A digital signal, which is obtained by over-sampling in the A/D converter 103A and stored in the buffer 111 temporarily, is inputted to a Fourier transforming portion 112. Then, discrete Fourier transformation is carried out in this Fourier transforming portion 112 and after the Fourier transformation, data is sent to the clock extracting portion 113. This clock extracting portion 113 detects a peak having a large spectrum based on the data after Fourier transformation. Consequently, the frequency of the proper clock (first clock) and an initial phase of the proper clock (first clock) with respect to an over-sampling clock (second clock) are obtained.

[0065] If the over-sampling is carried out with an over-sampling clock (second clock) of a frequency n times the frequency of the proper clock, the frequency of the proper clock (first clock) is frequency 1/n times the Nyquist frequency of over-sampling. Here, n is set to 1.0<n<2.0 in order to suppress the speed of the A/D conversion. Thus, it comes that the frequency of the proper clock is located in the middle of discrete spectrum obtained by discrete Fourier transformation. The frequency (first frequency) of the proper clock (first clock) and the initial phase are obtained as follows.

[0066] FIG. 3 is an explanatory diagram showing a method for obtaining the frequency of a proper clock in a clock extracting portion of FIG. 1.

[0067] In FIG. 3, the axis of abscissa ω indicates angular frequency and the axis of ordinate indicates spectrum |X(jω)|. Where X(jω) indicates data (j is an imaginary unit) obtained by discrete Fourier transformation and |X(jω)| indicates its absolute value.

[0068] ω_k−2, ω_k−1, ω_k, ω_k+1on the axis of abscissa of FIG. 3 indicate discrete angular frequencies of k−2th, k−1th, kth and k+1th and empty circles indicate spectrum of each discrete angular frequency. ω_con the axis of abscissa indicates the angular frequency of a proper clock intended to be obtained.

[0069] In the Fourier transforming portion 112 shown in FIG. 1, assuming that a sequence of signals read out from the buffer 111 is x(nT) (where n is a sampling number and T is a sampling interval) and a sum of samplings is N, the Fourier transforming portion 112 carries out discrete Fourier transformation based on a following expression. $\begin{array}{cc}X\left(j{\omega }_k\right)=\sum _{n=0}^{N-1}x\left(nT\right)e^{-j\frac{2\pi nk}{N}}& \left(1\right)\end{array}$

[0070] However, for the expression (1) to be formed, when it is assumed that the angular frequency of the proper clock is ω_cand the angular frequency of over-sampling is ω_s, a following expression has to be satisfied. $\begin{array}{cc}{\omega }_s\geqq \frac{N}{N-2}{\omega }_c& \left(2\right)\end{array}$

[0071] The angular frequency ω_cof the proper clock shown in FIG. 3 can be obtained from a following expression. $\begin{array}{cc}\left|X\left(j{\omega }_k\right)\right|=\frac{\begin{array}{c}\left\{\left|X\left(j{\omega }_{k+1}\right)\right|-\left|X\left(j{\omega }_k\right)\right|\right\}{\omega }_k-\left\{\left|X\left(j{\omega }_{k-1}\right)\right|-\left|X\left(j{\omega }_{k-2}\right)\right|\right\}{\omega }_{k-1}+\\ \frac{2\pi }{NT}\left\{\left|X\left(j{\omega }_{k-1}\right)\right|-\left|X\left(j{\omega }_k\right)\right|\right\}\end{array}}{\left|X\left(j{\omega }_{k+1}\right)\right|-\left|X\left(j{\omega }_k\right)\right|-\left|X\left(j{\omega }_{k-1}\right)\right|-\left|X\left(j{\omega }_{k-2}\right)\right|}& \left(3\right)\end{array}$

[0072] At this time, the initial phase θ(ω_c) of the proper clock with respect to the over-sampling clock can be obtained from a following expression. $\begin{array}{cc}\theta \left({\omega }_c\right)=\frac{\theta \left({\omega }_k\right)-\theta \left({\omega }_{k-1}\right)}{{\omega }_k-{\omega }_{k-1}}\left\{{\omega }_c-{\omega }_{k-1}\right\}+\theta \left({\omega }_{k-1}\right)& \left(4\right)\end{array}$

[0073] where θ(ω_k), θ(ω_k−1) are phases of angular frequencies ω_k, ω_k−1respectively.

[0074] The proper frequency (first frequency) and initial phase obtained according to the expressions (3), (4) in the clock extracting portion 113 of FIG. 1 are inputted to a phase error computing portion 114. The phase error computing portion 114 obtains a phase error with respect to the over-sampling clock of each clock pulse composing the proper clock (first clock) based on the inputted frequency and initial phase. That is, first, a mth clock sampling point of the proper clock (first clock) is converted to a phase at timing of the over-sampling clock. A phase θ_c(m) of a mth clock sampling point can be expressed as follows when the initial phase is θ_o. $\begin{array}{cc}\begin{array}{c}{\theta }_c\left(m\right)={\theta }_0+2\pi m·W_s/W_c\\ ={\theta }_0+2\pi m·T_c/T_s\end{array}& \left(5\right)\end{array}$

[0075] A phase of a nth clock sampling point of the over-sampling clock is expressed as follows.

[0076] θ_s(n)=2πn  (6)

[0077] Consequently, a phase error of the phase θ_c(m) of the mth clock sampling point of the proper clock relative to phases θ_s(n), θ_s(n+1) of nth and n+1th clock sampling points respectively of the over-sampling clock, which sandwich the mth clock sampling point of the proper clock on time axis, can be obtained here. Here is

[0078] θ_s(n)≦θ_c(m)≦θ_s(n+1)  (7)

[0079] If the expressions (5), (6) are substituted into the expression (7), a following expression can be obtained. $\begin{array}{cc}{\mathrm{nT}}_s\leqq \frac{{\theta }_0}{2\pi }{T}_s+{\mathrm{mT}}_c\leqq \left(n+1\right)T_s& \left(8\right)\end{array}$

[0080] FIG. 4 is a diagram showing a relation between the mth clock sampling point of the proper clock on time axis and nth and n+1th clock sampling points of the over-sampling clock, which sandwich the former.

[0081] The phase error obtained by the phase error computing portion 114 of FIG. 1 is inputted to the linear interpolating portion 115. In the linear interpolating portion 115, a signal value $x\left(\frac{{\theta }_0}{2\pi }{T}_s+{\mathrm{mT}}_c\right)$

[0082] of the mth clock sampling point of the proper clock can be obtained from signal values x(nT_s), x((n+1)T_s) of the nth and n+1th over-sampling clock shown in FIG. 4 according to a following expression. $\begin{array}{cc}x\left(\frac{{\theta }_0}{2\pi }{T}_s+{\mathrm{mT}}_c\right)=\{x(\left(n+1\right)T_s-x\left({\mathrm{nT}}_s\right)\}\left\{\frac{{\theta }_0}{2\pi }{T}_s+{\mathrm{mT}}_c-n\right\}+x\left({\mathrm{nT}}_s\right)& \left(9\right)\end{array}$

[0083] As described above, the digital signal value (second digital signal) obtained in this way is sent to the maximum likelihood detector 104 so as to detect maximum likelihood. A maximum detection result is RLL decoded by a RLL decoder 105 and then, error correction is carried out by an ECC 106 to reproduce correct data.

[0084] FIG. 5 is a block diagram showing a demodulator according to a second embodiment of the present invention. A different point from the first embodiment will be described.

[0085] In the decoder 100B according to the second embodiment shown in FIG. 5, a FIR filter 116 for accelerating equalization by an equalizer 102 appropriate for digital signal A/D converted by the over-sampling clock is provided between the A/D converter 103A and buffer 111. The decoder 100B of the second embodiment intensifies equalization due to provision of the FIR filter 116 thereby making it possible to reproduce further accurate data.

[0086] FIG. 6 is a block diagram showing the third embodiment of a decoder according to the present invention. A different point from the first embodiment shown in FIG. 1 will be described.

[0087] In the decoder 100C of the third embodiment shown in FIG. 6, a FIR filter 117 which accelerates equalization by an equalizer 102 appropriate for the proper clock is disposed between a linear interpolating portion 115 composing the operating portion 110 and the maximum likelihood detector 104. The decoder 100C of the third embodiment can progress the equalization due to provision of the FIR filter 117 thereby making it possible to reproduce further accurate data like the second embodiment shown in FIG. 5.

[0088] FIG. 7 is a block diagram showing the fourth embodiment of a decoder according to the present invention. A different point from the first embodiment shown in FIG. 1 will be described.

[0089] In the decoder 100D of the fourth embodiment shown in FIG. 7, an analog low-pass filter 107 is provided instead of the equalizer 102 provided on the decoder 100A of the first embodiment shown in FIG. 1. Additionally, a FIR filter 116 is provided between the A/D converter 103A and the buffer 111 like the second embodiment shown in FIG. 5.

[0090] In the decoder 100D shown in FIG. 7, its analog circuit structure is simplified because of provision of the low-pass filter 107 instead of the equalizer 102 in the decoder 100A shown in FIG. 1. However, the equalization is not sufficient with the provision of the low-pass filter 107 alone. Thus, after conversion to digital signal by the A/D converter 103A, the equalization is accelerated by the FIR filter 116, so that sufficient equalization is achieved.

[0091] In all the embodiments including the fourth embodiment shown in FIG. 7, digital processing after the conversion to digital signal by the A/D converter 103A is carried out by firmware. Thus, analog processing is simplified even if the digital processing becomes complicated to some extent, thereby leading to reduction of the circuit size and production cost.

[0092] FIG. 8 is a block diagram showing the fifth embodiment of a decoder according to the present invention.

[0093] The ECC 106 of the decoder 100A shown in FIG. 1 is represented with a block and it contains a buffer internally although not shown here.

[0094] The decoder 100E shown in FIG. 8 contains the buffer 111 for storing digital signal obtained by over-sampling by the A/D converter 103A which is also used as a buffer for the ECC.

[0095] To achieve this, the decoder 100E shown in FIG. 8 has switches 121, 122 before and after the buffer 111. When converting to digital signal by the A/D converter 103A and interpolating the digital signal by the operating portion 110, the buffer 111 is connected to the A/D converter 103A and the linear interpolating portion 122 by these switches 121, 122. After the interpolation ends, the switches 121, 122 are changed over, so that the buffer 111 functions as a buffer for the ECC 106′.

[0096] An output signal from the RLL decoder 105 is stored in the buffer 111 and at the same time, inputted to a first computing element for carrying out syndrome operation composing the ECC 106′, so that initial values S₀, S₁, . . . S_mare generated. After that, these initial values S₀, S₁, . . . S_mare set in a second computing element for computing an error location and error size. At the same time, a signal form the buffer 111 is inputted to the second computing element and finally a corrected data is outputted. The ECC itself is a conventionally well-known technology and therefore, a detailed description thereof is omitted.

[0097] After computation for data of a sector in the ECC 106′ is completed, the switches 121, 122 are changed over to a direction for connecting the buffer 111 to the A/D converter 103A and the linear interpolating portion 115 again. Then, an input of a signal of next sector is started.

[0098] In case of the decoder 100E shown in FIG. 8, the provision of the buffer 111 contributes to reduction of the circuit size.

[0099] In the above described respective embodiments, particularly the first embodiment, digital signal (first digital signal) obtained by the over-sampling is converted to a digital signal (second digital signal) corresponding to the proper clock by carrying out linear interpolation through computation shown by the expressions (1)-(9). However, the conversion from the first digital signal to the second digital signal does not always have to be based on the computation on the expressions (1)-(9) and the interpolation does not have to be linear interpolation. That is, it is just necessary to reproduce the second digital signal synchronous with the proper clock from the first digital signal obtained by the over-sampling.

[0100] In the above described respective embodiments, all the data structure shown in FIG. 2 is over-sampled regardless of which sync byte portion SB or actual data. However, it is permissible to over-sample only several bytes of the data portion and store in the buffer, Fourier-transform that over-sampled portion to extract the proper clock frequency and initial phase, and then sample the data portion and a remaining portion following the beginning several bytes in the data portion according to the proper clock.

[0101] In the above description, it is assumed that the embodiment of the present invention is incorporated in the magnetic disc unit. However, the present invention is not restricted to application to the magnetic disc unit. The present invention can be widely applied to a case in which analog signal obtained by reading out information stored in a recording medium is converted to digital signal and demodulated so as to generate data representing the information recorded in the recording medium.