Current limiting technique for a switching power converter

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 60/300,492, filed Jun. 21, 2001.

[0003] The invention relates to switching power converters. More particularly, the invention relates to a technique for limiting current by limiting a switching duty cycle in such a power converter.

[0004] In a conventional switching power converter, provision may be made for limiting current to a load in the event the load experiences a fault. For example, U.S. Pat. No. 5,742,151 discloses a PFC-PWM power converter in which the output current developed by the PWM section is limited in when an excessive output current is detected. More particularly, for each switch cycle, the switch is closed upon sensing an excessive output current. A drawback to this technique is that when the switch is opened for each switching cycle, an excessive current can occur before the switch is closed in response to the excessive current. This repeated occurrence of excessive current may cause excessive power dissipation in the converter.

[0005] What is needed is an improved current limiting technique for a switching power converter. It is to these ends that the present invention is directed.

[0006] The present invention is an improved technique for limiting current in a switching power converter. The power converter includes a switch for transferring energy from a source to the load by opening and closing the switch according to a duty cycle. A duty cycle limiter is triggered when the output current of the converter exceeds a predetermined level. The duty cycle is limited to an amount that is related to a degree to which the output current is excessive. In one aspect, the duty cycle limiter include a capacitor having a charge that is gradually changed in response to the output current exceeding the predetermined level where the duty cycle is related to a voltage on the capacitor. In another aspect, the duty cycle limiter includes a counter where the duty cycle is related to a count of the counter. In another aspect, the duty cycle limiter provides a soft-start in which the switching duty cycle is gradually increased upon powerup. Once the converter is operating normally, the duty cycle is controlled to regulate the output voltage.

[0007] The invention has an advantage in that by reducing the switching duty cycle, the output current is reduced and is, thus, less likely to reach an excessive level upon each cycle of the switch. In comparisons to prior techniques, this reduces power dissipation in the converter.

[0008] FIG. 1 illustrates a schematic diagram of a power converter in accordance with an aspect of the present invention;

[0009] FIG. 2 illustrates a schematic diagram of an alternate embodiment of a power converter in accordance with an aspect of the present invention;

[0010] FIGS. 3aand 3billustrate a schematic diagram of a two-stage power factor correction and pulse width modulation power converter in accordance with an aspect of the present invention;

[0011] FIG. 4 illustrates an exemplary three-input comparator that may be used with the power converters of the present invention; and

[0012] FIGS. 5aand 5billustrate a schematic diagram of a two-stage power factor correction and pulse width modulation power converter in accordance with an aspect of the present invention.

[0013] FIG. 1 illustrates a schematic diagram of a power converter 100 in accordance with an aspect of the present invention. An input voltage Vin may be applied to a first terminal of a main power switch SW1 (e.g., a transistor switch). A second terminal of the switch SW1 may be coupled to a first terminal of a second switch SW2 (e.g., a transistor switch) and to a first terminal of an inductor L. A second terminal of the inductor L may be coupled to a first terminal of a capacitor C1. A second terminal of the switch SW2 and a second terminal of the capacitor C1 may be coupled to a ground node. It will be apparent that the switch SW2 may be replaced by a diode.

[0014] A source 102 of the input voltage Vin may include a power factor correction (PFC) stage of the power converter 100. Thus, the source 102 may receive an alternating current (AC) signal and perform power factor correction in which current drawn from AC source VAC is maintained substantially in phase with the AC voltage signal so as to present a resistive load to the AC source. It will be apparent, however, that the PFC stage may be omitted, in which case, the input voltage Vin may be provided by another source that provides a regulated voltage, an unregulated voltage or a loosely-regulated voltage.

[0015] When the switch SW1 is closed, the switch SW2 is open. Under these conditions, current Iin from the source 102 charges the inductor L with energy. When the switch SW1 is opened, the switch SW2 is closed. Under these conditions, energy from the inductor L charges the capacitor C1 with energy. An output voltage Vo formed across the capacitor C1 may be used to power a load (not shown). The level of power delivered to the load may be adjusted according to the duty cycle of the switches SW1 and SW2.

[0016] A controller 104 may control the duty cycle of the switches SW1 and SW2 so as to maintain the output voltage Vo at a desired level. For this purpose, a first terminal of a resistor R1 may be coupled to receive the output voltage Vo. A second terminal of the resistor R1 may be coupled to a first terminal of a resistor R2. A second terminal of the resistor R2 may be coupled to a ground node. Accordingly, the resistors R1 and R2 form a resistive divider in which a feedback signal VFB formed at an intermediate node of the resistive divider is representative of the level of the output voltage Vo.

[0017] The feedback signal VFB may be coupled to a first input terminal of an amplifier 106. Reference voltage VREF1 that is representative of a desired level for the output voltage Vo may be coupled to a second input of the amplifier 106. Accordingly, an output of the amplifier 106 forms an error signal VEAO that is representative of a difference between the output voltage Vo and a desired level for the output voltage. The error signal VEAO may be coupled to a first input of a comparator 108. A second input of the comparator 108 may be coupled to receive a periodic ramp signal VRAMP from a ramp generator 110.

[0018] The output of the comparator 108 forms a switch control signal VSC. When the level of the ramp signal VRAMP is below the level of the error signal VEAO, the switch control signal VSC may be a logic high voltage. Then, as the ramp signal rises, it eventually exceeds the level of the error signal VEAO. In response, the switch control signal VSC may transition to a logic low voltage until the ramp signal VRAMP is reset and the process repeats. Thus, the duty cycle of the switch control signal VSC is adjusted depending upon the level of the output voltage Vo.

[0019] The switch control signal VSC may be coupled to a first (inverting) input of a logic OR gate 112. An output of the logic gate 112 may be coupled to a set input S of a flip-flop or latch 114. A reset input R of the flip-flop 114 may be coupled to receive a periodic clock signal from a duty-cycle limiter 116. A {overscore (Q)} (inverted) output PWM-OUT of the flip-flop 114 may be coupled to control the switch SW1 and the switch SW2 (via an inverter 118).

[0020] When the flip-flop 114 is reset by the duty-cycle limiter 116, the switch SW1 is closed and the switch SW2 is opened. In addition, the ramp signal VRAMP, being synchronized with the periodic clock signal from the duty-cycle limiter 116, is reset to its initial value from which it begins to rise. Under these conditions, the switch control signal VSC is a logic high voltage and the output of the logic gate 112 is a logic low voltage. Then, when the level of the ramp signal VRAMP exceeds the level of the error signal VEAO, the switch control signal VSC transitions to a logic low voltage. As a result, the flip-flop 114 is set and the switch SW1 is opened and the switch SW2 is closed. The switch SW1 remains open and the switch SW2 remains closed until the flip-flop 114 is once again reset by the duty-cycle limiter 116.

[0021] The signal PWM-OUT may differ from the signal VSC in that the signal PWM-OUT may be duty-cycle limited by a duty cycle limiter 116. The duty cycle limiter 116 may form a periodic square wave signal whose duty cycle is equivalent to a maximum duty cycle allowed for the switch SW1.

[0022] When the output voltage Vo rises, the error signal VEAO also rises. As a result, the switch SW1 remains open for a longer portion of the switching cycle because more time is required for the ramp signal VRAMP to exceed the error signal VEAO. Thus, the switching duty-cycle is reduced which tends to reduce the output voltage Vo. Conversely, when the output voltage Vo falls, the error signal VEAO also falls. As a result, the switch SW1 remains open for a shorter portion of the switching cycle because less time is required for the ramp signal to exceed the error signal VEAO. Thus, the switching duty-cycle is increased which tends to increase the output voltage Vo. Accordingly, the output voltage Vo is regulated in a closed feedback loop.

[0023] The power converter 100 of FIG. 1 is exemplary. Thus, it will be apparent that modifications can be made. For example, the exemplary power converter 100 uses trailing-edge modulation, however, leading-edge modulation may be used. As another example, the power converter 100 has buck converter topology. However, another type of converter topology may be used, such as that of a boost converter.

[0024] A current sensor 120 may be coupled to sense current in the converter 100. As shown in FIG. 1, the current sensor 120 may sense current in the inductor L. Alternately, the current sensor 120 may sense current in the switch SW1 or the switch SW2. In either case, the current sensor 120 senses a current that is representative of an output current provided to the load. Further, the current sensor 120 may be implemented in a number of different ways. For example, a resistor that is configured to receive the current to be sensed forms a voltage that is representative of the current. As another example, a current may be induced in the secondary winding of a transformer or coupled inductor. Thus, current in the inductor L may be sensed via an induced current in a second inductor (not shown) that is inductively coupled to the inductor L. Further, the current sensor 120 may form a signal that is representative of an average of the sensed current, such as by use of a filter.

[0025] The current sensor 120 forms a voltage signal DCILIMIT that is representative of the sensed current. This current-sensing signal may be coupled to a first input of a comparator 122. A second input of the comparator 122 may be coupled to receive a reference voltage VREF2 that is representative of a maximum desired level for the sensed current. An output of the comparator 122 may be coupled to a second input of the logic OR gate 112. Thus, the output of the comparator 122 may open the switch SW1 in the event that a current sensing signal DCI LIMIT exceeds a predetermined level.

[0026] As explained above, under normal operating conditions, the comparator 108 compares a signal VFB that is representative of an output voltage Vo of the converter 100 to a periodic ramp signal VRAMP in order to adjust the duty cycle of the switch SW1. Accordingly, the output voltage Vo is regulated in a feedback loop.

[0027] Upon start-up, however, a duty cycle limiting circuit arrangement 124 may provide a soft-start in which the duty cycle of the switch SW1 is limited so as to prevent excessive current in the switch SW1. Thus, a soft-start voltage Vss formed across a soft-start capacitor C2 is initially a low voltage level, when the output voltage Vo is significantly lower than the desired level. Over time, a current source 126 charges the capacitor C2. Initially, when the signal Vss is higher than the signal VEAO, the voltage Vss is compared by comparator 108 to the periodic ramp signal VRAMP. As the soft-start signal Vss increases, so does the duty cycle of the switch SW1. As a result, the output voltage Vo increases. Once the level of VEAO rises above the level of Vss, then the comparator 108 compares the signal VFB to the ramp signal VRAMP to control the duty cycle of the switch SW1. Accordingly, the comparator 108 compares the higher one of the two signals Vss and VEAO to the ramp signal VRAMP to control the duty cycle of the switch SW1.

[0028] The voltage signal DC ILIMIT is representative of the output current of a PWM stage of the converter 100 and is coupled to the comparator 122. In response to the signal DC ILIMIT exceeding a predetermined level of the reference voltage VREF2 (e.g., 1.0 volt), the comparator 122 opens the switch SW1 via a logic OR gate 112. Optionally, the comparator 122 may be disconnected from the logic OR gate 112 and the logic OR gate 112 may be provided with one less input (or replaced by an inverter). In addition, the output of the comparator 122 may be coupled to a set input of a flip-flop 128. A Q output of the flip-flop 128 may be coupled to a switch 130 (e.g., a MOSFET or bipolar transistor). The switch 130 is coupled across the capacitor C2. Thus, when the output of the comparator 122 changes to a logic high voltage, this sets the flip-flop 128 and closes the switch 130. As a result, the capacitor C2 begins to discharge through the switch 130. The capacitor C2 may be discharged during portions of the clock period used to control switching. In a preferred embodiment, a time constant for discharging the capacitor C2 is such that the capacitor C2 may lose approximately one-third of its voltage level in a single switching cycle. Thus, assuming the switch 130 is implemented by a transistor, the on-resistance relative to the value of the capacitor C2 is sufficient to provide this time constant. If needed, a resistor (not shown) may be coupled in series with the switch 130. A set input of the flip-flop 128 may coupled to an output of the duty cycle limiter 116. Accordingly, the flip-flop 128 is reset at the beginning of the next cycle for the switch SW1. This opens the switch 130. As a result, the current source 126 begins to charge the capacitor C2.

[0029] Thus, in the event of a “hard” short in the load, in which the load impedance falls to nearly zero, the capacitor C2 will be discharged to nearly ground level within a few switching cycles. As a result, the duty cycle of the switch SW1 will be limited further by operation of the comparator 108 than by the comparator 122. In the event of a “soft short” in which the load impedance falls below expected levels, but not to zero, then the capacitor C2 will not be completely discharged. As a result, the duty cycle of the switch SW1 will be less limited than in the event of a hard short. Thus, under these conditions, the output voltage may continue to be regulated. It will be apparent, therefore, that the duty cycle of the switch SW1 (and the switch SW2) may be limited by an amount that is related to the level of the output current and, thus, the degree of the fault.

[0030] FIG. 2 illustrates a schematic diagram of an alternate embodiment of a power converter 100′ in accordance with an aspect of the present invention. As shown in FIG. 2, the soft-start capacitor C2 and current source 126 of the duty cycle limiter of FIG. 1 may be replaced with a counter 132 having its output coupled to a digital-to-analog converter 134. An output of the digital-to-analog converter 134 may be coupled to the input of comparator 108 in place of the signal Vss. Upon start-up, the counter 132 may begin counting (e.g., counting up from zero). When the output of the comparator 122 is a logic high voltage, the counter 132 may be reset to zero or to some other value in order to limit the duty cycle in the event of fault which causes an excessive output current. Alternately, during periods that the Q output of the flip-flop 128 is a logic high voltage, the counter 132 may be programmed to change the count gradually (e.g., by counting down). When the output of the analog to digital converter 134 goes beyond a limit set by the feedback signal VEAO, the output of the analog to digital converter 134 may control the duty cycle in accordance with the count.

[0031] FIGS. 3aand 3billustrate a schematic diagram of a two-stage power factor correction and pulse width modulation power converter 100″ in accordance with an aspect of the present invention. The controller 104″ of FIG. 3bdiffers from the controller 104 of FIG. 1 and the controller 104′ of FIG. 2 principally in that the controller 104″ of FIG. 3aincludes a PFC section for controlling switching of a PFC stage of the converter 100″ of FIGS. 3aand 3bin addition to a pulse-width modulation (PWM) section. In addition, rather than using a resistive divider for sensing an output voltage Vo, as in FIGS. 1 and 2, the converter 100″ of FIGS. 3aand 3bmay include a feedback arrangement 136 that having an optical isolator 138 for forming a signal VDC. The signal VDC is representative of a difference between the output voltage Vo and a desired level for the output voltage.

[0032] As shown in FIG. 3a, an under-voltage lock out (UVLO) element 140 may maintain the voltage Vss across the soft-start capacitor C2 at a low level when the controller 104″ does not have sufficient voltage at its Vcc supply for powering circuitry of the controller 104″. A comparator 142 may also maintain the voltage across the soft-start capacitor C2 at a low level when a voltage Vin developed by the PFC stage is below a predetermined level. Thus, the elements 140 and 142 ensure that the voltage across the capacitor C2 is not allowed to begin gradually increasing for start-up until the converter 100″ is appropriately conditioned to enter start-up mode. The elements 140 and 142 generally do not affect the switching duty cycle once start-up has commenced. Rather, as explained above, the duty cycle is generally adjusted in a closed feedback loop according to a level of the output voltage Vo, unless a fault occurs. When a fault occurs that results in an excessive current in the PWM stage, the comparator 122 may initiate the discharging phases of the capacitor C2, thereby reducing the switching duty cycle and, thus, the current. Further, a transistor 144 may be provided to limit the voltage across the capacitor C2.

[0033] Excessive current in the PWM stage of the converter 100″ of FIGS. 3aand 3bmay be sensed via a voltage formed across resistor R20. The resistor R20 is coupled in series with the switch SW1. Accordingly, the current through the switch SW1 is sensed by forming a voltage across the resistor R20. A resistor R19 and a capacitor C17 are configured such that a current that is representative of the sensed current may charge the capacitor C17 during each switching cycle. The capacitor C17 may be discharged once for each switching cycle by a transistor 146 which is coupled to receive the duty-limit signal from the duty cycle limiter 116. Accordingly, the voltage on the capacitor C17 may be used to form the ramp signal VRAMP which is applied to the comparator 108 for controlling the switching duty cycle in the PWM stage. In addition, the voltage on the capacitor C17 may also be applied to the comparator 122 for determining whether the sensed current is excessive. More particularly, the comparator 122 compares the voltage across the capacitor (which is representative of the current through the switch SW1), to the reference level VREF2.

[0034] FIG. 4 illustrates an exemplary embodiment of the three-input comparator 108 in accordance with an aspect of the present invention. A current source 148 may be coupled to a source of P-type transistors M1, M2 and M3. A drain of the transistor M1 may be coupled to a drain of an N-type transistor M4. Drains of the transistors M2 and M3 may be coupled together, to a drain of an N-type transistor M5 and to a gate of an N-type transistor M6. A current source 150 may be coupled to a drain of the transistor M6. Sources of the transistors M4, M5 and M6 may be coupled to a ground node.

[0035] An inverting input Vn for the comparator 108 may be at the gate of transistor M1. A first non-inverting input Vp1 for the comparator 108 may be at the gate of transistor M2. A second non-inverting input Vp2 for the comparator 108 may be at the gate of the transistor M3. Accordingly, referring to FIGS. 1-3, the signal VEAO may be coupled to the gate of the transistor M1, the signal VRAMP may be coupled to the gate of the transistor M2 and the signal Vss may be coupled to the gate of the transistor M3. An output for the comparator 108 may be at the drain of the transistor M6. Accordingly, referred to FIGS. 1-3, the drain of the transistor M6 may be coupled to the logic gate 112.

[0036] The comparator 108 of FIG. 4 is exemplary. Accordingly, it will be apparent that another embodiment of the comparator 108 may be used.

[0037] FIGS. 5aand 5billustrate a schematic diagram of a two-stage power factor correction and pulse width modulation power converter in accordance with an aspect of the present invention. An example of such a power converter is available under part number CM6900 from Champion Microelectronic Corporation, located at 4020 Moorpark Avenue, Suite 105, San Jose, Calif.

[0038] Advantages of the invention include further limiting power dissipation in the event of an excessive current condition and an ability to continue to regulate the output voltage in the event of certain excessive current conditions.

[0039] Thus, while the foregoing has been with reference to particular embodiments of the invention, it will be appreciated by those skilled in the art that changes in these embodiments may be made without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims.