Functional clock observation controlled by JTAG extensions

[0002] The present invention is related to the subject matter of the following commonly assigned copending U.S. patent application, Ser. No. 09/504,973, which was filed concurrently with the present application, on the same day.

[0003] The content of the above-referenced copending patent application Ser. No. 09/504,973 is incorporated herein by reference.

[0004] The present invention relates to a system for functional clock observation, controlled by JTAG extensions, for the purpose of verifying the integrity of signals

[0005] The problem to be addressed is that clock signals present inside a VLSI module or chip need to be observed at the chips outputs, for the purpose of verifying the integrity of the signals. These clock signals are generated inside the chip (by a PLL 102 or other clock generation circuitry 104). If these signals are not being generated correctly, incorrect chip operations can result., or chip timing margins may be degraded. These types of Chip failures and problems that occur due to incorrect clocks are frequently very difficult to diagnose without the clocks being observable. This makes the ability to observe the clocks a highly desirable feature for any chip containing complex clock generation circuitry, such as a PLL. The present invention addresses these problems.

[0006] If the chip has spare output pins that would otherwise be unused, then providing clock observations is a simple matter of connecting the clock signals to the output pins. Since this frequently is not the case, it is necessary to multiplex functional chip signals with the clock signals. This allows a common set of chip output pins to be used for both normal functional signals, as well as the clock signals. However, since the clock signals being observed may not be operating correctly, it is necessary that the circuitry which controls the multiplexing circuitry, be completely independent of the clock signals themselves.

[0007] The present invention solves the problem outlined above, by adding circuitry to the part of the chip which implements IEEE Standard 1149.1 (IEEE Test Access Port and Boundary Scan Architecture, A.K.A. JTAG). Since JTAG circuitry uses clocking that is required to be independent of any other clocking domains on the chip, the requirement detailed above is met.

[0008] Furthermore, by adding the clock observation control circuity there, the already existing chip input and output pins which are used to provide the required JTAG signals, may also be used to access the clock observation circuitry. This solves the problem detailed above, without requiring any additional chip pins to be used to control the clock observation circuitry.

[0009] FIG. 1 This represents a description of the problem showing a ASIC (Chip).

[0010] FIG. 2 shows JTAG (IEEE 1149.1) Overview showing a ASIC (Chip)

[0011] FIG. 3 representation the solution of the problem as outlined in the Summary and description of the invention.

[0012] A JTAG design-specific data register (DSR) is added to the JTAG design. A latch (Itch) is also added. This latch is used to control the clock observation multiplexer that is selected between a clock signal and a functional signal. When Itch=0, the multiplexer selects the functional signal. When Itch=1, the multiplexer selects the clock signal.

[0013] When the chip's functional reset input signal is asserted, Itch is reset to “0”. This causes the clock observation multiplexer to select the functional signal, thus enabling normal functional operation of the multiplexed clock observation/functional chip output.

[0014] When any write occurs (via the JTAG interface) to the DSR, the write causes the DSR and the latch to be set to “1”. This causes the clock observation multiplexer to select the clock signal, thus enabling clock observation operation of the multiplexed clock observation/functional chip output.

[0015] The invention will now be illustrated by several FIGS. 1, 2 and 3. FIG. 1, represents a problem description of a ASIC (Chip). The Figure notes that if output clocks at location 100, are not being generated correctly, due to any reason, such as a logical error in the clock generation (location 101) logic or noise, then the types of failures which may occur are very difficult to diagnose without having observability of the output clocks at 100. A typical method to provide observability is to multiplex the output clock signals with other chip outputs.

[0016] Control of the multiplexer circuit described above, must be generated in a way that is completely independent of the output clocks being observed. This is because as noted above, the output clocks may be malfunctioning.

[0017] FIG. 2 Represents a JTAG (IEEE 1149.1) Overview of an ASIC CHIP located at 200, showing the input into the chip at 201 and the output at 202. The chip shows the scan instruction register at 203, the parallel instruction register at 204. The JTAG clock, the JTAG mode select and the JTAG Reset are seen at 205 respectively. The instruction decode is seen at 206, the scan data register select controls seen at 207. The multiplexer is located at 208.

[0018] FIG. 3 The figure represents the solution to the problem outline earlier in the Specification. The solution to the problem is achieved without requiring any dedicated chip input or output signals.

[0019] The functional chip input Reset at location 300, causes latch at 301 to reset, and chip outputs at 302, to carry functional outputs. Any write to the DSR at 303, causes the latch to be set, at 304, and the chip outputs to carry the output clocks 305. The “Parallel Design” Specific Register (DSR) is located at 306. The Clock/Functional Multiplexer(s) are located at 307 and the “Scan DSR” is located at 308.

[0020] While the invention has described with respect to a specific embodiment, it will be obvious to those skilled in this art that changes in both from and/or detail may be made without a departure from the scope and/or spirit of the invention.