Driving device having dummy circuit

[0002] 1. Field of the Invention

[0003] The present invention relates to a driving device for performing drive and control of so-called totem-pole-connected two switching devices and a technique for preventing a malfunction or incorrect action when a node or connected point between the two switching devices varies in potential.

[0004] 2. Description of the Background Art

[0005] Inverters are heavily used for power devices for driving motors, for example. An inverter is powered by a power supply of a DC voltage of several hundred volts obtained by rectifying AC voltage and has a two-phase or three-phase configuration having a circuit as a unit in which two identical power switching devices are connected in series (totem-pole-connected) to the power supply. To cause the inverter to exercise a desired inverting function, the switching devices need to be switched (turned on/off) by a driving device in a correct order. ON command and OFF command for switching are low voltage signals of about several volts outputted from a drive control circuit or the like.

[0006] The low voltage signals can be supplied as they are to one of the switching devices on the low potential side, but cannot be supplied to the other switching device on the high potential side unless a reference potential is increased in level. This is because a circuit for switching the high-potential side switching device in the driving device operates at the potential of a node of the high-potential side switching device and the low-potential side switching device serving as a reference potential.

[0007] Thus, a photocoupler has conventionally been used widely to transmit low voltage signals to the high-potential side switching device, which, however, results in a considerable increase in costs. Further, research and development has recently advanced for integrating switching devices as well as their control circuits on the same semiconductor chip, in which the photocoupler has become a bottleneck in integration.

[0008] To solve such disadvantage, there is known a technique for transmitting ON and OFF commands to the high-potential side switching device through a level shift circuit.

[0009] However, such level shift circuit is provided across both circuits for switching the high-potential side and low-potential side switching devices. Thus, when the node of the both switching devices varies in potential with switching of these switching devices, noise resulting from this potential variation induces a malfunction or incorrect action of the level shift circuit (therefore, that of the driving device), resulting in a malfunction or incorrect action of the inverter.

[0010] An object of the present invention is to provide a driving device capable of preventing a malfunction or incorrect action even if a node of two switching devices varies in potential.

[0011] According to the present invention, the driving device performs drive and control of at least a high-potential side switching device of two switching devices connected in series between a first potential and a second potential higher than the first potential. The driving device includes a control signal generator, a level shifter, a dummy circuit, a mask circuit and a discriminator. The control signal generator is configured to generate a control signal for a conducting command to bring the high-potential side switching device into a conducting state and a non-conducting command to bring the high-potential side switching device into a non-conducting state, thereby outputting the control signal from an output terminal. The level shifter is connected to the output terminal of the control signal generator and configured to level-shift the control signal with at least one level shift circuit to generate a level-shifted control signal. A node between the two switching devices has a third potential. The at least one level shift circuit and the dummy circuit each include a current path provided between the first potential and a fourth potential set higher than the third potential, and a first switching device having a main path provided on the current path and a control terminal controlling conducting/non-conducting state of the main path. The control terminal of the first switching device in the at least one level shift circuit is connected to the output terminal of the control signal generator while the first switching device in the dummy circuit is always set at the non-conducting state. The at least one level shift circuit includes a first node outputting the level-shifted control signal while the dummy circuit includes a second node corresponding to the first node. The mask circuit is connected to the first node of the at least one level shift circuit and the second node of the dummy circuit and configured to mask a signal outputted from the first node using a signal outputted from the second node to generate a masked signal. The discriminator is configured to discriminate between the conducting command and the non-conducting command on the high-potential side switching device using the masked signal.

[0012] When the third potential varies with switching of the two switching devices, currents flow through the current path of the level shift circuit and that of the dummy circuit, and signals resulting from the currents are outputted from the first node of the at least one level shift circuit and the second node of the dummy circuit. Since the first switching device of the dummy circuit is always set at a non-conducting state, the signal outputted from the dummy circuit is nothing but noise resulting from the variation in the third potential. Thus, the mask circuit can remove noise from the signal outputted from the at least one level shift circuit using the signal outputted from the dummy circuit. In other words, the mask circuit can obtain, as the masked signal, the level-shifted control signal from which noise has been removed. As a result, a malfunction can be prevented.

[0013] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0014] FIG. 1 is an explanatory circuit diagram showing a driving device according to the present invention;

[0015] FIG. 2 is an explanatory circuit diagram showing a driving device according to a first preferred embodiment of the present invention;

[0016] FIG. 3 is an explanatory circuit diagram showing a mask circuit of the driving device according to the first preferred embodiment;

[0017] FIG. 4 is a timing chart showing the operation of the driving device according to the first preferred embodiment;

[0018] FIG. 5 is an explanatory circuit diagram showing a driving device according to a second preferred embodiment of the present invention;

[0019] FIG. 6 is an explanatory circuit diagram showing a mask circuit of the driving device according to the second preferred embodiment;

[0020] FIG. 7 is an explanatory circuit diagram showing a driving device according to a third preferred embodiment of the present invention;

[0021] FIG. 8 is an explanatory circuit diagram showing a control signal generator of the driving device according to the third preferred embodiment;

[0022] FIG. 9 is an explanatory circuit diagram showing a mask circuit of the driving device according to the third preferred embodiment;

[0023] FIG. 10 is a timing chart showing the operation of the driving device according to the third preferred embodiment;

[0024] FIG. 11 is an explanatory circuit diagram showing a variant of the driving device according to the third preferred embodiment; and

[0025] FIG. 12 is an explanatory circuit diagram showing a driving device according to a fourth preferred embodiment of the present invention.

[0026] <First Preferred Embodiment>

[0027] Referring to FIG. 1, the basic structure of a driving device according to the present invention will be described.

[0028] FIG. 1 shows a driving device 10 for performing drive and control of a low-potential side switching device 2 and a high-potential side switching device 1 connected in series (so-called totem-pole-connected) in this order between a low-potential side main power supply potential (or first potential) GND and a high-potential side main power supply potential (or second potential) VH. Here, the potential GND is a ground potential, where (potential GND)<(potential VH). A load (inductive load such as a motor) not shown is connected to a connected point or node N0 between the switching devices 1 and 2.

[0029] The high-potential side switching device 1 has a power device 1psuch as an IGBT (Insulated Gate Bipolar Transistor) and a freewheel diode 1dconnected in antiparallel to each other. The power device 1pperforms a switching operation between a potential (or third potential) VS of the node N0 serving as a reference potential and the high-potential side main power supply potential VH, and is also referred to as a high-potential side power device. Similarly, the low-potential side switching device 2 has a power device 2pand a freewheel diode 2dconnected in antiparallel to each other. The power device 2pperforms a switching operation between the potential (ground potential) GND serving as a reference potential and the potential VS, and is also referred to as a low-potential side power device.

[0030] The driving device 10 is broadly divided into a high-potential side driving device 10H for performing drive and control of the switching device 1 and a low-potential side driving device 10L for performing drive and control of the switching device 2.

[0031] The high-potential side driving device 10H includes a control signal generator 100, a level shifter or level shift device 200, a dummy circuit 300, a mask circuit 400, a discriminator 500 and a high-potential side driving circuit 600. The control signal generator 100 is connected between the ground potential GND and a potential VCC set higher than the potential GND to be supplied with power. The potential VCC is determined based on the ground potential GND and is supplied from a power supply or power supply circuit 4. The mask circuit 400, discriminator 500 and driving circuit 600 are connected between the potential VS of the node N0 and a potential (or fourth potential) VB set higher than the potential VS to be supplied with power. The potential VB is determined based on the potential VS, and the potential difference between the potentials VS and VB is given by a power supply or power supply circuit 3. The level shifter 200 and dummy circuit 300 are respectively connected between the potentials GND and VB to be supplied with power.

[0032] The control signal generator 100 is configured to obtain a conducting/non-conducting command signal (hereinafter also referred to as “ON/OFF command signal”) S1 for a conducting command (hereinafter also referred to as “ON command”) to bring the high-potential side switching device 1 into a conducting state and a non-conducting command (hereinafter also referred to as “OFF command”) to bring the device 1 into a non-conducting state, thereby generating a control signal S100 in response to the ON/OFF command signal S1 to be outputted from its output terminal or output node. Here, a single ON/OFF command signal S1 contains information on both the ON command and OFF command, and a control signal S100 similarly contains information on both the commands.

[0033] The level shifter 200 is connected to the output terminal of the control signal generator 100 and includes at least one level shift circuit. The level shifter 200 is configured to level-shift (here, for step-up (or level-up)) the control signal S100 outputted from the control signal generator 100 by the at least one level shift circuit to generate and output a level-shifted control signal S200. The at least one level shift circuit has a node (or first node) for outputting the level-shifted control signal S200, which will be described in detail.

[0034] The dummy circuit 300 is connected between the potentials GND and VB in parallel to the level shifter 200. As will be described in detail, the dummy circuit 300 is of configuration substantially identical to that of the at least one level shift circuit and has a node (or second node) that corresponds to the node of the level shift circuit, for example, from which a signal S300 is outputted.

[0035] The nodes of the level shifter 200 and dummy circuit 300 are both connected to the mask circuit 400. The mask circuit 400 is configured to mask a signal (i.e., the level-shifted control signal S200 on which noise may be superimposed as will be described later) outputted from the node of the level shifter 200 by using the signal S300 outputted from the node of the dummy circuit 300 to generate and output a masked signal S400.

[0036] The discriminator 500 is configured to obtain and, by using the masked signal S400, to discriminate the conducting command and non-conducting command on the high-potential side switching device 1, thereby generating and outputting a discrimination result signal S500.

[0037] The high-potential side driving circuit 600 controls conduction/non-conduction of the switching device 1 with a control signal S600 in response to the discrimination result signal S500. The driving circuit 600 includes, for example, two N-channel MOSFETs connected in series between the potentials VS and VB for complementarily turning on/off the two MOSFETs, thereby switching the switching device 1.

[0038] Referring now to the low-potential side driving device 10L, it obtains a conducting/non-conducting command signal (ON/OFF command signal) S2 for a conducting command (ON command) to bring the low-potential side switching device 2 into a conducting state and a non-conducting command (OFF command) to bring the switching device 2 into a non-conducting state, thereby controlling conduction/non-conduction of the switching device 2 with a control signal S900 in response to the ON/OFF command signal S2. Here, a single ON/OFF command signal S2 includes information on both the ON command and OFF command.

[0039] Next, a specific structural example of the driving device 10 will be described using a driving device 11 according to the present embodiment shown in FIG. 2. FIG. 3 shows a mask circuit 401 of the driving device 11, and FIG. 4 is a timing chart for explaining the operation of the driving device 11.

[0040] As is apparent from comparison between FIGS. 1 and 2, the driving device 11 has a high-potential side driving device 11H and a low-potential side driving device 11L corresponding to the aforementioned driving devices 10H and 10L, respectively.

[0041] The driving device 11H includes a control signal generator (or selective iterative pulse signal generator) 101, a level shifter 201 having a level shift circuit 201a, a dummy circuit 301, a mask circuit 401 and a discriminator (or first discriminator) 501 as the aforementioned components 100, 200, 300, 400 and 500, respectively, and further includes the above-described driving circuit 600.

[0042] The control signal generator 101 includes an original clock signal generator 111 and a one-shot pulse generator 112, each connected between the potentials GND and VCC to be supplied with power.

[0043] The original clock signal generator 111 generates a clock signal S111 having a period of T (FIG. 4). The one-shot pulse generator 112 is configured to generate an iterative pulse signal S112 (FIG. 4) including iterative pulses (iterative pulse waveform) having the period T in synchronization with the clock signal S111. Specifically, the one-shot pulse generator 112 is configured to obtain the ON/OFF command signal S1 on the high-potential side switching device 1 and selectively output the iterative pulse signal S112 as the control signal S100 only in an ON command period T1on in the ON/OFF command signal S1. Thus, the control signal generator 101 can be called “selective iterative pulse signal generator 101” for outputting the iterative pulse signal S112 as the control signal S100 only in the ON command period T1on.

[0044] The period T of the clock signal S111 and the corresponding iterative pulses is shorter than either the period T1on or T1off in the ON/OFF command signal S1 and is set within a range of a one tenth to one several-tenth of a period of the ON/OFF command (T1on+T1off), for example.

[0045] The driving device 11 may be configured such that the control signal generator 101 outputs the iterative pulse signal S112 as the control signal S100 only in the OFF command period T1off.

[0046] The level shifter 201 includes a level shift circuit 201a. The level shift circuit 201aincludes a high voltage N-channel field-effect transistor (or first switching device) 211, a level shift resistor 212, a NOT circuit (inverter circuit) 213 and a clamping diode (or clamping device) 214. A MOSFET (or MISFET) is used for the transistor in this case, and the high voltage N-channel MOSFET is also referred to as “HVNMOS”.

[0047] The HVNMOS 211 has its source and drain connected to the ground potential GND and one terminal of the resistor 212, respectively, while the resistor 212 has the other terminal connected to the potential VB. Accordingly, a current path 210 is formed between the potentials GND and VB. A source-drain path (or main path) of the HVNMOS 211 is provided on the current path 210, and the conducting state/non-conducting state of the source-drain path is controlled by an input signal received at the gate (or control terminal) of the HVNMOS 211, thereby controlling the conducting state/non-conducting state of the current path 210. The HVNMOS 211 has its gate connected to an output terminal of the one-shot pulse generator 112 outputting the control signal S100 (corresponding to an output terminal of the control signal generator 101). The substrate potential of the HVNMOS 211 is set at the ground potential GND.

[0048] Further, the NOT circuit 213 has its input terminal connected between the drain of the HVNMOS 211 and the one terminal of the resistor 212. The output terminal of the NOT circuit 213 corresponds to the node (first node) outputting the level-shifted control signal S200. Although detailed illustration is omitted, the NOT circuit 213 is connected between the potentials VS and VB to be supplied with power.

[0049] Furthermore, the clamping diode 214 is connected between the current path 210 of the level shift circuit 201aand the potential VS. Specifically, the drain of the HVNMOS 211, the one terminal of the resistor 212 and the input terminal of the NOT circuit 213 are connected to the cathode of the clamping diode 214 while the anode of the clamping diode 214 is connected to the potential VS. Accordingly, even if a voltage drop of the resistor 212 is increased when a current flows over the current path 210, the potential at the input terminal of the NOT circuit 213 (i.e., potential at the drain of the HVNMOS 211 and at the one terminal of the resistor 212) is clamped to the potential VS and is prevented from becoming lower than the potential VS.

[0050] With such level shift circuit 201a, when the control signal S100 is on a high level (high-potential level), the HVNMOS 211 is brought into a conducting state and a current flows over the current path 210. The resistor 212 causes a voltage drop with this current, which brings the input terminal of the NOT circuit 213 to a low level (low-potential level). Therefore, the output terminal of the NOT circuit 213 is brought to a high level, so that the level-shifted control signal S200 having the same waveform as the control signal S100 (FIG. 4) but increased in potential is obtained. When the control signal S100 is on a low level, the control signal S100 is also level-shifted so that the level-shifted control signal S200 is obtained. In short, the control signal S100 making transition between the potentials GND and VCC, for example, is level-shifted to the signal S200 making transition between the potentials VS and VB.

[0051] The dummy circuit 301 includes an HVNMOS (or first switching device) 311, a resistor 312, a NOT circuit (inverter circuit) 313 and a clamping diode (or clamping device) 314. Specifically, these components 311 to 314 have characteristics (values) substantially equal to those of the components 211 to 214 of the level shift circuit 201a, respectively, and are connected in the same manner as the components 211 to 214 except that the HVNMOS 311 has its gate connected to the ground potential GND.

[0052] Specifically, the HVNMOS 311 has its source and drain connected to the ground potential GND and one terminal of the resistor 312, respectively, while the resistor 312 has the other terminal connected to the potential VB. Thus, a current path 310 is formed between the potentials GND and VB. At this time, a source-drain path (or main path) of the HVNMOS 311 is provided on the current path 310.

[0053] More specifically, the HVNMOS 311 in the dummy circuit 301 has its gate (or control terminal) connected to the ground potential GND different from the level shift circuit 201a, so that the HVNMOS 311 is always set at a non-conducting state. The substrate potential of the HVNMOS 311 is set at the ground potential GND.

[0054] Further, the NOT circuit 313 has its input terminal connected between the drain of the HVNMOS 311 and the one terminal of the resistor 312. The output terminal of the NOT circuit 313 is a node (second node) that corresponds to the node from which the level shift circuit 201aoutputs the level-shifted control signal S200. Although detailed illustration is omitted, the NOT circuit 313 is connected between the potentials VS and VB to be supplied with power.

[0055] Furthermore, the clamping diode 314 is connected between the current path 310 of the dummy circuit 301 and the potential VS. Specifically, the drain of the HVNMOS 311, the one terminal of the resistor 312 and the input terminal of the NOT circuit 313 are connected to the cathode of the clamping diode 314, while the anode of the clamping diode 314 is connected to the potential VS. This prevents the potential at the input terminal of the NOT circuit 313 from becoming lower than the potential VS.

[0056] The mask circuit 401 includes a NOT circuit 411 and a NOR circuit 412 as shown in FIG. 3. Specifically, the NOT circuit 411 has its input terminal connected to the node from which the level-shifted control signal S200 is outputted (i.e., the output terminal of the NOT circuit 213). The output terminal of the NOT circuit 411 and the node of the dummy circuit 301 (i.e., the output terminal of the NOT circuit 313) are connected to the input terminal of the input terminal of the NOR circuit 412. The output terminal of the NOR circuit 412 is the output terminal of the mask circuit 401 and outputs the masked signal S400. As shown in FIG. 4, the masked signal S400 has the same waveform as (but is level-shifted from) the control signal S100 outputted from the control signal generator 101, which, in other words, includes iterative pulses.

[0057] The discriminator (or first discriminator) 501 includes a re-triggerable one-shot pulse generator, and is also referred to as “re-triggerable one-shot pulse generator 501”. The pulse generator 501 uses each of a plurality of pulses in the masked signal S400 (that correspond to iterative pulses in the control signal S100, on which, however, noise may be superimposed as will be described) as a trigger and generate a pulse for each trigger.

[0058] Specifically, each of pulses generated by the pulse generator 501 has a width set not smaller than the period T of the iterative pulse signal S112 (FIG. 4) generated by the one-shot pulse generator 112 of the control signal generator 101, and for example, is set at a width not smaller than the period T and substantially the same as T. More specifically, the width is set slightly greater than the period T (e.g., (the period T)+(the width of iterative pulse)). Thus, as shown in FIG. 4, a plurality of the above-described pulses are joined in series to form a pulse in the discrimination result signal S500 outputted from the re-triggerable one-shot pulse generator 501. Since a period during which the control signal S100 includes iterative pulses corresponds to the ON command period T1on as described above, a pulse on a high level in which a plurality of pulses are joined in series, in the discrimination result signal S500, corresponds to (period T1on of) the ON command, and the remaining part on a low level corresponds to (period T1off of) the OFF command.

[0059] Consequently, the pulse generator 501 discriminates between (period T1on of) the ON command and (period T1off of) the OFF command using the iterativeness of the plurality of pulses included in the masked signal S400.

[0060] As has been described, the driving circuit 600 controls conduction/non-conduction of the switching device 1 with the control signal S600 in response to the discrimination result signal S500.

[0061] Referring now to the low-potential side driving device 11L, it includes a synchronizing circuit 901 and a low-potential side driving circuit 900 each connected between the potentials VCC and GND. Specifically, the synchronizing circuit 901 obtains the clock signal S111 outputted from the original clock signal generator 111 and the ON/OFF command signal S2 on the switching device 2 to synchronize the ON/OFF command signal S2 with the clock signal S111, thereby generating a signal S901. The driving circuit 900 controls conduction/non-conduction of the switching device 2 with a control signal S900 in response to the signal S901. The driving circuit 900 is configured in the same manner as the driving circuit 600.

[0062] The driving devices 10 and 11 can prevent a malfunction or incorrect action as will be described below even if the potential VS of the node N0 between the switching devices 1 and 2 varies with switching of the switching devices 1 and 2.

[0063] First, when the potential VS of the node N0 varies, currents for charging source-drain parasitic electrostatic capacitance of the HVNMOSs 211 and 311 flow over the current path 210 of the level shift circuit 201 a and the current path 310 of the dummy circuit 301, respectively. At this time, the current in the level shift circuit 201ais superimposed on the level-shifted control signal S200 as noise to be outputted from the output terminal of the circuit 201a.

[0064] The HVNMOS 311 of the dummy circuit 301 is always set at a non-conducting state. The dummy circuit 301 does not generate a signal in a normal operation. Thus, the signal S300 outputted from the aforementioned node of the dummy circuit 301 resulting from the above-mentioned currents is nothing but noise resulting from the variation in the potential VS. That is, the dummy circuit 301 functions as a noise detector.

[0065] With the mask circuit 401 configured as described above, the level-shifted control signal S200 is outputted as it is as the masked signal S400 when the signal S300 is on a low level, i.e., when noise does not appear. On the other hand, when the signal S300 is on a high level, i.e., when noise appears, noise is removed from a signal (i.e., the level-shifted control signal S200 on which noise is superimposed) to be outputted from the level shift circuit 201a, and the signal can thereafter be outputted as the masked signal S400. As described, the level-shifted control signal S200 from which noise has been removed can be obtained as the masked signal S400 using the signal S300 outputted from the dummy circuit 301.

[0066] As a result, a malfunction can be prevented even if the potential VS of the node N0 varies.

[0067] The level shift circuit 201aand the dummy circuit 301 are configured almost in the same manner. Thus, when the potential VS varies with the HVNMOS 211 of the level shift circuit 201abeing in a non-conducting state, the above-mentioned currents flowing over the current paths 210 and 310 are almost equal in magnitude and timing to each other. Therefore, the effect of removing noise is significant in this case.

[0068] Conversely, when the currents flowing over the current paths 210 and 310 are shifted in timing, it is difficult to completely remove noise even with the dummy circuit 301 and mask circuit 401, which may cause a malfunction to occur and continue due to a noise pulse included in the masked signal S400 having a pulse width corresponding to the timing difference. A reason why the currents are shifted in timing is that the components of the level shift circuit 201aand those of the dummy circuit 301 vary in characteristics or that the HVNMOS 211 is in a conducting state at the switching of the high-potential side switching device 1 (in this case, the HVNMOSs 211 and 311 differ from each other in parasitic electrostatic capacitance).

[0069] However, the driving device 10 can suppress/prevent a continuation of a malfunction even when the currents flowing over the current paths 210 and 310 are shifted in timing.

[0070] Specifically, the control signal S100 outputted from the control signal generator 101 includes iterative pulses and the masked signal S400 has the same waveform as the control signal S100 (if noise does not appear) (FIG. 4) as described above. The re-triggerable one-shot pulse generator 501 generates pulses in synchronization with respective pulses included in the masked signal S400. The pulse width is set, for example, slightly greater than the period T of the iterative pulse signal S112 (FIG. 4) in the control signal S100. Thus, if the masked signal S400 includes the pulse resulting from noise (noise pulse), a pulse included in the discrimination result signal S500 corresponding to the noise pulse is a one-shot pulse and appears only in a period corresponding to the pulse width. As a result, a malfunction due to the noise pulse occurs only in a period corresponding to the width of the pulses generated by the re-triggerable one-shot pulse generator 501, after the lapse of which a normal operation is returned.

[0071] That is, the pulse generator 501 uses the iterativeness of the plurality of pulses included in the masked signal S400 to discriminate between the conducting command and non-conducting command, so that, even if the plurality of pulses include a noise pulse, a period during which the noise pulse causes a malfunction can be limited, allowing return to a normal operation.

[0072] Further, setting a threshold value of the NOT circuit 313 of the dummy circuit 301 higher than that of the NOT circuit 213 of the level shift circuit 201aallows a masking process at the mask circuit 401 to be performed with more reliability even when the currents flowing over the current paths 210 and 310 are shifted in timing. This is because such setting of the threshold value allows the whole period during which the level shift circuit 201ais on a high level to be included in a period during which the signal S300 outputted from the dummy circuit 301 is on a high level.

[0073] As has been described, the driving devices 10 and 11 can suppress/prevent a malfunction resulting from variations in the potential VS with more reliability employing double or triple remedies.

[0074] <Second Preferred Embodiment>

[0075] Another specific structural example of the driving device 10 will be described using a driving device 12 and a mask circuit 402 according to a second preferred embodiment shown in FIGS. 5 and 6. The driving device 12 has basically the same structure as the driving device 11 except that the driving device 11H is replaced by a high-potential side driving device 12H. The driving device 12H has basically the same structure as the driving device 11H except that the level shifter 201, dummy circuit 301 and mask circuit 401 are replaced by a level shifter 202, a dummy circuit 302 and the mask circuit 402, respectively.

[0076] The level shifter 202 includes a level shift circuit 202aconfigured by removing the diode 214 from the level shift circuit 201aand providing with two paths leading to the mask circuit 402 from the current path 210 through two NOT circuits 213, respectively. The two NOT circuits 213 each output the level-shifted control signal S200.

[0077] The dummy circuit 302 is configured by removing the diode 314 from the dummy circuit 301.

[0078] The mask circuit 402 includes an AND circuit 413 in addition to the NOT circuit 411 and NOR circuit 412 as shown in FIG. 6. Specifically, one NOT circuit 213 of the level shift circuit 202aand the NOT circuit 313 of the dummy circuit 302 have their output terminals connected to the input terminal of the AND circuit 413, while the other NOT circuit 213 of the level shift circuit 202ahas its output terminal connected to the input terminal of the NOT circuit 411. The NOT circuit 411 and NOR circuit 412 have their output terminals connected to the input terminal of the NOR circuit 412. The NOR circuit 412 outputs the masked signal S400. In the mask circuit 402 of such configuration, the AND circuit 413 detects noise, noting that noise resulting from variations in the potential VS is transmitted in the same phase.

[0079] The level shift circuit 202amay be provided with one NOT circuit 213 such that the level-shifted control signal S200 outputted from the NOT circuit 213 is inputted to both the NOT circuit 411 and AND circuit 413.

[0080] Further, setting threshold values of the one NOT circuit 213 and the NOT circuit 313 connected to the AND circuit 413 higher than a threshold value of the other NOT circuit 213 connected to the NOT circuit 411 allows a masking process at the mask circuit 402 to be performed with more reliability.

[0081] The driving device 12 can achieve the same effects as the above-described driving devices 10 and 11.

[0082] <Third Preferred Embodiment>

[0083] A third specific structural example of the driving device 10 will be described using a driving device 13 according to a third preferred embodiment shown in FIG. 7. FIGS. 8 and 9 show a control signal generator 102 and a mask circuit 403 of the driving device 13, and FIG. 10 is a timing chart for explaining the operation of the driving device 13. The driving device 13 has basically the same structure as the driving device 11 except that the driving devices 11H and 11L are replaced by a high-potential side driving device 13H and a low-potential side driving device 12L, respectively.

[0084] The driving device 13H includes the control signal generator 102, a level shifter 203, a dummy circuit 303, the mask circuit 403 and a discriminator (or second or third discriminator) 503 as the aforementioned components 100, 200, 300, 400 and 500, respectively, and further includes the above-described driving circuit 600.

[0085] As shown in FIG. 8, the control signal generator 102 includes an iterative pulse signal generator 110, first and second selectors 114a, 114b, an ON transition pulse (or conducting transition pulse) generator 115a, an OFF transition pulse (or non-conducting transition pulse) generator 115band OR circuits 116aand 116b.

[0086] Specifically, the iterative pulse signal generator 110 includes the original clock signal generator 111 and a one-shot pulse generator 113. The one-shot pulse generator 113 is connected between the potentials VCC and GND to be supplied with power and is configured to obtain the clock signal S111 to generate and output an iterative pulse signal S113 (cf. FIG. 10; corresponding to the iterative pulse signal S112 shown in FIG. 4) including iterative pulses (iterative pulse waveform) having the period T in response to the clock signal S111.

[0087] The first selector 114aincludes an AND circuit 114a1 connected to receive the iterative pulse signal S113 and ON/OFF command signal S1. Accordingly, the iterative pulse signal S113 is selectively outputted as an output signal S114afrom the first selector 114aonly in the ON command period T1on (FIG. 10).

[0088] The ON transition pulse generator 115aincludes a one-shot pulse generator 115a1 connected to receive the ON/OFF command signal S1. The one-shot pulse generator 115a1 is configured to generate ON transition pulses in synchronization with rising of pulses in the ON/OFF command signal S1 (corresponding to transition from the OFF command to ON command) to be outputted as a signal S115a(FIG. 10). The ON transition pulses are set at the same width as the iterative pulses generated by the one-shot pulse generator 113.

[0089] The OR circuit 116ais connected to receive the output signal S114aof the first selector 114aand the output signal S115aof the ON transition pulse generator 115a. An operation result of the OR circuit 116ais outputted from the output terminal (or conduction control signal output terminal) of the OR circuit 116aas an ON control signal (or conduction control signal) S100a. The iterative pulses in the signal 114aand the ON transition pulses in the signal 115aare superimposed on each other in the ON control signal S100a(FIG. 10).

[0090] On the other hand, the second selector 114bincludes an AND circuit 114b1 and a NOT circuit 114b2. The second selector 114bis configured such that the AND circuit 114b1 receives the iterative pulse signal S113 and the ON/OFF command signal S1 with its waveform inverted by the NOT circuit 114b2. Accordingly, the iterative pulse signal S113 is selectively outputted as the output signal S114bfrom the second selector 114bonly in the OFF command period T1off (FIG. 10).

[0091] The OFF transition pulse generator 115bincludes a one-shot pulse generator 115b1 and a NOT circuit 115b2. The pulse generator 115bis configured such that the one-shot pulse generator 115b1 receives the ON/OFF command signal S1 with its waveform inverted by the NOT circuit 115b2. The one-shot pulse generator 115b1 is configured to generate OFF transition pulses in synchronization with rising of pulses of the ON/OFF command signal S1 with inverted waveform (corresponding to transition from the ON command to OFF command) to be outputted as a signal S115b. The OFF transition pulses are set at the same width as the iterative pulses generated by the one-shot pulse generator 113.

[0092] The OR circuit 116bis connected to receive the output signal S114bof the second selector 114band the output signal S115bof the OFF transition pulse generator 115b. An operation result of the OR circuit 116bis outputted from the output terminal (or non-conduction control signal output terminal) of the OR circuit 116bas an OFF control signal (or non-conduction control signal) S100b. The iterative pulses in the signal 114band the OFF transition pulses in the signal 115bare superimposed on each other in the ON control signal S100b(FIG. 10).

[0093] The control signals S100aand S100boutputted from the OR circuits 116aand 116b, respectively, generically correspond to the control signal S100 outputted from the control signal generator 100, and the output terminals of the OR circuits 116aand 116bgenerically correspond to the output terminal of the control signal generator 100.

[0094] The level shifter 203 includes two level shift circuits (or first and second level shift circuits) 203aand 203b.

[0095] The first level shift circuit 203ais basically configured to have a P-channel field-effect transistor (or second switching device) 215 added to the level shift circuit 201ashown in FIG. 2. A MOSFET (or MISFET) is used for the transistor 215 in this case. The P-channel MOSFET is also referred to as “PMOS”.

[0096] The PMOS 215 is inserted such that the source-drain path of the PMOS 215 is provided on the current path 210. Specifically, the PMOS 215 has its source connected to the node between the input terminal of the NOT circuit 213 and the one terminal of the resistor 212 and its drain connected to the node between the cathode of the diode 214 and the drain of the HVNMOS 211. In this case, the PMOS 215 is provided between the diode (or clamping device) 214 and the potential VB, i.e., between the potentials VS and VB. The PMOS 215 has its gate connected to a Q output of an RS flip-flop serving as the discriminator 502. Thus, the PMOS 215 controls the conducting/non-conducting estate of the current path 210 in response to the discrimination result signal S500 outputted from the discriminator 502. The substrate potential of the PMOS 215 is set at the potential VB.

[0097] In the first level shift circuit 203a, the HVNMOS 211 has its gate connected to the output terminal (or conduction control signal output terminal) of the OR circuit 116aof the control signal generator 102 from which the ON control signal (or conduction control signal) S100ais outputted, and a level-shifted ON control signal (or level-shifted conduction control signal) S200ais outputted from the output terminal of the NOT circuit 213.

[0098] The second level shift circuit 203bincludes an HVNMOS 221, a level shift resistor 222, a NOT circuit 223, a clamping diode 224 and a PMOS 225 having characteristics (values) almost equal to those of the components 211 to 215 of the first level shift circuit 203a, respectively, and is basically configured in the same manner as the first level shift circuit 203a. Accordingly, the second level shift circuit 203bforms a current path 220 between the potentials GND and VB.

[0099] In the second level shift circuit 203b, the HVNMOS 221 has its gate connected to the output terminal (or non-conduction control signal output terminal) of the OR circuit 116bin the control signal generator 102 from which the OFF control signal (or non-conduction control signal) S100bis outputted, and a level-shifted OFF control signal (or level-shifted non-conduction control signal) S200bis outputted from the output terminal of the NOT circuit 223. The second level shift circuit 203bfurther includes a NOT circuit 251 having its input terminal connected to the Q output of the RS flip-flop serving as the discriminator 502 and its output terminal connected to the gate of the PMOS 225. Accordingly, the PMOS 225 controls the conducting/non-conducting state of the current path 220 in response to (an inverted signal of) the discrimination result signal S500 outputted from the discriminator 502.

[0100] In the level shifter 203, the level-shifted ON control signal S200aand the level-shifted OFF control signal S200bgenerically correspond to the level-shifted control signal S200.

[0101] The dummy circuit 303 is configured to have a PMOS 315 added to the dummy circuit 301 shown in FIG. 2. The PMOS 315 has characteristics (values) almost equal to those of the PMOSs 215 and 225 of the level shift circuits 203aand 203band is provided on the current path 310 similarly to the PMOSs 215 and 225. However, the PMOS 315 has its gate connected to the potential VS. The components (e.g., HVNMOS 211, 221, 311) corresponding to one another between the dummy circuit 303 and the level shift circuits 203aand 203bhave characteristics (values) substantially equal to one another.

[0102] The mask circuit 403 is broadly divided into first and second mask circuits 403aand 403bas shown in FIG. 9. As is apparent from comparison between FIGS. 9 and 3, the mask circuits 403aand 403beach have a similar configuration as the mask circuit 401.

[0103] Specifically, the first mask circuit 403aincludes a NOT circuit 411aand a NOR circuit 412a. The NOT circuit 411ahas its input terminal connected to the node of the first level shift circuit 203a(from which the level-shifted ON control signal S200ais outputted) while the output terminal of the NOT circuit 411aand the node of the dummy circuit 303 are connected to the input terminal of the NOR circuit 412a. Accordingly, the first mask circuit 403amasks a signal outputted from the node of the first level shift circuit 203ausing a signal outputted from the dummy circuit 303 to generate a first masked signal S400a. The output terminal of the NOR circuit 412ais that of the first mask circuit 403aoutputting the first masked signal S400a.

[0104] Similarly, the second mask circuit 403bincludes a NOT circuit 411band a NOR circuit 412b. The NOT circuit 411bhas its input terminal connected to the node of the second level shift circuit 203b(from which the level-shifted OFF control signal S200bis outputted) while the output terminal of the NOT circuit 411band the node of the dummy circuit 303 are connected to the input terminal of the NOR circuit 412b. Accordingly, the second mask circuit 403bmasks a signal outputted from the node of the second level shift circuit 203busing a signal outputted from the node of the dummy circuit 303 to generate a second masked signal S400b. The output terminal of the NOR circuit 412bis that of the second mask circuit 403bfrom which the second masked signal S400bis outputted.

[0105] The masked signals S400aand S400bgenerically correspond to the masked signal S400.

[0106] The discriminator 502, including the RS flip-flop, is also referred to as “RS flip-flop 502”. The RS flip-flop 502 has its set input (S input) connected to the output terminal of the NOR circuit 412aof the mask circuit 403 and its reset input (R input) connected to the output terminal of the NOR circuit 412bof the mask circuit 403.

[0107] Thus, the RS flip-flop 502 outputs a signal of high level as the discrimination result signal S500 from its Q output in response to pulses of high level in the first masked signal S400aoutputted from the first mask circuit 400a, while outputting a signal of low level as the discrimination result signal S500 from its Q output in response to pulses of high level in the second masked signal S400boutputted from the second mask circuit 400b. In other words, a period during which the discrimination result signal S500 is on a high level and that during which the signal S500 is on a low level correspond to the ON command period T1on and the OFF command period T1off on the switching device 1, respectively.

[0108] As described, the discrimination result signal S500 is also inputted to the PMOS 215 of the first level shift circuit 203aand the NOT circuit 251 of the second level shift circuit 203b.

[0109] Referring now to the low-potential side driving device 12L, it includes a delay circuit 902 and the aforementioned driving circuit 900. The delay circuit 902, connected between the potentials GND and VCC to be supplied with power, is configured to obtain the ON/OFF command signal S2 on the low-potential side switching device 2 and delay the signal S2 to output the same as a signal S902 to the driving circuit 900. The delay circuit 902 is provided such that a delay time from the receipt of the ON/OFF command signal S1 at the high-potential side driving device 13H to the actual switching operation performed by the high-potential side switching device 1 is corrected at the driving device 12L, for example.

[0110] The driving device 13 of such configuration can achieve the same effects as the above-described driving devices 10 to 12 even when the conducting command and non-conducting command on the switching device 1 are given by separate signals, i.e., the ON control signal (conduction control signal) S100aand OFF control signal (non-conduction control signal) S100b. Setting a threshold value of the NOT circuit 313 of the dummy circuit 303 higher than that of the NOT circuit 213 of the level shift circuit 203aand that of the NOT circuit 223 of the level shift circuit 203ballows a masking process at the mask circuit 403 to be performed with more reliability.

[0111] Specifically, one of the ON control signal S100aand OFF control signal S100bincludes iterative pulses, and the RS flip-flop 502 performs discrimination using pulses included in the masked signals S400aand S400b. Thus, even when a noise pulse included in the masked signals S400aand S400bcauses a malfunction, a normal pulse (forming iterative pulses transmitted to the ON control signal S100aor OFF control signal S100b) next to the noise pulse allows return to a normal operation. At this time, the period of the malfunction is limited to a period that corresponds to the period T of the iterative pulses at most.

[0112] Since the ON/OFF command signal S1 and iterative pulse signal S112 are out of synchronization with each other in the driving devices 11 and 12, a delay time td may occur between the conducting/non-conducting command and the control signal S100 (FIG. 4). This delay time td is also reflected (transmitted) in a period from the issuance of the conducting command and non-conducting command to the actual switching operation of the high-potential side switching device 1. On the other hand, with the driving device 13, the ON control signal S100aand OFF control signal S100binclude the conducting transition pulses and non-conducting transition pulses, respectively, and the RS flip-flop 502 performs discrimination using pulses, included in the masked signals S400aand S400b, that correspond to the conducting transition pulses and non-conducting transition pulses, respectively, which allows a reduction in the delay time td.

[0113] When the delay time td depends upon rising/falling of the ON/OFF command signal S1 and rising of the iterative pulse signal S112 (or the clock signal S111) as in the driving devices 11 and 12, the ON/OFF command signal S2 on the low-potential side switching device 2 and the clock signal S111 are brought into synchronization with each other in order to ensure a period (dead time) during which the switching devices 1 and 2 are inactive. However, the driving device 13 eliminates the need to synchronize the ON/OFF command signal S2 and the clock signal S111 since the delay time td does not depend upon the timing of the ON/OFF command signal S1 and iterative pulse signal S112. Thus, the driving device 13 does not require the synchronizing circuit 901 or interconnection, provided for the driving device 11L shown in FIG. 2, connecting the synchronizing circuit 901 and original clock signal generator 111 (such interconnection is prolonged in the case where the driving devices 11H and 11L are separate integrated circuits).

[0114] Further, the level shift circuits 203aand 203binclude the PMOSs 215 and 225, respectively, allowing a reduction in power consumption of the driving device 13. The reason is as follows: upon detecting transition from the OFF command to ON command, for example, the RS flip-flop 502 maintains the Q output until transition is thereafter made from the ON command to OFF command. Thus, in the driving device 13, the switching device 1 can be switched upon detecting transition between the ON command and OFF command from the control signals S100aand S100b. Therefore, during a continuation of the ON command, the level shift circuit 203btransmitting the OFF command for detecting next transition (from the ON command to OFF command) may only be operated while the level shift circuit 203atransmitting the ON command may be suspended. Specifically, the level shift circuit 203amay be controlled such that a current does not flow over the current path 210. Such suspension can be achieved since the driving device 13 is configured such that the PMOS 215 controls the conducting state/non-conducting state of the current path 210 in response to the discrimination result signal S500. Such suspension of the level shift circuit 203aallows a reduction in power consumption. Needless to say, the same applies to a period during which the OFF command continues.

[0115] Considering the case where the potential VS varies when the Q output of the RS flip-flop 502 is on a high level, a current for charging parasitic electrostatic capacitance of the HVNMOS 211 flows over the current path 210 through the diode 214 and noise resulting from the current does not appear in the signal S200asince the PMOS 215 of the level shift circuit 203ais in a non-conducting state at this time. However, currents flow over the current paths 220 and 310 through the resistors 222 and 312, respectively, with the PMOSs 225 and 315 being in a conducting state, so that noise resulting from the currents appears in the signals S200band S300, which can be suppressed/removed by the mask circuit 403 and RS flip-flop 502. Similarly, in the case where the potential VS varies when the Q output of the RS flip-flop 502 is on a low level, noise can be suppressed/removed using the signals S200aand S300 outputted from the level shift circuit 203aand dummy circuit 303, respectively. In short, the effect of suppressing/removing noise can be obtained even if one of the level shift circuits 203aand 203bis suspended.

[0116] Further, the PMOSs 215 and 225 are each provided between the clamping diode (clamping device) and the potential VB (fourth potential), so that currents flowing through the PMOSs 215 and 225 are defined by the difference between the potentials VB and VS. This potential difference is smaller than that between the potentials VB and GND, eliminating the need to use a high voltage device (power device) for the PMOSs 215 and 225, which allows a cost reduction in this regard.

[0117] With the cost reduction described above, the driving device 13 may be modified into a driving device 13B as shown in FIG. 11. The driving device 13B will be described as a fourth specific structural example of the driving device 10. The driving device 13B shown in FIG. 11 includes a high-potential side driving device 13HB in place of the driving device 13H in the driving device 13 shown in FIG. 7. The driving device 13HB is configured to have a power supply circuit including a capacitor 5 and a bootstrap diode 6 added to the driving device 13H shown in FIG. 7. Specifically, the capacitor 5 is connected between the potentials VB and VS, and the diode 6 has its cathode and anode connected to the potentials VB and VCC, respectively. Such configuration allows the driving device 13B to operate with the single power supply 4.

[0118] <Fourth Preferred Embodiment>

[0119] A fifth specific structural example of the driving device 10 will be described using a driving device 14 according to a fourth preferred embodiment shown in FIG. 12. The driving device 14 has basically the same structure as the driving device 13 shown in FIG. 7 except that the driving device 13H is replaced by a high-potential side driving device 14H. The driving device 14H has basically the same structure as the driving device 13H except that the level shifter 203 and dummy circuit 303 are replaced by a level shifter 204 and a dummy circuit 304, respectively.

[0120] The level shifter 204 is broadly divided into first and second level shift circuits 204aand 204bsimilarly to the first and second level shift circuits 203aand 203bshown in FIG. 7.

[0121] The first and second level shift circuits 204aand 204bare configured by replacing the PMOSs 215 and 225 in the level shift circuits 203aand 203bshown in FIG. 7 with analog switches (or second switching devices) 216 and 226, respectively, and removing the diodes 214 and 224. The level shifter 204 includes a NOT circuit 252 in place of the NOT circuit 251 of the level shifter 203.

[0122] The analog switches 216 and 226 each have P- and N-channel field-effect transistors connected in parallel to each other with the source and drain connected to the drain and source, respectively, between the P- and N-channel transistors. In this case, MOSFETs are used for the P- and N-channel field-effect transistors, and the analog switches 216 and 226 are so-called C-MOS analog switches having characteristics (values) substantially equal to each other.

[0123] The analog switches 216 and 226 have their main paths provided on the current paths 210 and 220, respectively, in the same position as the PMOSs 215 and 225 shown in FIG. 7. The P-channel MOSFET of the analog switch 216 and the N-channel MOSFET of the analog switch 226 have their gates connected to the Q output of the RS flip-flop 502, while the N-channel MOSFET of the analog switch 216 and the P-channel MOSFET of the analog switch 226 have their gates connected to the output terminal of the NOT circuit 252. The NOT circuit 252 has its input terminal connected to the Q output of the RS flip-flop 502. The substrate potentials of the respective N-channel MOSFETs of the analog switches 216 and 226 are both connected to the potential (or third potential) VS, while those of the respective P-channel MOSFETs of the analog switches 216 and 226 are both connected to the potential VB.

[0124] The dummy circuit 304 is configured by replacing the PMOS 315 with an analog switch 316 and removing the diode 314 from the dummy circuit 303 shown in FIG. 7. The analog switch 316 is configured in the same manner as the analog switches 216 and 226 having characteristics (values) substantially equal to those of the analog switches 216 and 226. The analog switch 316 has its main path provided on the current path 310 in the same position as the PMOS 315 shown in FIG. 7. As described, the dummy circuit 304 in the driving device 14H is basically configured in the same manner as the level shift circuits 204aand 204bexcept that, in the analog switch 316, the P-channel MOSFET has its gate connected to the potential VS and the N-channel MOSFET has its gate connected to the potential VB. The substrate potentials of the N- and P-channel MOSFETs of the analog switch 316 are connected to the potentials VS and VB, respectively.

[0125] The driving device 14 can achieve the same effects as the driving device 13. Specifically, the driving device 14 eliminates the need to provide another clamping diode (clamping device) since the diodes provided between the substrate and the source of the N-channel MOSFETs of the analog switches 216, 226 and 316, respectively, function as clamping diodes. This allows the number of components to be reduced, which can improve integration properties as compared to the driving device 13.

[0126] <Variant>

[0127] The driving devices 10 to 14 may be configured to process signals obtained by inverting the waveforms of the signals described above and shown in the timing charts. Further, the diodes 214, 224 and 314 may be replaced with clamping diodes configured by transistors.

[0128] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.