Fin memory cell and method of fabrication

[0002] The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming double gated field effect transistors.

[0003] The need to remain cost and performance competitive in the production of semiconductor devices has driven the increase in device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.

[0004] The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) technologies. DRAMs are the most commonly used type of memory and are thus found in a wide variety of integrated circuit designs. DRAM is often embedded into application specific integrated circuits (ASICs), such as processors and logic devices.

[0005] Each DRAM cell contains an access transistor and a capacitor used to store the memory data. The two most common types of capacitors used to store the memory are deep trench and planar capacitors. Deep trench capacitors generally have the advantage of increased memory density, but have the disadvantage of increased process complexity and cost. For this reason, deep trench capacitors are generally only used where the large number of memory cells can justify the increased process cost. In contrast, planar capacitors can be manufactured using much simpler manufacturing techniques, and generally do not add excessive processing costs to the device. However, planar capacitors do not provide the cell density that deep trench capacitors do, and thus are limited to applications in which the number of memory cells needed is relatively low.

[0006] Thus, there is a need for improved memory structure and method of fabrication that provides for increased DRAM memory cell density without excessively increasing fabrication complexity and cost.

[0007] Accordingly, the present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.

[0008] The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

[0009] The preferred exemplary embodiment of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and

[0010] FIG. 1 is a flow diagram illustrating a first fabrication method;

[0011] FIGS. 2, 3, 5, 6, 9, 12 and 14 are cross-sectional side views of an exemplary memory device during fabrication; and

[0012] FIGS. 4, 7, 8, 10, 11 and 13 are top views of an exemplary memory device during fabrication.

[0013] Accordingly, the present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention uses a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.

[0014] In fin FET technologies, the body of the transistor is formed with a vertical “fin” shape. The gates of the transistor are then formed on one or more sides of the fin. The preferred method for forming this double gated transistors allows the gate length of the device to have minimum feature size, while allowing the thickness of the body to be much smaller than the gate length. Generally, it is desirable to make the fin narrow enough insure a fully depleted channel during operation of the transistor. This improves control of the threshold voltage of the resulting device. The preferred method for forming the fin FET accomplishes this by using an image enhancement technique, sidewall image transfer, to define the thickness of the transistor body, allowing it to be reliably formed at sub minimum feature size.

[0015] The memory cell of the current invention also forms the storage capacitor using the fin shaped body. Specifically, a portion of the fin body will be highly doped and made to comprise the storage node of the memory cell capacitor. An insulator layer is then formed on the fin sidewalls, and a common counter electrode is formed over the fins to complete the fin capacitor. These fin capacitors have the advantage of providing a high device density without requiring excessive process complexity.

[0016] The memory cell of the current invention has density advantages over typical planar memory cells for several reasons. First, the use of a fin FET for the transfer transistor has density advantages over typical planar transistors. Second, the fin structure of the capacitor allows for greater capacitance in a limited space than can be accomplished using typical planar capacitor technology. This is because both sides of the fin comprise capacitor storage area. Fins are typically formed one lithographic unit high and thus the fin capacitor can have twice the capacitor storage area of the typical planar capacitor. Further advantage yet is attainable through the use of taller fins to obtain greater storage capacitance without any penalty to the physical cell area. Taken together, a fin memory cell can thus be formed in less than ten lithographic squares, depending upon the area allocated to the fin capacitor. For example, if the capacitor is limited in width to the minimum feature size, the memory cell can be formed in nine lithographic squares.

[0017] In contrast, the typical planar DRAM cell must be at least 25% larger for equivalent lithographic feature size. This is because silicon mesas used to form the FET and the storage node must be at least on lithographic square wide, and hence the entire cell must grow to accommodate this size. Even with the increase in layout area, the typical planar DRAM cell will have half the capacitance of the fin memory cell because of the added capacitance of the fin capacitor discussed above. In contrast, in typical planar cells the cell area must be increased to increase the storage area.

[0018] Thus, the fin memory cell can provide high density memory arrays for storage used in embedded applications at low process cost.

[0019] Turning now to FIG. 1, a method 100 for forming a fin memory cell in accordance with the preferred embodiment is illustrated. Method 100 forms a fin memory cell in a way that provides increased device density, while maintaining fabrication simplicity and reducing costs.

[0020] The first step 102 of method 100 is to provide an appropriate wafer. In the preferred embodiment, the wafer used comprises a silicon on insulator (SOI) wafer. As such, the wafer is comprised of a buried oxide layer beneath an SOI layer. As will be come clear, the SOI layer is used to form the body of the double gated transistor. As such, it is generally preferable to use a SOI layer that has a p-type doping density in the range of 5×10¹⁵cm⁻³to 8×10¹⁸cm⁻³to provide proper centering and control of the threshold voltage of the transistors. However, in another embodiment to be described later, the doping of the SOI layer is done later with an appropriate implant.

[0021] However, non-SOI wafers can be used. When a non-SOI wafer is used, the processing remains otherwise identical to those of the SOI wafer case, except as noted.

[0022] The next step 104 of method 100 is to form a fin pattern using sidewall image transfer. It is generally desirable to have the fin thickness narrower than the gate length. Typically, the fin thickness should be less than one quarter of the gate length to give good threshold voltage control. Also, it is generally desirable that the fin thickness should be greater than 2.5 nm to avoid degraded mobility due to quantum confinement issues. As the gate length is generally made to minimum feature size, sidewall image transfer is used to achieve the subminimum feature size of the fin.

[0023] Sidewall image transfer typically involves the formation of a mandrel layer and at least one etch stop layer. The mandrel layer is then patterned, and sidewall spacers are formed on the sidewalls of the patterned mandrel layer. These sidewall spacers will be used to define the fins, completing the sidewall image transfer. Sidewall image transfer provides many advantages, the most notable being that it allows features to be accurately fabricated below the minimum lithographic feature size. Specifically, because sidewall image transfer is used to define the fins, the fins of the transistor can be accurately formed with a narrower width than could be formed using traditional lithography. The fin width is determined by the spacer width. Spacer width can be etched much narrower than the fin can be printed and formed using conventional lithography.

[0024] The mandrel layer is thus first patterned to define shapes such that the exterior perimeter of the shapes will provide the sidewalls used to define the spacers. The mandrel layer preferably comprises a layer of oxide or other suitable material. Generally it will be desirable for the mandrel layer to have a thickness of between 10 nm and 100 nm, however, such a thickness may change depending on the desired body thickness. The sidewall spacer can be formed using a deposition of silicon nitride or other suitable material, followed by a suitable directional etch.

[0025] Turning now to FIG. 2, a cross sectional view of a wafer portion 200 is illustrated after the formation of an etch stop layers and a mandrel layer. The wafer portion 200 comprises an SOI wafer, and as such includes an. SOI layer 202 and a buried insulator layer 204. On top of the SOI layer is formed an etch stop layer. On top of etch stop layer 206 is formed a mandrel layer 212.

[0026] Turning now to FIG. 3, a cross sectional view of a wafer portion 200 is illustrated after the mandrel layer has been patterned. Again, the patterned mandrel layer provides the mandrel shapes 402 that will be used in the sidewall image transfer.

[0027] Turning now to FIG. 4, a top view of the wafer portion 200 is illustrated, including a cross sectional line A—A that defines the FIG. 3 and the other cross sectional views. Those skilled in the art will recognize that FIG. 4, and the other top views illustrated herein and not drawn to the same scale as FIG. 3 and the other cross sectional views. FIG. 4 illustrates the mandrel shapes 402 formed on the wafer portion 200 that will be used to the define the fins that make up the fin memory cells. As will become clear, the mandrel shapes 402 will be used to define the fins that will be used to form eight DRAM fin memory cells.

[0028] Turning now to FIG. 5, a cross sectional view of wafer portion 200 is illustrated after the formation of sidewall spacers 403 on the sidewalls of mandrel shapes 402. Turning now to FIG. 6, a cross sectional view of wafer portion 200 is illustrated after the mandrel shapes 402 and etch stop layer 206 have been removed, leaving only a loop of sidewall spacer 403 around the old perimeter of the mandrel shapes. Because this process has naturally formed sidewall spacers on all edges of the mandrel shapes, the sidewall spacers will generally comprise “loops” of material. As will be described next, these loops will be trimmed to provide for discrete fin structures.

[0029] Returning to FIG. 1, the next step 106 is to trim the fin pattern. The fin pattern is trimmed to turn the loops into discrete shapes. Specifically, the ends of each fin pattern loop are removed, making two fin patterns from each loop. This can be done using any suitable patterning technique, such as depositing and patterning a suitable photoresist to expose only the ends of the loops, and then etching away the exposed ends. The remaining photoresist is then stripped, leaving the discrete fin patterns.

[0030] Turning now to FIG. 7, a top view of wafer portion 200 is illustrated with the fin patterns 400 covered by a suitable photoresist. The portion of the fin pattern 400 covered by the photoresist is shown in dashed lines. Openings 404 have been made in the photoresist exposing the ends of sidewall spacers 403. This allows the ends 401 of the fin pattern 400 to be removed using a suitable etch. Turning now to FIG. 8, a top view of the wafer portion 200 is illustrated after the ends 401 of the fin patterns 400 have been trimmed and the photoresist removed. This process turns each loop of the fin pattern into a two discrete fin patterns 403 from each fin pattern 400 of FIG. 7. As will become clear, two DRAM memory cells will be formed with each discrete fin pattern 403.

[0031] Returning to FIG. 1, the next step 108 is to etch the SOI layer to form the fins. This can be done using any suitable etch that is selective to the fin pattern. The SOI layer is etched selective to the fin pattern, forming a “fin” structure for each pattern that will comprise the body of the fin transistors and the fin capacitors in the memory cell. This etch transfers the trimmed sidewall spacer image into the SOI layer, and thus completes the sidewall image transfer. This is preferably done by using a reactive ion etch that etches the SOI layer selective to the sidewall spacers and stops on the buried insulator layer. In the case where bulk wafers are used, etch stop is performed by other means; such as forming a layer. Alternatively, a timed etch to desired depth could be used.

[0032] Turning now to FIG. 9, a cross sectional view of wafer portion 200 is illustrated after the fins and have been formed. Specifically, a fin 406 is formed from the SOI layer under each of the sidewall spacers 403 that made up the fin pattern. In the case where bulk wafers are used, etch stop is performed by other means, such as form layer or a timed etch to desired depth.

[0033] Returning to FIG. 1, the next step 110 is to form sacrificial oxide on the sidewalls of the fin. Sacrificial oxide is used to clean the exposed sides of the fins and protect the fins during ion implantation. Typically, the sacrificial oxide would be provided by growing a thin layer of thermal oxide.

[0034] The next step 112 is to dope the capacitor fins. It is generally desirable to have the fins that make up the storage capacitor of the DRAM cell degenerately doped to improve capacitance. However, the regions of the fin of the transfer transistor should generally not be doped in this way. Thus, the capacitor portions of the fins are selectively exposed using a suitable lithographic process, and those portions of the fins are subjected to a suitable doping implant.

[0035] In some cases it will be desirable to perform additional processing on the exposed capacitor portions 412 (see FIG. 10) of the fins. For example, additional or different types of dielectric, such as high k dielectric 415 (see FIG. 14, can be formed only on the capacitor portions 412 of the fins at this time. Other processing of the exposed capacitor portions 412 of the fins could include adding additional conductive material to improve the performance of the capacitor or to give improved process capability with the capacitor dielectric 415.

[0036] Turning now to FIG. 10, a top view of wafer portion 200 is showing how the fins 406 are selectively exposed during a dopant implant process. This degenerately dopes the capacitor portions 412 of the fins 406, while leaving other portions 413 of the fins 406 undoped. These highly doped portions of the fins 406 will be used to form the storage nodes of the memory cell capacitors. Again, other processing, such as the formation of special capacitor dielectrics can be performed at this time.

[0037] Returning now to FIG. 1 the next step 114 is to perform additional fin implants and remove the sacrificial oxide. After the blocking layer from step 112 is removed, additional implants with the appropriate species (depending on whether N-type or p-type transistors are being formed) are made into the fin body. These implants can be performed to properly dope the body and to set the threshold voltage of the transistor. These implants would preferably comprise an angled implant into the exposed sidewall of the SOI layer. The removal of the sacrificial oxide completes the cleaning process and prepares the sidewalls of the fins for the formation of the gate insulator layers.

[0038] The next step 116 is to form a gate insulator layer 414 (see FIG. 12) on the sidewalls of the fins 406. This can be provided by forming gate oxide using thermal oxidation, typically at 750-800° C., or any other suitable process.

[0039] The next step 118 is to form and pattern the gate conductor material. In DRAM cells, the gate conductor material, in addition to forming the gates of the transfer transistors, forms the counter electrode of the capacitors and the word lines used to access the memory cells. A suitable gate conductor material is doped polysilicon. The gate conductor material can be deposited and then doped, or doped in situ. Turning to FIGS. 11, 12, and 14, the wafer portion 200 is illustrated with gate conductor material that has been deposited and patterned. FIG. 11 illustrates a top view of wafer portion 200, FIG. 12 illustrates a cross sectional view taken along line B—B of FIG. 11, FIG. 14 illustrates a cross sectional view taken along line C—C of FIG. 11. In FIGS. 11, and 12, and 14, the gate conductor material has been patterned to form gates 408 and counter electrodes 410. The gates 408 also make up wordlines used to access the memory cell. Each fin (or fin body) 406 in FIG. 11 comprises portions 421-427 as shown. It should be noted that a transfer fin FET is formed at each location in which the gate 408 crosses over a fin 406 at fin portion 423 and 425. Thus, FIG. 11 illustrates the formation of eight separate transfer FETs on wafer portion 200. Additionally, a fin storage capacitor is formed at each location in which a counter electrode 410 crosses over a fin 406 at fin portion 421 and 427. Thus, FIG. 11 illustrates the formation of eight separate fin storage capacitors in wafer portion 200. Note that portions 421 and 427 of the fin 406 embody the capacitor portion 412 shown in FIG. 10. FIG. 12 depicts four transfer FETs 416 on wafer portion 200, with each transfer FET 416 having the gate 408 envelop the spacer 403, the portion 425 of fin 406, and the insulator layer 414. FIG. 14 depicts four fin storage capacitors 417 on wafer portion 200, with each storage capacitor 417 having the counter electrode 410 envelop the spacer 403, the portion 427 of fin 406, and the dielectric layer 415. Note that FIGS. 12 and 14 show an enlarged view of the fins such that the fin thicknesses of fin portions 425 and 427 are shown on a different geometric scale than are the corresponding fin thicknesses in FIG. 11.

[0040] Returning to FIG. 1, the next step 120 is to perform a sidewall reoxidation and then to form source/drain implants. The sidewall reoxidation again serves to clean the sides of the fin that may have been damaged during the patterning of the gate structure. The source/drain implants are preferably done by performing an angled implant into the sidewall of the fin to form the source and drain regions. The angled implants preferably comprise arsenic for n-type FETs or boron difluoride for p-type FETs, tilted between 45 degrees and 75 degrees from a ray normal to the plane of the wafer. The doses and energies of the these implants preferably range from between 2×10¹⁴to 1×10¹⁵cm⁻²at 0.5 to 5 keV. In FIG. 11, the source/drain may be formed with source formation in portion 424 of fin body 406 adjacent to gate electrode 408 and drain formation in portions 422 and 426 of fin body 406 adjacent to gate electrode 408. Alternatively the source/drain may be formed with drain formation in portion 424 of fin body 406 adjacent to gate electrode 408 and source formation in portions 422 and 426 of fin body 406 adjacent to gate electrode 408.

[0041] Returning now to FIG. 1, the next step 122 is to form contacts and complete the memory cells. The contacts formed would typically include bit line contacts and wordline contacts. Additionally, it would also include the formation of contacts to the counter electrodes of the capacitor, allowing the counter electrode to be tied to a potential such as ground or VDD. All of these contacts can be formed using any suitable technique, such as a damascene process where an insulator is deposited, patterned to open vias, and then the vias are filled with a suitable conductive material.

[0042] Generally, a bit line contact would be formed across each fin. Turning now to FIG. 13, the wafer portion 200 is illustrated after the bit line contact 411 has been formed within portion 424 across each fin 406.

[0043] With the contacts formed, the devices can be completed using any suitable back end of line processing and packaging as desired.

[0044] Thus, the present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.

[0045] While the invention has been particularly shown and described with reference to an exemplary embodiment using a fin type double gated field effect transistor, those skilled in the art will recognize that the preferred embodiment can be applied to other types of double gated transistors, and that changes in implementation details may be made therein without departing from the spirit and scope of the invention. It will also be understood by those skilled in the art that the invention is applicable to different isolation technologies (e.g., LOCOS, recessed oxide (ROX), etc.), well and substrate technologies, dopant types, energies and species. It will also be understood that the spirit of the invention is applicable to other semiconductor technologies (e.g., BiCMOS, bipolar, silicon on insulator (SOI), silicon germanium (SiGe).