Power efficient capacitive load driving device

[0002] This application claims priority of U.S. Provisional Patent Application No. 60/237,247 filed Oct. 2, 2000 entitled PARAMETRIC ARRAY AMPLIFIER METHODS.

[0003] N/A

[0004] The present invention relates generally to devices and methods for driving capacitive loads, and more specifically to a power efficient capacitive load driving device that can be used to drive one or more acoustic transducers of a parametric audio system.

[0005] Parametric audio systems are known that employ one or more acoustic transducers to project an ultrasonic carrier signal modulated with an audio signal through the air for subsequent regeneration of the audio signal. U.S. patent application Ser. No. 09/758,606 filed Jan. 11, 2001 entitled PARAMETRIC AUDIO SYSTEM discloses a parametric audio system that includes a modulator configured to modulate an ultrasonic carrier signal with an audio signal, a driver amplifier configured to amplify the modulated ultrasonic signal, and one or more acoustic transducers configured to receive the amplified ultrasonic signal and project it through the air along a selected path. Because of the non-linear propagation characteristics of the air, the modulated ultrasonic carrier signal is demodulated as it passes through the air, thereby regenerating the audio signal along the selected path of projection.

[0006] Each acoustic transducer included in the above-referenced parametric audio system is a wide-bandwidth capacitive transducer such as a membrane-type electrostatic transducer. Further, the driver amplifier of the parametric audio system includes one or more inductors that can be coupled to the capacitive load of the acoustic transducer, thereby effectively forming a resonant circuit to facilitate the transfer of energy between the driver amplifier and the acoustic transducer.

[0007] One drawback of the above-referenced parametric audio system is that the transfer of energy between the driver amplifier and the acoustic transducer can be inefficient and can cause high system power requirements. For example, because the load provided by the acoustic transducer is reactive, a significant amount of the energy delivered to the acoustic transducer by the driver amplifier is reflected back to the driver amplifier, which typically recovers at least a portion of the reflected energy via the above-mentioned inductor and dissipates the remaining energy as heat. Such energy dissipation can increase both the power and cooling requirements of the system.

[0008] Another drawback of the above-referenced parametric audio system is that, in some configurations, the driver amplifier may deliver energy to the acoustic transducer with some distortion and/or reduced bandwidth. To address this problem, the inductor of the driver amplifier can be connected to the capacitive load of the acoustic transducer via a damping resistor to dampen the resonance between the inductor and the capacitive load. However, as energy is transferred between the driver amplifier and the acoustic transducer through the damping resistor, at least some of this energy is typically absorbed by the damping resistor, which dissipates the absorbed energy as heat to further degrade the power efficiency of the system.

[0009] It would therefore be desirable to have a more power efficient capacitive load driving device. Such a device would be configurable to drive one or more acoustic transducers of a parametric audio system. It would also be desirable to have a capacitive load driving device that can be used to drive an acoustic transducer of a parametric audio system with low distortion and to assure wideband output capability.

[0010] In accordance with the present invention, a device and method for driving a capacitive load is provided that has a more power efficient design. The power efficient capacitive load driving device can be used to drive one or more acoustic transducers of a parametric audio system with low distortion and increased bandwidth. Such benefits are achieved by coupling the capacitive load driving device to a capacitive load, and driving the capacitive load with at least one controlled switched drive signal.

[0011] In one embodiment, the capacitive load driving device includes a current source, a plurality of switches interconnected in an “H-bridge” configuration coupled to an output of the current source, and a controller. The current source comprises a DC current source including a voltage source having a negative terminal connected to ground potential and a positive terminal, an optional charge capacitor coupled between the positive terminal of the voltage source and the ground potential, and a relatively large-valued inductor having first and second terminals. The relatively large inductor value is selected to achieve a desired low resonant frequency value with the capacitive load. The DC current source further includes a first switch connected between the positive terminal of the voltage source and the first terminal of the inductor and configured to allow current to flow from the voltage source through the first switch to the inductor, and a diode connected between the first terminal of the inductor and the ground potential and configured to allow current to flow from the ground potential through the diode to the inductor. The second terminal of the inductor comprises the DC current source output, which provides the drive energy to the capacitive load.

[0012] The plurality of switches interconnected in the “H-bridge” configuration includes a first pair of series-connected switches and a second pair of series-connected switches. Each of the first and second pairs of series-connected switches is connected between the output of the DC current source and the ground potential. Further, the capacitive load is coupled between the node connection of the first pair of series-connected switches and the corresponding node connection of the second pair of series-connected switches. The first switch, which is connected between the voltage source and the inductor, and the plurality of switches interconnected in the H-bridge configuration, include respective control terminals.

[0013] The controller is configured to (1) receive a first input signal representative of a predetermined input waveform, a second input signal representative of a measured voltage level across the capacitive load, and a third input signal representative of a measured current level through the inductor, and (2) control the operation of the DC current source and the plurality of interconnected switches to generate an output voltage waveform across the capacitive load that corresponds to the predetermined input waveform. In a preferred embodiment, the controller employs a mathematically optimal control algorithm to control the operation of the DC current source and the plurality of interconnected switches. Such control is carried out by generating suitable control signals and applying the control signals to the respective control terminals of the switches.

[0014] The following control activities are presented for purposes of illustration. The controller may perform these control activities at fixed or variable time intervals. In the event it is determined that (1) the level of the predetermined input waveform is increasing and (2) the capacitive load voltage level is less than the level of the predetermined input voltage, the controller controls the DC current source and the plurality of interconnected switches to provide a first controlled switched drive signal to the capacitive load that causes the capacitive load to charge positively. In the event it is determined that (1) the level of the predetermined input waveform is increasing and (2) the capacitive load voltage level is greater than or equal to the level of the predetermined input voltage, the controller controls the DC current source and the plurality of interconnected switches to hold the charge on the capacitive load.

[0015] In the event it is determined that (1) the level of the predetermined input waveform is decreasing and (2) the capacitive load voltage level is greater than the level of the predetermined input voltage, the controller controls the DC current source and the plurality of interconnected switches to provide a second controlled switched drive signal to the capacitive load that causes the capacitive load to discharge or charge negatively. In the event it is determined that (1) the level of the predetermined input waveform is decreasing and (2) the capacitive load voltage level is less than or equal to the level of the predetermined input voltage, the controller controls the DC current source and the plurality of interconnected switches to hold the charge on the capacitive load. In this way, the controller controls the operation of the DC current source and the plurality of interconnected switches to generate the output voltage waveform across the capacitive load corresponding to the predetermined input waveform.

[0016] By driving a capacitive load with at least one controlled switched drive signal, the presently disclosed capacitive load driving device delivers (recovers) energy to (from) the capacitive load in a more efficient manner, thereby generating a desired output voltage waveform across the capacitive load with increased power efficiency. Further, because the presently disclosed device includes reactive elements (e.g., the current source inductor) that store energy rather than merely dissipate energy as heat, system power and cooling requirements are reduced.

[0017] Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.

[0018] The invention will be more fully understood with reference to the following Detailed Description of the Invention in conjunction with the drawings of which:

[0019] FIG. 1 is a schematic diagram depicting a capacitive load driving device according to the present invention;

[0020] FIG. 2 is a flow diagram depicting an exemplary method of operating the capacitive load driving device of FIG. 1 according to the present invention;

[0021] FIG. 3 is a diagram depicting an exemplary input waveform applied to the capacitive load driving device of FIG. 1 and an output voltage waveform corresponding to the input waveform generated across a capacitive load by the capacitive load driving device; and

[0022] FIG. 4 is a schematic diagram depicting an alternative embodiment of the capacitive load driving device of FIG. 1 including multiple current sources.

[0023] U.S. Provisional Patent Application No. 60/237,247 filed Oct. 2, 2000 is incorporated herein by reference.

[0024] A device and method for driving a capacitive load is provided that has a more power efficient design. Improved power efficiency is achieved by configuring the capacitive load driving device to drive a capacitive load with at least one controlled switched drive signal, which allows more efficient delivery (recovery) of energy to (from) the load. Further, because the capacitive load driving device employs reactive elements that store rather than merely dissipate energy, power requirements are reduced. The presently disclosed device can be used to drive the capacitive load of, e.g., one or more acoustic transducers of a parametric audio system with minimal distortion and essentially flat frequency response.

[0025] FIG. 1 depicts an illustrative embodiment of a capacitive load driving device 100, in accordance with the present invention. In the illustrated embodiment, the capacitive load driving device 100 includes a current source 101 that can be coupled to a capacitive load 122 via a plurality of interconnected switches 110, 112, 114, and 116. The device 100 further includes a controller 102 configured to control the operation of the current source 101 and the plurality of interconnected switches 110, 112, 114, and 116 to provide at least one controlled switched drive signal to the capacitive load 122.

[0026] Specifically, the current source 101 comprises a DC current source including a voltage source 104, an optional charge capacitor 108, a switch 106, a diode 118, and a relatively large-valued inductor 120. The voltage source 104 has a positive terminal and a negative terminal, which is coupled to ground potential. One side of the switch 106 is connected to the positive terminal of the voltage source 104 at a node 126, and the other side of the switch is connected to a first terminal of the inductor 120 at a node 128. The switch 106 is configured to allow current to flow in one direction from the node 126 to the node 128. The charge capacitor 108 is coupled between the node 126 and the ground potential. Further, the diode 118 is coupled between the node 128 and the ground potential to allow current to flow in one direction from the ground potential to the node 128. A second terminal of the inductor 120, which constitutes the output of the DC current source, is coupled to the plurality of interconnected switches 110, 112, 114, and 116 at a node 130.

[0027] It is noted that the current source 101 may alternatively comprise an AC or time-varying current source with appropriate changes to the control algorithm. Further, the value of the inductor 120 included in the current source 101 may be increased to enhance the stability and consistency of the output current. Moreover, the inductor 120 may comprise a relatively large transformer winding instead of a large-valued inductor.

[0028] The plurality of switches 110, 112, 114, and 116 are interconnected in an “H-bridge” configuration. The switches 110 and 112 are connected in series and coupled between the current source output 130 and the ground potential. Similarly, the switches 114 and 116 are connected in series and coupled between the current source output 130 and the ground potential. The capacitive load 122 is coupled between the node connection 132 of the switches 110 and 112 and the corresponding node connection 134 of the switches 114 and 116. The switches 110 and 116 are configured to allow current to flow from the current source output 130 through the capacitive load 122 to the ground potential as the load 122 charges positively. Further, the switches 112 and 114 are configured to allow current to flow from the ground potential through the capacitive load 122 to the current source output 130 as the load 122 discharges or charges negatively.

[0029] The controller 102 is configured to receive an input voltage V_inrepresenting a predetermined input voltage waveform, a measured voltage level V_Cmrepresenting the voltage level across the capacitive load, a measured current level I_Lmrepresenting the current level through the inductor 120, and an optional clock signal CLK having a predetermined clock frequency. The controller 102 is configured to control the operation of the DC current source 101 and the plurality of interconnected switches 110, 112, 114, and 116 to generate an output voltage waveform across the capacitive load 122 that corresponds to the predetermined input voltage waveform. It should be understood that the predetermined input waveform may take the form of any signal representative of the output voltage waveform to be generated, e.g., voltage, current, or digitally-coded instructions.

[0030] Specifically, the controller 102 controls the operation of the switches 110, 112, 116, 114, and 106 by generating digital control signals T₁, T₂, T₃, T₄, and T₅based on at least the input voltage waveform V_in, and the measured voltage level V_Cm, and applying the control signals T₁T₂, T₃, T₄, and T₅to control terminals of the switches 110, 112, 116, 114, and 106, respectively. The controller 102 may also be configured to regulate the voltage source 104 via at least one line 124 For example, each of the switches 106, 110, 112, 114, and 116 may comprise a power transistor switch such as a power MOSFET switch or any other suitable device. Further, the controller 102 may comprise a suitable microprocessor or Digital Signal Processor (DSP), at least one analog-to-digital converter for converting the input voltage V_in, the measured voltage level V_Cm, and the measured current level I_Lmto digital form for use by the microprocessor or DSP, and at least one digital-to-analog converter for converting digital signals generated by the microprocessor or DSP to analog form for use in regulating the voltage source 104.

[0031] In the illustrated embodiment, the capacitive load 122 comprises one or more acoustic transducers of a parametric audio system (not shown) such as that described in U.S. patent application Ser. No. 09/758,606 filed Jan. 11, 2001, which is incorporated herein by reference. For example, the capacitive load 122 may comprise a wide-bandwidth capacitive transducer, e.g., a membrane-type electrostatic transducer, or a piezoelectric or other suitable transducer. Further, the input voltage V_inmay be representative of an ultrasonic carrier signal modulated with an audio signal.

[0032] Accordingly, the controller 102 may be configured to control the DC current source 101 and the plurality of interconnected switches 110, 112, 114, and 116 to generate an output voltage waveform across the capacitive load of one or more acoustic transducers that corresponds to the modulated ultrasonic carrier signal. The acoustic transducer may then project the modulated ultrasonic carrier signal through the air to demodulate the carrier signal and subsequently regenerate the audio signal. It should be understood, however, that the capacitive load driving device 100 may be configured to provide controlled switched drive signals suitable for driving electrostatic loudspeakers, piezoelectric transducers (e.g., for audio, sonar, or general actuation applications) or any other capacitive load.

[0033] Specifically, the capacitive load driving device 100 generates a desired output voltage waveform across the capacitive load 122 by employing the DC current source 101 and the plurality of interconnected switches 110, 112, 114, and 116 to deliver energy to the capacitive load 122, recover energy from the capacitive load 122, or hold energy in the capacitive load 122. For example, the capacitive load driving device 100 may deliver energy to a positively charged capacitive load 122 by charging the inductor 120 to a predetermined current level, and actuating the switches 110 and 116 (i.e., the switches are “closed”) while deactivating the switches 112 and 114 (i.e., the switches are “open”). As a result, the capacitive load 122 is oriented such that a positive terminal of the load 122 is effectively connected to the current source output 130 and a negative terminal of the load 122 is effectively connected to the ground potential. The capacitive load driving device 100 then delivers energy to the capacitive load 122 by allowing the inductor current I_Lto charge the load 122 to a positive potential.

[0034] Further, the capacitive load driving device 100 may recover energy from the capacitive load 122 by actuating the switches 112 and 114 while deactivating the switches 110 and 116. As a result, the capacitive load 122 is oriented such that the positive terminal of the load 122 is effectively coupled to the ground potential and the negative terminal of the load 122 is effectively connected to the current source output 130. The capacitive load driving device 100 then recovers energy from the positively charged capacitive load 122 by allowing the inductor 120 to receive current provided by discharging the load 122. The device 100 may alternatively charge the load 122 to a negative potential.

[0035] Moreover, the capacitive load driving device 100 may hold energy in the capacitive load 122 by either actuating the switches 110 and 112 while deactivating the switches 114 and 116, or actuating the switches 114 and In 116 while deactivating the switches 110 and 112. In this way, the capacitive load driving device 100 holds energy in the capacitive load 122 by orienting the load 122 such that either the positive terminal or the negative terminal of the load 122 effectively floats. Because the capacitive load driving device 100 delivers (recovers) energy to (from) the capacitive load 122 via the inductor 120 while dissipating virtually none of this energy as heat, the power efficiency of the device 100 is increased.

[0036] A method of operating the presently disclosed capacitive load driving device 100 is illustrated by reference to FIG. 2. In this illustrative example, the controller 102 (see FIG. 1) is configured to receive an input voltage V_in302 (see FIG. 3), a measured voltage level V_Cm, a measured current level I_Lm, and optionally the clock signal CLK. The controller 102 is further configured to make determinations based on the level of the input voltage V _in302, the direction of the rate of change of the input voltage V_in302 (i.e., whether the input voltage V_in302 is increasing or decreasing), the measured voltage level V_Cm, and the measured current level I_Lm. Based on the outcome of these determinations, the controller 102 controls the DC current source 101 and plurality of interconnect switches 110, 112, 114, and 116 to generate an output voltage V_out304 (see FIG. 3) across the capacitive load 122 corresponding to the input voltage V_in302.

[0037] It is noted that the method of FIG. 2 may be performed at fixed time intervals (i.e., the capacitive load driving device 100 may operate in a synchronous manner) or at variable time intervals (i.e., the capacitive load driving device 100 may operate in an asynchronous manner). Further, the optional clock signal CLK is normally employed when the device 100 operates synchronously, and may be omitted when the device 100 operates asynchronously.

[0038] In this illustrative example, the switches 106, 114, and 116 are initially open, and the switches 110 and 112 are initially closed (alternatively, the switches 106, 110, and 112 may be initially open, and the switches 114 and 116 may be initially closed). The plurality of interconnected switches 110, 112, 114, and 116 are not allowed to be open simultaneously. As depicted in block 202, a determination is made as to whether the input voltage V_in302 is increasing. For example, the controller 102 may make this determination by comparing the level of the input voltage V_in302 at the present time with the level of the input voltage V_in302 at an earlier time. It is noted that the input voltage V_in, 302 is increasing from time t₀to time t₁, (see FIG. 3). In the event the input voltage V_in302 is increasing, a determination is made, as depicted in block 206, as to whether the voltage level V_Cmis less than the level of the input voltage V_in302, i.e.,

[0039] V_C<V_in.  (1)

[0040] In the event the voltage level V_Cmis less than the input voltage level V_in302, a determination is made as to whether the current level I_Lmis sufficient for charging the capacitive load 122. Specifically, a determination is made, as depicted in block 208, as to whether

[0041] I_L<C dV_in/dt,  (2)

[0042] in which “C” is the capacitance of the capacitive load 122. In the event the current level I_Lmis insufficient for charging the capacitive load, the inductor 120 is energized, as depicted in block 210. Specifically, the controller 102 actuates the switch 106 to allow the voltage source 104 to feed energy into the inductor 120 until

[0043] I_L≧C dV_in/dt,  (3)

[0044] at which time the switch 106 is deactivated.

[0045] When current level I_Lmis sufficient for charging the capacitive load 122, the load 122 is charged, as depicted in block 212. Specifically, the controller 102 actuates the switches 110 and 116 to allow current to flow from the inductor 120 to the capacitive load 122 (i.e., the inductor delivers energy to the load) until

[0046] V_C≧V_in  (4)

[0047] at which time the plurality of interconnected switches 110, 112, 114, and 116 revert to their initial configuration to hold the charge on the capacitive load 122.

[0048] In the event it is determined in block 202 that the input voltage V_in302 is not increasing, a determination is made, as depicted in block 204, as to whether the voltage level V_Cmis decreasing. Again, the controller 102 may make this determination by comparing the level of the input voltage V_in302 at the present time with the level of V_in302 at an earlier time. It is noted that the input voltage V_in302 is decreasing from time t₁, to time t₂(see FIG. 3). In the event the input voltage V_in302 is decreasing, a determination is made, as depicted in block 214, as to whether the voltage level V_Cmis greater than the level of the input voltage V_in302, i.e.,

[0049] V_C>V_in.  (5)

[0050] In the event the voltage level V_Cmis greater than the input voltage level V_in302, the capacitive load 122 is discharged, as depicted in block 216. Specifically, the controller 102 actuates the switches 112 and 114 to allow current to flow from the capacitive load 122 to the inductor 120 (i.e., the inductor recovers energy from the load) until

[0051] V_C≦V_in  (6)

[0052] at which time the plurality of interconnected switches 110, 112, 114, and 116 revert to their initial configuration to hold the charge on the capacitive load 122. Alternatively, the inductor 120 may charge the load 122 negatively. By repeating the above-described method at fixed or variable time intervals, the capacitive load driving device 100 (see FIG. 1) can generate an output voltage waveform V_outacross the capacitive load 122 that corresponds to essentially any arbitrary input voltage waveform V_in.

[0053] It should be understood that the method depicted in FIG. 2 is presented for purposes of illustration. In a preferred embodiment, the controller 102 employs a mathematically optimal control algorithm to control the operation of the DC current source 101 and the plurality of interconnected switches 110, 112, 114, and 116. Following such an algorithm, the controller 102 makes control decisions based not only on the state of the system at specific times but also on trends. The controller 102 then considers all of the possible control choices, and selects the one that minimizes the error between the input voltage waveform V_inand the output voltage waveform V_out.

[0054] It is noted that as the capacitive load driving device 100 selectively charges and discharges (or charges negatively) the capacitive load 122, the output voltage waveform V_out304 either ramps up or down following the same slope. As shown in FIG. 3, the output voltage waveform V_out304 ramps up following the same slope during three (3) successive time intervals between time t_oand time t₁. Further, the output voltage waveform V_out304 ramps down following the same slope during ten (10) successive time intervals between time t₁and time t₂. This is because only one current source, i.e., the DC current source 101, is used to drive the capacitive load 122.

[0055] FIG. 4 depicts an alternative embodiment 100aof the capacitive load driving device that includes a DC current source 101aconfigured to provide a plurality of current output levels. Specifically, the capacitive load driving device 100aincludes a transformer 121 having a plurality of secondary windings 120a-120d, a plurality of diodes 118a-118d, and a plurality of switches 111, 113, 115, and 117 (e.g., power MOSFET switches), which replace the single inductor 120 and the single diode 118 included in the capacitive load driving device 100 (see FIG. 1). The to primary winding of the transformer 121 is omitted from FIG. 4 for clarity. It is noted that the inductance of the secondary windings 120a-120dmay alternatively be provided by a plurality of inductors. Accordingly, the controller 102 is configured to control the operation of the switches 111, 113, 115, and 117 by generating digital control signals T₆, T₇, T₈, and T₉. The controller 102 controls the switches 111, 113, 115, and 117 either individually or in combination to provide selected current output levels at the current source output 130, thereby causing the output voltage waveform V_outto ramp up or down following different slopes. In this way, the output voltage waveform V_outcan be made to correspond more closely to the input voltage waveform V_inwith a slower switching frequency.

[0056] It will further be appreciated by those of ordinary skill in the art that modifications to and variations of the above-described power efficient capacitive load driving device may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.