Modulation method, modulation apparatus, demodulation method, demodulation apparatus, information recording medium, information transmission method, and information transmission apparatus

[0002] 1. Field of the Invention

[0003] The present invention relates to a modulation method, a modulation apparatus, a demodulation method, a demodulation apparatus, an information recording medium, an information transmission method, and an information transmission apparatus. More particularly, it relates to a modulation method, a modulation apparatus, a demodulation method, a demodulation apparatus, an information recording medium, an information transmission method, and an information transmission apparatus suitable for modulating, demodulating, recording, and transmitting a digital information signal as an information code series which satisfies k=9 in a (1, k) run length limited (hereinafter referred to as “(1, k) RLL”), while limiting the repetition of a shortest run, so that the digital information signal is recorded in storage mediums such as an optical disk and magnetic disk by a recording code series to satisfy k=9 in the (1, k) RLL.

[0004] 2. Description of the Related Art

[0005] As a recording modulation system for recording a series of digital information signals in recording mediums such as an optical disk and magnetic disk, (1, 7) RLL has heretofore been used frequently. However, in the (1, 7) RLL which has heretofore been used, it is difficult to suppress signal components in the vicinity of a direct current (DC). Depending on a bit pattern, a large DC component is generated, and for example, a spectrum of an information signal component is entrained in a servo signal band. In consequence, it is predicted that problems adversely influencing servo capabilities occur.

[0006] Moreover, it is known that the repetition of a shortest run, that is, 2T (T denotes a channel bit interval) in the (1, 7) RLL is disadvantageous for clock detection by a phase locked loop (PLL). In this connection, it is described in Jpn. Pat. Appln. KOKAI Publication No. 1994-195887 titled “Recording Code Modulation Apparatus” that a specified bit pattern is prevented from being repeated and thereby DC components are suppressed. Moreover, it is also disclosed in Jpn. Pat. Appln. KOKAI Publication No. 1998-340543 titled “Encode Apparatus, Decode Apparatus, Encode Method, and Decode Method” or in Jpn. Pat. Appln. No. 1998-150280 corresponding to KOKAI Publication No. 11-346154 titled “Modulation Apparatus and Method, Demodulation Apparatus and Method, and Providing Medium” that redundant bits are inserted not to disturb the (1, 7) RLL rule, and thereby the DC components are suppressed. Furthermore, in Jpn. Pat. Appln. KOKAI Publication No. 1999-346154, (1, 7) RLL modulation is disclosed in which the repetition of the shortest run can be limited.

[0007] However, according to the Jpn. Pat. Appln. KOKAI Publication No. 1994-195887, the repetition of the specified pattern is reduced by means such as bit reverse and randomizing, but it is difficult to sufficiently suppress the DC components. Moreover, according to the Jpn. Pat. Appln. KOKAI Publication No. 1998-340543, as compared with the former, the DC components are largely suppressed, but all of the redundant bits cannot be DSV controlled. Furthermore, unless the redundant bits are used, it is disadvantageously impossible to perform the DSV control. On the other hand, in the Jpn. Pat. Appln. KOKAI Publication No. 1998-150280, parity numbers (parity of 1 included in a symbol) of data bits and code bits are set to be the same, and the DSV control is necessarily possible by inserting the redundant bits in the data bits. However, according to the Jpn. Pat. Appln. KOKAI Publication No. 1998-150280 or 1999-346154, the DSV control is possible by the redundant bits, but there is a problem that the DSV control cannot be performed in another section.

[0008] The present invention has been developed under the above-described circumstances. An object of the present invention is to provide a method and apparatus in which even with insertion of redundant bits, DSV control is possible in any section, k satisfies 9 in a (1, k) RLL rule, and a repetition frequency of a minimum run is limited.

[0009] To achieve the object, there is provided a modulation method comprising: referring to a plurality of coding tables including output code words corresponding to input data words, and coding table designation information in which an coding table for use in encoding a next input data word is designated, to thereby encode a four bits unit of a plurality of continuous input data words into a six bits unit of a plurality of continuous output code words; and inserting two redundant bits into each predetermined number of data words of the plurality of continuous output code words, so that a digital sum variation (DSV) control is possible, k satisfies 9 in a (1, k) run length limited (RLL) rule, and a successive repetition frequency of a minimum run is limited.

[0010] Moreover, to achieve the object, there is provided a modulation apparatus comprising: a plurality of coding tables including output code words corresponding to input data words, and coding table designation information in which an coding table for use in encoding a next input data word is designated; encoding means for referring to the plurality of coding tables, and thereby encoding a four bits unit of a plurality of continuous input data words into a six bits unit of a plurality of continuous output code words; and redundant bits inserting means for inserting two redundant bits into each predetermined number of data words of the plurality of continuous output code words, so that a digital sum variation (DSV) control is possible, k satisfies 9 in a (1, k) run length limited (RLL) rule, and a successive repetition frequency of a minimum run is limited.

[0011] Furthermore, to achieve the object, there is provided a demodulation method of demodulating the plurality of continuous output code words encoded by using the modulation method according to the first aspect of the present invention and having the two redundant bits inserted into each predetermined number of data words, into a reproduction data string, the method comprising: extracting the inserted redundant bits and restoring the plurality of continuous code words; and demodulating the plurality of continuous code words into the reproduction data string based on judgment information indicating an coding table by which a subsequent code word is encoded among the plurality of coding tables, and the subsequent code word.

[0012] Additionally, to achieve the object, there is provided a demodulation apparatus which demodulates the plurality of continuous output code words encoded by using the modulation apparatus according to the second aspect of the present invention and having the two redundant bits inserted into each predetermined number of data words, into a reproduction data string, the apparatus comprising: redundant bit extracting means for extracting the redundant bits and restoring the plurality of continuous code words; and demodulating means for demodulating the plurality of continuous code words into the reproduction data string based on judgment information indicating an coding table by which a subsequent code word is encoded among the plurality of coding tables, and the subsequent code word.

[0013] Moreover, to achieve the object, there is provided an information recording medium in at least a part of which a code word encoded by using the modulation method according to the first aspect of the present invention is recorded.

[0014] Furthermore, to achieve the object, there is provided an information recording medium in at least a part of which a code word encoded by using the modulation apparatus according to the second aspect of the present invention is recorded.

[0015] Additionally, to achieve the object, there is provided an information transmission method comprising a step of transmitting a code word encoded by using the modulation method according to the first aspect of the present invention as transmission information.

[0016] Moreover, to achieve the object, there is provided an information transmission apparatus which transmits a code word encoded by using the modulation apparatus according to the second aspect of the present invention as transmission information.

[0017] The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

[0018] In the accompanying drawings:

[0019] FIG. 1 is a basic constitution diagram of a modulation apparatus of the present invention;

[0020] FIG. 2 is a block diagram of a 4-6 modulator of the present invention;

[0021] FIG. 3 is a flowchart showing an encode operation of the modulation apparatus shown in FIG. 2;

[0022] FIG. 4 is an explanatory view of the encode operation of the modulation apparatus shown in FIG. 2;

[0023] FIG. 5 is an explanatory view of insertion of redundant bits according to the modulation apparatus of the present invention;

[0024] FIG. 6 is a diagram showing a relation between a type of a precedent code word and a redundant bit pattern for use in the modulation apparatus of the present invention;

[0025] FIG. 7 is a diagram showing binary output code words each represented in six bits corresponding to decimal input data words each corresponding four bits;

[0026] FIG. 8 is a diagram showing contents of four coding tables S(k)=0 to S(k)=3 for use in the modulation apparatus of the present invention;

[0027] FIG. 9 is an explanatory view of an encode process in the modulation apparatus of the present invention;

[0028] FIGS. 10A and 10B are explanatory view of an operation of the modulation apparatus of the present invention;

[0029] FIG. 11 is a block diagram of one embodiment of a demodulation apparatus of the present invention;

[0030] FIG. 12 is a diagram showing judgment information for use in the demodulation apparatus of the present invention;

[0031] FIG. 13 is a diagram showing a demodulation table for use in the demodulation apparatus of the present invention; and

[0032] FIG. 14 is an explanatory view of the operation of the demodulation apparatus of the present invention.

[0033] Embodiments of the present invention will be described hereinafter in detail with reference to the drawings.

[0034] Types of six bits unit of output code word satisfying a (1, 7) RLL are shown in FIG. 7. As one example of an coding table based on the code word type, four coding tables shown in FIG. 8 (coding table number S(k)=“0” to “3”) can be constituted. S(k)=“0” to S(k)=“3” denote coding table selection numbers allocated to four coding tables. Moreover, S(k+1) in FIG. 8 denotes the coding table selection number for selecting the coding table for use in performing the next encoding. Additionally, for allocation of a data word D(k) and code word C(k), it is possible to change arrangement so that an encode rule is not disturbed and demodulation is not obstructed. The embodiments of the present invention are effective in constitutions other than the constitution of the coding table of FIG. 8.

[0035] Moreover, it is apparent that the constitution of the coding table for converting the data word formed of bits of an integral multiple of 4 to a code bit of an integral multiple of 6 while satisfying a DSV control rule according to the present invention and, for example, to allocate eight bits of data word to 12 bits of code word bits can easily be analogized from the present invention, and is included in the present invention.

[0036] First, a modulation apparatus 1 of the present invention will be described with reference to FIG. 1. A digital information signal obtained by converting an image, sound, and the like to be modulated into a binary series by discrete means (not shown) is subjected to so-called formatting such as addition of an error correction code and sector structuring in a format unit 11, thereafter forms a source code series every four bits, and is added to a 4-6 modulator 12.

[0037] The 4-6 modulator 12 uses an coding table 13 shown as one example in FIG. 8 to perform an encode processing described later and add a predetermined synchronous word. Thereafter, an NRZI conversion circuit 14 NRZI-converts encode information from the 4-6 modulator 12, and sends the information as a recording signal to a recording driving circuit 15. The encode information sent via the recording driving circuit 15 is recorded in a recording medium 2 or transmitted/encoded by transmission encoding means 31 and sent to a transmission medium 3.

[0038] FIG. 2 is a block diagram showing a constitution example for describing an operation of the 4-6 modulator 12 of FIG. 1 in more detail. Input data words (source codes) D(k) are added to a code word alternative presence/absence detection circuit 121, shortest run repetition detection unit 130, coding table address operation unit 122, synchronous word generation unit 123, and redundant bit insertion unit 120. The code word alternative presence/absence detection circuit 121 uses D(k) and state S(k) to detect whether there is a prospective code word having a different DSV polarity. An coding table address operation is performed based on the detection result and D(k), and prospective code words C(k)0, C(k)1 from a plurality of coding tables 13 are sent to a code word memory [0] 126, and code word memory [1] 125, respectively.

[0039] The code word memory [0] 126 and code word memory [1] 125 are connected to a DSV operation memory [0] 124 and DSV operation memory [1] 127, respectively. Every time the code words C(k)0, C(k)1 are inputted into the code word memory [0] 126 and code word memory [1] 125, CDSs are calculated, and stored DSV values are updated, and calculation results of absolute values of the DSV values are ready to output. Here, when the code word alternative presence/absence detection circuit 121 detects a source code D(k) having an alternative, an absolute value comparison unit 128 compares absolute values of DSVs stored in the DSV operation memory [0] 124 and DSV operation memory [1] 127. A memory control unit/code output unit 129 selects the code word stored in the code word memory having a smaller absolute value of DSV, outputs the code word as an output code word to the outside, and replaces contents of the code word memory and DSV operation memory on unselected side with contents of the selected side code word memory and DSV operation memory on selected side.

[0040] FIG. 3 is a flowchart showing the above-described content in detail. Additionally, it has been described that two code word memories are disposed. Moreover, when the code word alternative presence/absence detection circuit 121 detects the D(k) having alternatives, the output code word is quickly outputted. However, the number of the code word memories is not limited to two. When the D(k) having alternatives is detected, it is unnecessary to quickly output the output code word. Even in a method of disposing more memories, referring to some selectable source codes, and selecting/outputting a code word string having a smallest DSV, the present invention is effective.

[0041] The encoding of a four bits unit of input data words D(k) under (1, 7) RLL will next concretely be described with reference to FIG. 9. As input data words D(k), D(k+1) . . . , “4, 5, 6, 7, 8 (decimal)” is used as an example. In an initial state of the encoding, by operations such as insertion of a synchronous word whose description is omitted, an initial selection number of coding table is determined, for example, an coding table S(k)=“0” is selected. When the input data word D(k)=4 is inputted in the coding table S(k)=“0”, an output code word C(k)=18 (decimal) is outputted, and the next coding table selection number S(k+1)=“1” is selected. Subsequently, when the input data word D(k)=5 is inputted in the selected coding table S(k)=“1”, the output code word C(k)=9 (decimal) is outputted, and the next coding table selection number S(k+1)=“1” is selected. Similarly, when the input data word D(k)=6 is inputted in the coding table S(k)=“1”, the output code word C(k)=2 is outputted, and the coding table selection number S(k+1)=“3” is selected. Subsequently, when the input data word D(k)=7 is inputted in the coding table S(k)=“3”, the output code word C(k)=20 is outputted, and the coding table selection number S(k+1)=“1” is selected. Moreover, when the input data word D(k)=8 is inputted in the coding table S(k)=“1”, the output code word C(k)=4 is outputted, and the coding table selection number S(k+1)=“2” is selected.

[0042] As a result, “4, 5, 6, 7, 8 (decimal)” as the input data word D(k) is encoded into “010010, 001001, 000010, 010100, 000100 (binary)” as the output code word C(k) and successively outputted. Therefore, a series of output code word string obtained by successively and directly coupling the above-described five output code words C(k) is 010010001001000010010100000100, and the output code word string which satisfies the (1, 7) RLL can be obtained.

[0043] In this example, no source code having alternatives appears. However, according to the modulation apparatus described with reference to FIGS. 1 to 3, when the coding table shown in FIG. 8 is used, the code word string satisfying the (1, 7) RLL and successively and directly coupled can be obtained by four bits of source code D(k), and S(k) obtained by delaying S(k+1) outputted in outputting the previous code word by one word (having a four bit length as a source code).

[0044] An operation of the code word alternative presence/absence detection circuit 121 will next be described in detail with reference to FIG. 4. FIG. 4 is a diagram in which conditions concerning the operation of the code word alternative presence/absence detection circuit 121 with (1, 9) RLL are arranged. In FIG. 4, a respect related with a shortest run limitation and redundant bit will be described later in detail. Here, k=9 is shown, because two redundant bits are inserted in the coding table of k=7 and thereby k increases by 2. Therefore, DSV control is also performed so as to satisfy k=9.

[0045] In FIG. 4, S(k) indicates a state of a k-th symbol, L(k−1) indicates a zero run length on LSB side of the code word C(k−1) having a k−1 symbol, that is, the continuation number of bits 0, and D(k) denotes four bit data corresponding to the k-th symbol.

[0046] For condition 1, with the state S(k) of 3, when the continuation number L(k−1) of bits 0 on LSB side of the previous code word is 4 or 5, that is, 010000 or 100000, and further when the input data D(k) is 6 or less, the code word can be replaced with the corresponding code word in the coding table of S(k)=1. Similarly, when L(k−1) is 6, and when D(k) is 0, 1, 3, or 5, the code word can be replaced with the code word of S(k)=1.

[0047] For condition 2, with S(k)=2, when L(k−1) is 5 or 6 and D(k) is 7 or more, or when L(k−1) is 4 and D(k) is 10 or more, the code word can be replaced with the code word of S(k)=1.

[0048] For condition 3, with S(k)=2, when L(k−1) is not less than 1 and not more than 4, and D(k)=0 or 5, the code word can be replaced with the code word of S(k)=0.

[0049] For condition 4, in states other than a state immediately before the redundant bits, when L(k−1)=1 and D(k) is 13 or 15, the code word can be replaced with the code word of S(k)=0. Moreover, immediately before the redundant bits, when L(k−1)=1, D(k)=15, and D(k+1) is 7 or more, or 0 or 5, the code word can be replaced with the code word of S(k)=0. Furthermore, immediately before the redundant bits, when L(k−1)=1, D(k)=13, and D(k+1) is 6 or less, or 13 or 15, the code word can be replaced with the code word of S(k)=0.

[0050] For condition 5, with S(k)=2, in the state other than the state immediately before the redundant bits, and when L(k−1)=2, and D(k)=13 or 15, the code word can be replaced with the code word of S(k)=0.

[0051] For condition 6, with S(k)=2 and L(k−1)=3, in the state other than the state immediately before the redundant bits, when D(k)=13, and D(k+1) is 6 or less, or 13 or 15, the code word can be replaced with the code word of S(k)=0.

[0052] For condition 7, with S(k)=2 and L(k−1)=3, in the state other than the state immediately before the redundant bits, when D(k)=15, and D(k+1) is 7 or more, or 0 or 5, the code word can be replaced with the code word of S(k)=0.

[0053] All the pairs of code words replaceable with each other on the conditions 1 to 7 are arranged such that the number of 1 included in code bits of one code word of each pair is even while the number of 1 included in code bits of the other code word is odd and that code words of each pair have the same next state S(k+1) as shown in FIG. 8. Moreover, even with the replacement, the (1, 9) RLL is not broken. Furthermore, the difference in the number of 1 between the code words enables the DSV control apparently because the difference in the number of 1 between C(k)s causes the reverse of the output level after NRZI modulation as shown in FIGS. 10A and 10B. For this reason, according to the present modulation method and apparatus, as described above, while the (1, 9) RLL is satisfied, the DSV control is possible.

[0054] Additionally, as described above, according to the coding table of the present invention, a plurality of coding tables 13 are used which include the output code word C(k) corresponding to the input data word D(k) and coding table designation information S(k+1) for designating the coding table for use in encoding the next code word. This can realize the modulation method or the modulation apparatus in which the code having the (1, 9) RLL can be generated.

[0055] The insertion of the redundant bits according to the present invention will next be described with reference to FIGS. 5, 6, 8. FIG. 5 is a diagram showing the constitution of the synchronous frame in which the redundant bits are inserted for each N data symbol after the synchronous word. As shown in FIG. 6, the redundant bits can take 01 or 00 when the LSB of the precedent code word is 0, and can take 10 or 00 when the LSB of the precedent code word is 0.

[0056] For the redundant bits 01, bits 00 enable the DSV polarity to be reversed. Similarly, for the redundant bits 10, bits 00 enable the DSV polarity to be reversed.

[0057] Here, as described with reference to FIG. 4, according to the coding tables of FIG. 8, it is possible to generate the code word by the limitation of k=7 and even with the redundant bits of 00, the limitation of k=9 can be maintained. That is, according to the present invention, when two redundant bits are inserted in each predetermined interval, that is, the N data symbol interval, the code word series having an opposite DSV polarity can be surely generated.

[0058] For example, in FIG. 8, when S(k)=0 and D(k)=13, C(k) is 000000, and the number of 0 on the MSB side of the next code word is one at maximum. Here, even when the redundant bits of 00 is inserted, the number of 0 is limited to 9, and thus k=9 can be maintained. Additionally, the redundant bits can be inserted even before or after the code bit to be encoded at present.

[0059] The method of the DSV control applicable even when the redundant bits according to the present invention are inserted will next be described with reference to FIG. 3 based on the above-described selection of the code word.

[0060] First, in FIG. 3, an initial table can be set by determining the S(k) subsequent to the synchronous word to be added to the code word (step 101). Subsequently, four bits of source code D(k) are inputted (step 102), and encoded by S(k) and D(k) according to the coding tables of FIG. 8. In this process, the previously encoded C(k−1) is referred to, the zero run length on the LSB side is calculated, and the bit pattern of LSB is detected. Thereafter, it is next judged whether the next code word is one to be added with the redundant bits (step 103). If No, it is judged according to the condition of FIG. 5 whether there is an alternative of the code word (step 104).

[0061] When the selectable code word is not present in the coding table (“absent” in step 104), the code words C(k)0, C(k)1 outputted from the coding tables are added to the code word memory [0] 126 and code word memory [1] 125, respectively (step 108), the respective CDSs are calculated, and the DSV operation memory [0] 124 and DSV operation memory [1] 127 are updated (step 109).

[0062] When the selectable code word exists in the coding table (“present” in step 104), the code word alternative presence/absence detection circuit 121 outputs the signal indicating the presence of the alternative, the absolute values outputted from the DSV operation memory [0] and DSV operation memory [1] are compared in an absolute value comparison unit 128, and the code series (code word) having a smaller absolute value is selected and outputted from the memory control unit/code output unit 129 (step 105). Thereafter, the contents of the unselected code word memory and DSV operation memory are rewritten with the contents of the selected code word memory and DSV operation memory (step 106). Subsequently, as described with reference to FIG. 4, the code words selectable as the prospective code words are selected from one coding table and the other coding table determined by S(k), and outputted as C(k)0, C(k)1 (step 107).

[0063] Subsequently, the respective code words C(k)0, C(k)1 outputted from the coding table are added to the code word memory [0] 126 and code word memory [1] 125, respectively (step 108), the respective CDSs are calculated, and the DSV operation memory [0] 124 and DSV operation memory [1] 127 are added with the respective calculated CDSs (step 109).

[0064] On the other hand, when the next code word is one to be added with the redundant bits (Yes in step 103), the absolute values outputted from the DSV operation memory [0] and DSV operation memory [1] are compared in the absolute value comparison unit 128, and the code series (code word) having a smaller absolute value is selected and outputted from the memory control/code output unit 129 (step 111). Thereafter, the contents of the unselected code word memory and DSV operation memory are rewritten with the contents of the selected code word memory and DSV operation memory (step 112). Subsequently, as described with reference to FIG. 6, the redundant bit pattern is selected according to the LSB of the code word, the code word obtained by adding one of the redundant bits to the code word is set to C(k)0, and the code word with the other redundant bits added thereto is set to C(k)1, and the C(k)0 and C(k)1 are added to the code word memory [0] 126 and the code word memory [1] 125 (steps 113, 108). The CDSs of the prospective code words C(k)0, C(k)1 are calculated, and the DSV operation memory [0] 124 and DSV operation memory [1] 127 are added with the respective calculated CDSs (step 109). When the above-described operation is performed until the end of the coding (step 110), the generation of the code word with the suppressed DC components including the redundant bits terminates.

[0065] Additionally, as described with reference to FIG. 4, by the insertion of the redundant bits, the condition on which the code word can be converted sometimes differs. For example, on the condition 4, the replacement condition differs immediately before the redundant bit. This is a processing for maintaining k=9, even when two redundant bits are 00. Moreover, similarly, immediately after the redundant bit, the code word conversion with L(k−1)=6 is not performed. The above processing enables (1, 9) RLL to be maintained even when the redundant bits are inserted.

[0066] That is, as described above, according to the present invention, a plurality of coding tables 13 are used including the output code word C(k) corresponding to the input data word D(k), and the coding table designation information S(k+1) for designating the coding table for use in encoding the next code word, and two redundant bits are inserted in each predetermined data word in the output code word outputted as a binary series, so that the DSV control can necessarily and apparently be possible while k=9 is satisfied.

[0067] A prohibition processing of the repetition of the shortest run will next be described. In FIG. 8, the repetitions of the shortest run, that is, 2T pattern includes the repetition of S(k)=0 and D(k)=8 and the repetition of S(k)=2 and D(k)=15.

[0068] First, in the former repetition, that is, when further D(k)=8 comes after S(k)=0 and D(k)=8, D(k)=8 is replaced with D(k)=12 by way of exception, and the next state, that is, the coding table S(k)=1 is selected. That is, 010101 010101 is changed to 010000 000100. This pattern is not a replaceable pattern as described with reference to FIG. 4. After 010000, the state S(k+1) is 2 or 3, and does not transfer to 1, and decoding is possible by way of exception.

[0069] Moreover, in the latter repetition, that is, when further D(k)=15 comes after S(k)=2 and D(k)=15, similarly as the code word replacement on the condition 4, 101010 101010 may be replaced with 101010 000000, and without any exception, the decoding is possible.

[0070] On the condition 4 shown in FIG. 4, the repetition of 101010 is prohibited. After all the conditions are checked, the repetitions of the 010101 and 101010 patterns are prohibited.

[0071] To detect the occurrence of the successive repetition, with 010101, the repetition of S(k)=0 and D(k)=8 may be monitored. With 101010, the repetition of S(k)=2 and D(k)=15 may be monitored. In FIG. 2, the shortest run repetition detection unit 130 checks the output code word C(k−1), state S(k), and input data word D(k) to detect the repetition of the shortest run, sends the results to the coding table address operation unit 122, and limits the repetition of the shortest run.

[0072] A demodulation method and apparatus according to the present invention will next be described. FIG. 11 shows one embodiment of the demodulation apparatus suitable for the present invention.

[0073] For the input code words other than the input code words with the redundant bits inserted therein, the bit string of the input code words is NRZI-demodulated by an NRZI demodulator 501, and a synchronization detection circuit 502 detects the synchronous word. The NRZI-demodulated signal and synchronous word are constituted in a code string C(k) each having six bit length by a serial/parallel converter 503 in accordance with a word clock as a timing signal for conversion to parallel six bits. Thereafter, the code word C(k−1) inputted into a word register 504 and delayed by one word is inputted into a detection unit 505 of judgment information of the code word, and the judgment information described later is calculated/outputted. The judgment information and input code word Ck are inputted in a state calculator 506, and the state S(k) indicating the coding table by which the encoding has been performed among four coding tables is outputted. In accordance with an address by the code word C(k−1) and state S(k) in an address generator 507, the output data word is outputted, for example, from a decoding table 508 shown in FIG. 12.

[0074] As described with reference to FIG. 5, the insertion position of the redundant bits can be known by the word clock from the synchronization detection circuit 502 in which the synchronous word is used as a reference, and a bit clock generated by PLL means (not shown), and a redundant bit extractor 509 can remove the redundant bits. The code word series from which the redundant bits are removed is decoded as described above.

[0075] As shown in FIG. 12, the judgment information is divided into four for 0, 1, 2, and 3, and indicates the coding table by which the next code word is to be encoded by the zero run length on the LSB side. That is, the coding table by which the previous code word C(k−1) and the present code word are to be encoded is known, and thereby the code word C(k−1) is demodulated into the output data word D(k−1).

[0076] Equation 1 is a calculation for obtaining the state S(k) from the code word C(k) and judgment information, and is described in C language. According to the calculation, the state S(k) is obtained from the judgment information and code words C(k), C(k−1), and the code word C(k−1) can be demodulated in the output data word D(k−1) according to the demodulation table of FIG. 13.

[0077] For example, as shown in FIG. 14, when a code word string 010000 001001 000001 000101 010001 is inputted in the demodulation apparatus shown in FIG. 11, for the judgment information of the code word C(k−1)=010000, the zero run length on the LSB side is 4, and therefore the judgment information is 3 as shown in FIG. 2. Moreover, the next code word C(k) continues as 001001 (9 in decimal), this is applicable to a first condition judgment of Equation 1, and it is therefore seen that S(k) is 0. Therefore, with the code word C(k−1) of the demodulation table of FIG. 13, the state S(k) of row 010000 is 3, and 14 is obtained as the output data word D(k−1). That is, the output data word D(k−1) corresponding to the code word C(k−1) of a time k−1 is determined from the state information (number) S(k) of the coding table in which the code word C(k) of a time k is generated. Similarly, for 001001, the judgment information is 0, and 000001 of the subsequent code word is in the state S(k)=0 of the coding table. Therefore, the output data word D(k−1) is obtained as 0 according to the demodulation table of FIG. 13. Similarly, for 000001, D(k−1) is obtained as 1, and for 000101, D(k−1) is obtained as 1. Additionally, 001001 is a code word replaced on a first condition of the condition 1 of FIG. 4 for the DSV control. However, from the above description, it is apparent that the decoding can normally be performed.

[0078] As described above, according to the present invention, the continuous binary data series is converted to the four bit unit of the input data word. Thereafter, it is possible to insert the redundant bits such that the DSV polarity can necessarily be reversed for each predetermined data word interval. Moreover, the DSV control is possible even in the coding table, the DC components of the output code word string can effectively be suppressed, and it is possible to limit the repetition of the shortest run.

[0079] It should be understood that many modifications and adaptations of the invention will become apparent to those skilled in the art and it is intended to encompass such obvious modifications and changes in the scope of the claims appended hereto.