Oscillator circuit with automatic level control for selectively minimizing phase noise

[0002] 1. Field of the Invention

[0003] The present invention relates to oscillator circuits, such as voltage controlled oscillator (VCO) circuits, and in particular, oscillator circuits having automatic level control for controlling the amplitude of the oscillator output signal so as to control the amount of phase noise within such signal.

[0004] 2. Description of the Related Art

[0005] In oscillator circuit design, particularly when designing VCO circuits for use in a phase lock loop (PLL), a key design parameter is that of the phase noise performance of the oscillator. As is well known in the art, the term phase noise is generally used for. describing short term, random frequency fluctuations of a signal, such as that generated by an oscillator. The frequency stability of the oscillator circuit is a measure of the degree to which the oscillator maintains the same value of output signal frequency over a given interval of time. The ideal output signal from a sine wave oscillator is generally described as:

[0006] V(t)=Vo* sin(2πft)

[0007] where: V(t)=oscillator output signal

[0008] Vo=nominal amplitude of oscillator output signal

[0009] f=frequency in Hertz (Hz)

[0010] t=time in seconds

[0011] while the instantaneous output signal of the oscillator is generally represented by:

[0012] V(t)=Vo*{1+A(t)}*sin{2πft+Δφ(t)}

[0013] where: A(t)=normalized amplitude fluctuations of oscillator output signal

[0014] Δφ(t)=phase fluctuations of oscillator output signal in radians

[0015] Amplitude fluctuations in an oscillator signal can be removed, at least partially, by using a limiting amplifier. However, the phase noise of such a signal cannot be filtered out by any conventional means, and must be minimized at the point of generation. The magnitude of an oscillator's phase noise close in to the carrier can be expressed by Leeson's equation, as follows:

[0016] L(Δω)=10*log[2FkT/Psig*(ω_o/2QΔω)²]

[0017] where: L(Δω)=phase noise power spectral density of the oscillator in dBc/Hz

[0018] F=equivalent noise factor of the negative R cell

[0019] Psig=signal power in the oscillator

[0020] ω_o=center frequency of the oscillator

[0021] Q=loaded Q (quality factor) of the oscillator tank

[0022] Δω=frequency offset from the center frequency

[0023] k=Boltzmann's constant

[0024] T=temperature in Kelvin

[0025] As predicted by Leeson's equation, phase noise can be reduced by increasing oscillation amplitude. Since Psig is proportional to Vo², the phase noise decreases by a factor of 4 each time the oscillation voltage is doubled. However, most oscillators operate in a state of saturation. As a result, simply increasing the output signal level will cause adverse loading effects, such as those from increased base currents flowing through the bipolar transistors used for generating the output signal. These loading effects manifest themselves as a dramatic reduction in loaded Q of the tank circuit, degrading phase noise per the equation above.

[0026] The phase noise of the oscillator is often one of the more significant limiting factors in the performance capabilities of the host system, such as the ability of a radio receiver to reject undesired signals and preserve modulation fidelity of the frequency down converted signals. For example, in a radio transceiver, poor oscillator phase noise can lead to undesirable noise transmissions outside the desired bandwidth of the channel being transmitted. Hence, the phase noise of the oscillator circuit is one of the primary figures of merit used to determine the performance of the overall system.

[0027] Several factors play a role in the phase noise performance of the oscillator. The quality factor (“Q”) of the resonator, the noise factor of the negative impedance cell and the oscillation signal amplitude all affect the phase noise of the oscillator, as shown in Leeson's equation.

[0028] One conventional technique that has been used to address the effect of the oscillation signal amplitude upon the phase noise performance is to introduce automatic level control for establishing the amplitude of the oscillation signal at the appropriate level needed for achieving the desired phase noise. Such conventional automatic level control techniques have involved the detection of the oscillation signal (e.g., in terms of peak, peak-to-peak or RMS voltage) and comparing such detected voltage to a fixed voltage reference.

[0029] However, such automatic level control techniques do not allow the circuit to maintain the desired amount of control over the phase noise throughout significant variations in circuit operating temperature, power supply voltages and fabrication processes used to produce such circuit. Accordingly, it would be desirable to have a form of automatic level control for an oscillator circuit to optimize the amplitude performance of the oscillator in such a manner as to provide consistent control over its phase noise performance, and to maintain such control not withstanding variations in circuit operating temperature, power supply voltages and fabrication processes.

[0030] An oscillator in accordance with the presently claimed invention generates an oscillation signal having an amplitude that is automatically controlled for a selectively minimized phase noise. Automatic level control is used for controlling the amplitude of the oscillation signal such that the phase noise of the oscillation signal can be minimized or maintained at some selected level.

[0031] In accordance with one embodiment of the presently claimed invention, an oscillator with an oscillation signal amplitude that is automatically controlled for a selectively minimized oscillation signal phase noise includes oscillator circuitry and voltage control circuitry. The oscillator circuitry including first and second circuit terminals and an active circuit portion coupled between the first and second circuit terminals, responsive to an amplitude control signal, generates an oscillator signal, wherein the first and second circuit terminals are at first and second DC bias potentials, respectively, and the first DC bias potential is higher than the second DC bias potential. The voltage control circuitry, coupled to the oscillator circuitry and responsive to a comparison of a minimum signal voltage at the first circuit terminal and a maximum signal voltage at the second circuit terminal, generates the amplitude control signal such that a difference between the minimum and maximum signal voltages is maintained at a predetermined voltage amplitude.

[0032] In accordance with another embodiment of the presently claimed invention, a method for generating an oscillation signal amplitude that is automatically controlled for a selected oscillation signal phase noise includes the steps of

[0033] operating an active circuit between first and second circuit terminals, wherein the first and second circuit terminals are at first and second DC bias potentials, respectively, and the first DC bias potential is higher than the second DC bias potential;

[0034] receiving an amplitude control signal;

[0035] generating, in response to the amplitude control signal, an oscillator signal with a minimum signal voltage at the first circuit terminal and a maximum signal voltage at the second circuit terminal, wherein a difference between the minimum and maximum signal voltages is maintained at a predetermined voltage amplitude;

[0036] comparing the minimum and maximum signal voltages; and

[0037] generating the amplitude control signal in response to the voltage comparison.

[0038] FIG. 1 is a schematic diagram of an oscillator circuit with automatic level control in accordance with one embodiment of the presently claimed invention.

[0039] FIG. 2 is a schematic diagram of one example embodiment of the circuit of FIG. 1.

[0040] FIG. 3 is a schematic diagram of an oscillator with automatic level signal control in accordance with another embodiment of the presently claimed invention.

[0041] FIG. 4 is a schematic diagram of an alternate embodiment of the circuit of FIG. 3.

[0042] FIG. 5 is a schematic diagram of an alternate embodiment of the circuit of FIG. 2.

[0043] Referring to FIG. 1, an oscillator circuit 10 in accordance with one embodiment of the presently claimed invention includes an oscillator circuit in the form of a differential amplifier implemented with NPN bipolar transistors Q1, Q2 cross coupled with capacitors C9, C10. The reactive load elements L5, L6, C11, C12 primarily determine the oscillation frequency of the circuit, while a current source 18 with a controllable current source circuit I11 provides the tail current Itail for the differential transistor pair Q1, Q2. (All elements are biased between power supply terminals VCC and circuit ground GND.)

[0044] The collector voltages Vc1, Vc2 of transistors Q1 and Q2 provide the oscillator output signal in the form of a differential output voltage Vc1-Vc2. These voltages, Vc1, Vc2 are each detected by a voltage detector 12nin the form of a negative peak detector (discussed in more detail below).

[0045] Similarly, the emitter voltage Ve present at the commonly connected emitter terminals of the transistors Q1, Q2 is detected by another voltage detector in the form of a positive peak detector 12p(discussed in more detail below).

[0046] The negative peak detector 12ndetects the minimum collector voltage Vcmin for each of the transistor collector voltages Vc1, Vc2. Conversely, the positive peak detector 12pdetects the maximum emitter voltage Vemax of the emitter voltage Ve at the commonly connected emitter terminals of the transistors Q1, Q2. The minimum detected collector voltage 13nis reduced by a voltage factor Vsat, generated by a voltage reference circuit 14. The resulting voltage 15 is compared to the maximum detected emitter voltage 13pin an error amplifier 16 (e.g., an operational amplifier integrator circuit) to produce a control voltage 17.

[0047] This control voltage 17 is an amplified version of the difference between the input voltages 15, 13p. Normally, the gain of the amplifier 16 is quite high such that the voltage difference between the two input terminals is driven to zero. It is this feedback operation that ensures that the following equations are satisfied:

[0048] Vcmin=Vemax+Vsat

[0049] Vcmin−Vemax=Vcemin=Vsat

[0050] where: Vcmin=minimum detected collector voltage

[0051] Vemax=maximum detected emitter voltage

[0052] Vsat=collector-emitter saturation voltage (e.g., 0.4 volt)

[0053] Vcemin=minimum collector-emitter voltage

[0054] Based upon the foregoing, it can be seen that, in accordance with the presently claimed invention, two voltage detectors are used to detect the minimum collector voltage Vcmin and maximum emitter voltage Vemax of the main oscillator device (or devices). This voltage difference is then effectively compared to a desired voltage difference, such as the saturation voltage Vsat of such oscillator device. Based upon this voltage comparison, a control voltage is used to ensure that the voltage difference between the minimum collector voltage Vcmin and maximum emitter voltage Vemax is maintained at an amplitude that corresponds to the voltage factor Vsat. For example, by maintaining this voltage difference equal to the saturation voltage of the main oscillator device, the phase noise within the oscillation signal will be minimized.

[0055] By controlling the minimum collector voltage(s) Vcmin and maximum emitter voltage Vemax, the control voltage 17 thereby controls the minimum collector-emitter voltage Vcemin across the transistors Q1, Q2. This is accomplished by controlling the tail current Itail. Hence, the control voltage 17 is used to control, or modulate, the current generator circuit I11 within the current source 18. By controlling the tail current Itail, the individual device currents Iq1, Iq2 through the transistors Q1, Q2 are controlled, thereby controlling the amplitudes of the collector Vc and emitter Ve voltages potentially available at the collector and emitter terminals, respectively, of the transistors Q1, Q2.

[0056] Based upon the foregoing discussion, it: should be readily appreciated that this type of oscillation circuit is capable of tracking variations in circuit power supply voltages, operating temperature and fabrication processes since two voltages generated within the circuit are constantly monitored and compared against one another. Hence, any changes in these voltages due to such power supply voltage, operating temperature or fabrication process variations will become self canceling.

[0057] As depicted in FIG. 1, the voltage reference circuit 14 may be controlled by some form of bias control signal Vb so as to allow th e amplitude of the voltage factor Vsat to be selectively adjusted. For example, depending upon a given application for the circuit 10, it. may be desirable to cause this voltage factor Vsat to be equal to some amplitude other than the saturation voltage of the oscillation transistors Q1, Q2.

[0058] Referring to FIG. 2, one example embodiment 10aof the circuit 10 of FIG. 1 includes a negative peak detector circuit 12naand a positive peak detector circuit 12paimplemented as shown. In the negative peak detector circuit 12na, the minimum, or negative, signal peaks of the collector voltages Vc1, Vc2 are detected by the diodes D0, D1 and used to charge a shunt capacitor C17. The voltage across this capacitor C17 biases the base of a voltage follower transistor Q9, which is maintained in a normally on state by a base current source I26 and emitter current source I23. The emitter voltage of transistor Q9 forms the output signal 13nof the negative peak detector circuit 12naand is equal to the minimum, or most negative, peak voltage of the transistor collector voltages VC1, VC2 since the junction voltages of the diodes D0, D1 are in series and polarity opposition to the base-emitter voltage of transistor Q9.

[0059] In the positive peak detector circuit 12pa, the common emitter voltage Ve of the oscillation transistors Q1, Q2 is detected by detecting the corresponding base voltages Vb1, Vb2 which differ from the emitter voltage Ve by the well-known relationship of the base-emitter voltage Vbe of the transistors Q1, Q2. These base voltages Vb1, Vb2 are detected by the base-emitter junctions of transistors Q11 and Q10, respectively, to produce a combined detected voltage across the shunt current source 128 (used to bias transistors Q10 and Q11 in normally on states) and shunt capacitor C18. Shunt capacitor C18 provides a positive peak hold function, provided that the discharge time of the capacitor C18 through the current source I28 is much longer than one period of the oscillation signal. Hence, the voltage of the output signal 13pis equal to the maximum, or most positive, peak of the emitter voltage Ve due to the self-canceling effects of the serially connected and polarity opposed base-emitter voltages of the oscillator transistors Q1, Q2 and detector transistors Q11, Q10.

[0060] The current source 18ain this circuit 10ais implemented using NPN bipolar transistor Q3 as the current source circuit to generate the tail current Itail for the differential transistor pair Q1, Q2.

[0061] Referring to FIG. 3, an alternative embodiment 10bof an oscillator circuit in accordance with the presently claimed invention generates a non-differential, or single-ended, oscillator output signal. In this circuit 10b, a single oscillation transistor Q1 biased by a resistor R12 to the power supply VCC and the current source 18 to circuit ground GND, generates the oscillation signal Vc at its collector terminal, with the frequency determined by an inductor L13 and capacitors C26, C27. The operation and functionality of the remaining circuitry, including the detector circuits 12n, 12p, voltage reference circuit 14 and error amplifier circuit 16, are in accordance with the discussion above.

[0062] Referring to FIG. 4, an alternative embodiment 10cof the circuit of FIG. 3 uses a crystal in place of the inductive circuit element L13 (FIG. 3) to establish the oscillation frequency. (Additionally, as is well known in the art, the use of the crystal in place of the inductive element causes the oscillation frequency to be significantly more stable.)

[0063] Referring to FIG. 5, an alternative embodiment 10dof the circuit 10aof FIG. 2 has an oscillator circuit whose frequency is controlled by a frequency control voltage Vfc that controls the bias on varactor diodes D6, D7 connected between the collector terminals of the oscillator transistors Q1, Q2. The remaining circuitry operates in accordance with the discussion above concerning FIG. 2.

[0064] It should be noted and readily appreciated that although the discussion of the presently claimed invention has been in the context of an oscillation circuit using NPN transistors, the principles discussed herein are also applicable to oscillator circuits implemented with PNP transistors, with appropriate reversals of power supply polarities and connections of the tail current source 18 and reactive circuit elements in accordance with well known circuit design techniques.

[0065] Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.