Interference canceller

[0002] 1. Field of the Invention

[0003] The present invention relates to interference canceling, and more particularly, to interference canceling for use in a code division multiple access (CDMA) cellular telephone system.

[0004] 2. Description of the Related Art

[0005] Code Division Multiple Access (CDMA) is a digital multiple access method specified by the Telecommunications Industry Association (TIA) as IS-95. CDMA is a form of spread-spectrum. The basic principle of spread-spectrum is the use of noise-like carrier waves, and, as the name implies, bandwidths much larger than that required for simple point-to-point communication at the same data rate. CDMA receivers separate communications channels using pseudo-random modulation that is applied and removed in a digital domain, not on the basis of frequency. Multiple users occupy the same frequency band. This universal frequency reuse is crucial to the very high spectral efficiency that is characteristic of CDMA.

[0006] CDMA systems are interference limited, which means that the interference caused by other users is the critical factor which prevents even more users from being added. Therefore, controlling the impact of interference is a key concern in systems which use CDMA.

[0007] Current systems, such as IS-95, derive their interference reduction from two sources, random spreading codes and power control. Random spreading ensures the interference looks like noise, not a signal and power control attempts to keep the interference power at a minimum.

[0008] A completely different approach to improving systems which use CDMA is to actively cancel interference, rather than having it contribute to noise. Such approaches improve CDMA system capacity by at least 50%. Two types of known interference cancellers are “parallel” and “successive” interference cancellers, where successive interference cancellers are generally considered to provide better performance.

[0009] In both, interference signals are subtracted out from the desired signal. The difference is primarily the order in which the subtraction is performed. In a parallel canceller, all subtractions are done at the same instant. For example, a parallel canceller includes a number of parallel processors. Each parallel processor includes a detector, a regenerator, a subtractor, and a delay circuit. Each parallel processor receives the same input signal. If there are K users in the system, then each branch of the parallel canceller receives K input signals. Each parallel branch of the parallel canceller “picks out” one user signal from the total and subtracts that one user signal.

[0010] Successive cancellers differ from parallel cancellers in that cancellations are not done at the same instant, but rather sequentially. In particular, the first serial processor in the successive canceller receives K signals, the second serial processor receives only K−1, then K−2, and so on. By the time the signal gets to the second serial processor, one signal has been cancelled. If the cancellations are done correctly, then each successive serial processor down the chain receives a signal with a better signal-to-noise ratio.

[0011] As shown in FIG. 1, the structure of a conventional successive interference canceller 10 includes several identical processors 12, 14, 16, in series. Each serial processor 12, 14, 16 includes a detector 20 which produces a data bit estimate 34, a regenerator 24 which receives the data bit estimate 34, and produces a waveform 26, a delay circuit 28 which delays the input signal to processor 12 to produce a delayed signal 30, and a subtractor 32 which subtracts the waveform 26 output from the regenerator 24 from the delayed signal 30 output from the delay circuit 28 to produce a signal including K−1 users 35.

[0012] Each serial processor 12, 14, 16 in the “pipeline” architecture illustrated in FIG. 1 can be implemented as a separate microprocessor or as a separate digital signal processor circuit. The “pipeline” architecture is used to divide up the problem because of the limited speed of each microprocessor/digital signal processor circuit by assigning each of the K users to a separate serial processor 12, 14, 16, which can be implemented separately from the other serial processors, and hence run quickly. Each serial processor 12, 14, 16 produces a data bit estimate 34, 36, 38 for one of the K users.

[0013] There are several problems with the conventional successive interference canceller illustrated in FIG. 1. One is the delay for a particular user. The data for the Kth user is not detected until K symbol times after receipt, which is often unacceptably long. The second problem is a “reordering” problem. To achieve the best performance from a successive canceller, the K users must be assigned to particular places in the hierarchical chain, depending on the power of the user's signal. This order must change from time to time as the K users move about and their signal strengths vary. An order controller 40 is required to control the detector 20 and the regenerator 24 by assigning spreading codes, parameters, etc., to each serial processor 12, 14, 16, and this ordering must change in real time since the ordering reflects the receive power of each user.

[0014] This reordering causes a special problem for the conventional successive interference canceller architecture. To illustrate this problem, assume a receiver is running with an established order of users. Due to signal strength variations, a third user (user 3), should be placed first (the current location of user 1), and user 1 should be moved to the previous location of user 3. If the order is switched immediately, the data “in the pipeline” that is being held in between positions will be adversely affected. In this example, the data at stage 2 has already canceled user 1. However, when reaching stage 3, the architecture now cancels user 1 again, and user 3 is never canceled.

[0015] The present invention solves this problem by providing a successive interference canceller which includes a number of parallel processors. Rather than being assigned a particular user, each of the parallel processors is assigned a time segment which includes data for all users. Each processor receives an assigned time segment and assigns an order to each of the K user signals independent of the other processors. The outputs of the N processors are then multiplexed together to form a data signal for all K users in time sequence. This architecture does not result in an unacceptable delay for any one of the users and does not have the same reordering problem found in the conventional successive interference canceller architecture, since each processor is permitted to assign its own order independently.

[0016] FIG. 1 is a block diagram of a conventional successive interference canceller; and

[0017] FIG. 2 illustrates a successive interference canceller with parallel processors, in one embodiment of the present invention.

[0018] FIG. 2 illustrates the successive interference canceller of the present invention in one embodiment. In particular, the successive interference canceller 100 includes a demultiplexer 102, N processors 104, 106, 108 (where N>1) and a multiplexer 110. Each of the N processors 104, 106, 108 includes a memory 112, a detector 120, a memory 114, a regenerator 124, a delay 128, a subtractor 132, and an ordering controller 140. All the functions of the N processors 104, 106, 108 including the functions of the detector 120, the regenerator 124, the delay 128, the subtractor 132 and the ordering controller 140 can also be implemented through the use of software, embodied on an appropriate medium, executing on a processor. In a preferred embodiment, each of the N processors is a digital signal processor chip.

[0019] The successive interference canceller 100 illustrated in FIG. 2 operates as discussed below. The demultiplexor 102 receives an input signal including K user signals and demultiplexes the input signal into N (wherein N>1) time segments, where each time segments contains a portion of each of the K user signals. Each of the N time segments is supplied to a corresponding one of the N processors 104, 106, 108. Each of the N processors 104, 106, 108 assigns its own unique ordering to each of the K user signals supplied thereto, independent of the ordering applied by the other N−1 processors. Each of the N processors 104, 106, 108 outputs K user symbols for their assigned time segment. The K user symbols output from the N processors are input to multiplexor 110, which multiplexes the K user symbols to form a data signal for all K users in time sequence.

[0020] As illustrated in FIG. 2, each of the N processors 104, 106, 108 receives a time segment which contains a portion of each of the K user signals. The time segment is input to a memory 112 and then provided to the detector 120 and the delay 128. The detector 120 produces a resulting symbol 136 for a first of the K users, which is supplied to the regenerator 124 which produces a waveform 138. The waveform 138 output from the regenerator 124 is subtracted from a delayed signal 139 from the memory 112 (delayed by delay 128) in subtractor 132. The output 141 of subtractor 132 is returned to the memory 112. The above functions are then repeated for each of the K users. The resulting symbols 136 output from the detector 120 are stored in memory 114 until all K users are completed. Once all K users are completed, the memory 114 outputs the K users symbols 134 for the time segment applied to the processor 104, to multiplexer 110.

[0021] In one embodiment, each of the N processors 104, 106, 108 is a conventional serial canceller. As set for above, each of the N processors are assigned a time segment and not a single one of the K users.

[0022] In another embodiment, the N time segments overlap in order to ensure no data is lost. As illustrated in FIG. 2, since each of the N processors 104, 106, 108 is working in parallel, the K user symbols 134 are output at substantially the same time and none of the K user symbols are subject to the delay caused by storage in a data pipeline, as described in the conventional successive interference canceller.

[0023] The foregoing merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are thus within its spirit and scope.