US 6,645,847 B2Grant
Microelectronic interconnect material with adhesion promotion layer and fabrication method
Issue Date:2003-11-11
•22 Claims
•1 Drawing Sheets
Abstract
A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
Metadata
Assignee
- CVC Products, Inc.
Inventors
- Ajit P. Paranjpe
- Mehrdad M. Moslehi
- Boris Relja
- Randhir S. Bubber
- Lino A. Velo
- Thomas R. Omstead
- David R. Campbell, Sr.
- David M. Leet
- Sanjay Gopinath
Application Information
Application Number:US 10/060,548
Filing Date:2002-01-30
Priority Date:1998-12-22
Art Unit:7
Classifications
IPC:
H01L 214763
Field of Search:
438618438620438626438627438628438622438637438643438644438645438680438681438687
Patent Drawings (1 sheets)
Description
Cross Reference to Related Applications
[0002] This application is a continuation of application Ser. No. 09/518,294 filed by Ajit P. Paranjpe et al. on Mar. 3, 2000 entitled “Microelectronic Interconnect Material with Adhesion Promotion Layer and Fabrication Method,” now U.S. Pat. No. 6,365,502, which is a continuation-in-part and claims priority from application Ser. No. 09/219,147 filed by Ajit P. Paranjpe et al. on Dec. 22, 1998 entitled “Semiconductor Chip Interconnect Barrier Material and Fabrication Method,” now U.S. Pat. No. 6,294,836.
Technical Field of the Invention
[0003] This invention relates in general to the field of semiconductor electronic devices, and more particularly to an improved microelectronic interconnect copper metallization structure having a cobalt-based or ruthenium-based adhesion promotion layer between diffusion barrier and copper layers and method of fabricating the same.
Background of the Invention
[0004] Microelectronic semiconductor integrated circuit chip fabrication technology has focused on techniques and materials to produce smaller and faster devices with increasing packing densities for higher performance chips. This trend towards miniaturization has led to demand for improved semiconductor integrated circuit (IC) interconnect performance and improved manufacturability, resulting in a shift from conventional Al/SiO2interconnect architectures to copper-based metallization in conjunction with low-permitivity (or low-k) dielectrics. Compared to aluminum, Copper metallization reduces interconnect propagation delays, reduces cross-talk, and enables higher interconnect current densities with extended electro migration lifetime. When combined with low-k dielectrics, copper metallization can also decrease the number of metallization levels, resulting in reduced chip manufacturing costs. For instance, the superior electro migration performance and lower resistivity of copper compared to aluminum, permits a reduction in metal stack height that results in reduced signal cross-talk and improved interconnect speed.
[0005] A number of deposition methods, such as chemical-vapor deposition (CVD), physical-vapor deposition (PVD), and electrochemical deposition (ECD) or plating can be used for deposition of uniform thin-film copper layers. Chemical-vapor deposition, in particular, provides a number of advantages over other deposition techniques, including the capability for fully vacuum cluster integrated deposition of the diffusion barrier and copper layers through cluster tool equipment. Metal-organic CVD (MOCVD) is a particularly desirable means for deposition of copper due to its excellent gap-fill characteristics, such as is desirable for high-aspect ratio via holes and trenches, its excellent step coverage, its compatibility with single/dual damascene processing, and its relatively low thermal budget, such as less than 250° C. deposition process temperature, which helps ensure compatibility with low-k polymer dielectrics. Due to these advantages, as device dimensions shrink, MOCVD technology is likely to replace other deposition techniques as the preferred solution for deposition of uniform high-conductivity copper layers.
[0006] Although copper provides a number of advantages for microelectronic semiconductor chip performance, significant difficulties exist in depositing and reliably integrating copper layers on a substrate. One difficulty relates to rapid diffusion of copper atoms through many materials, including both metals and dielectrics. Copper tends to diffuse through device materials during the thermal cycling that a semiconductor substrate experiences during the multi-level interconnect fabrication process flow, as well as during actual chip operation under applied electric fields. Copper diffusion into and/or through the inter-metal dielectric (IMD) results in current leakage between adjacent metal lines, known as line-to-line leakage. Copper diffusion through the IMD and pre-metal dielectric (PMD) or inter-level dielectric (ILD) and into the transistor regions results in degraded device characteristics such as accelerated aging and, potentially, non-functional transistor and chips.
[0007] Another difficulty associated with copper in microelectronic device fabrication, such as semiconductor IC fabrication, is the sufficient adhesion of the copper to the underlying barrier to prevent copper delamination during subsequent chemical-mechanical polishing (CMP). Moreover, copper is prone to corrosion and must be passivated. Non-conducting diffusion barriers, such as Si3N4, are ideal for passivation and prevention of copper diffusion between metallization layers. However, for many applications, a conducting barrier is necessary. For instance, a conducting barrier is necessary to enable electrical current flow between via plugs and lower level metal lines. To reduce copper diffusion and corrosion, a number of advanced diffusion barriers have been developed to supplant traditional barriers used with aluminum and tungsten metallization, such as TiN and TiW barriers. For instance, some barrier materials proposed for use with copper metallization include Ta, TaN, WNx, and ternary barrier materials such as TiSiN, TaSiN, WSiN, and WBN. Although these barriers improve reliability of copper metallization in microelectronic devices, these conventional barriers have some significant difficulties including poor adhesion with as deposited copper and sometimes with other adjacent layers, such as low-K dielectrics.
[0008] Other potential problems associated with copper metallization include difficulties associated with the deposition process for depositing copper and barrier layers onto the substrate. The deposition of a barrier layer using conventional barrier materials and deposition techniques may have difficulty achieving a good nucleation surface to promote <111> texture in an overlying copper layer for improved electro migration lifetime, and good step coverage in high-aspect-ratio features so that barrier thickness on the sidewall and bottom of trenches and via holes is comparable to barrier thickness in the field. In addition, conventional barrier materials and deposition techniques tend to have increased resistivity, especially as deposition temperatures are lowered to below 380° C.
[0009] The adhesion and uniform nucleation of CVD Cu on commonly used PVD and CVD barriers is problematic. Organometallic precursors used for CVD Cu tend to prematurely decompose on the barrier surface at the initiation of the deposition, which results in non-uniform nucleation with long nucleation delays as well as poor adhesion. This problem is exacerbated as the CVD Cu thickness is scaled to 100-250 Å. For applications as a seed layer for subsequent electroplating, the CVD Cu thickness cannot exceed 15-20% of the feature size to be electroplated. For example, 0.1 m structures correspond to 150-200 Å CVD Cu thin film. For such thin seed films, long and variable nucleation delays (typically 30-60 s) lead to poor process repeatability as well as to discontinuous films within the high aspect ratio features. Adhesion of these films to the underlying barrier is also marginal leading to adhesion failure during electroplating or subsequent CMP process steps used to form the inlaid metal line and via plugs.
Summary of the Invention
[0010] Therefore, a need has arisen for a barrier material and method for deposition of the barrier which reduces or suppresses copper diffusion through device layers.
[0011] A further need exists for a barrier material and method of deposition that improves adhesion of metallization layers, including adhesion of the barrier to underlying layers and adhesion of copper metallization to the barrier layer.
[0012] A further need exists for a barrier material and method of deposition that provides low resistance of the barrier layer to electrical current flow.
[0013] A further need exists for a barrier material and method of deposition that provides improved step coverage of microelectronic device features, such as a semiconductor chip interconnect structure, having high-aspect-ratio features.
[0014] A further need exists for a barrier material and method of deposition that supports deposition of low resistivity films at relatively low deposition temperatures.
[0015] A further need exists for a barrier material and method of deposition that reduces or eliminates copper corrosion.
[0016] In accordance with the present invention, a barrier material and method for deposition of the barrier are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed diffusion barriers and methods of deposition. The barrier material comprises a known material such as TaN, TiN, or WNx. Moreover, the barrier may comprise one or more metallic dopants selected from the group consisting of cobalt, ruthenium, platinum, palladium, iridium, rhodium, and tin. As indicated, the dopant can be combined with at least one refractory metal selected from the group consisting of tantalum, tungsten, titanium and chromium, and can also be combined with at least one element selected from the group consisting of carbon, oxygen and nitrogen. A variety of combinations of the dopant or several dopants can be used to address particular difficulties or process integration requirements associated with various device structures. Additionally, a simple binary barrier material such as TaN may also be realized by the present invention. The MOCVD technique for incorporation of the dopant provides a uniform thin film layer with good step coverage and nucleation surface. Co-deposition of the dopant with other materials at varied deposition rates allows manipulation of barrier material characteristics throughout the thickness of the barrier layer, allowing the dopant to have varying concentrations relative to other barrier materials at the barrier interface with overlying and underlying layers by depositing graded composition barrier layers.
[0017] In accordance with another aspect of the invention, a semiconductor integrated circuit interconnect structure formed on a substrate is disclosed. The interconnect structure comprises a conductive layer comprised of a metallic material and a barrier layer coupled to the substrate, the barrier layer including an adhesion region comprising a refractory metal, the adhesion region promoting adhesion of the conductive layer to the barrier layer.
[0018] In accordance with another aspect of the present invention, a method for forming a microelectronic interconnect structure on a substrate is provided. The method includes depositing a conductive layer and depositing a barrier layer, the barrier layer including an adhesion region coupled to the conductive layer. The adhesion region includes a refractory metal doped with an adhesion promotion material such as cobalt or ruthenium.
[0019] A further aspect of the invention provides a microelectronic semiconductor interconnect structure formed on a substrate. The interconnect structure includes a metal layer having copper and a barrier layer comprising a barrier material. The barrier material includes an adhesion region comprised of cobalt, ruthenium, cobalt alloy, of ruthenium alloy material for promoting adhesion between the copper layer and the barrier layer.
[0020] The present invention provides a number of important technical advantages. One important technical advantage is the reduced diffusion of copper through the barrier material, due to the thermal budget of the fabrication processes associated with the multi-level interconnect formation and during actual device operation under applied electric fields and possible thermal stress conditions.
[0021] Another important technical advantage is thermal stability so that the barrier material remains inert during processing. Another advantage that deposition temperatures can be reduced for compatibility with low-k dielectrics, typically having deposition temperatures of below approximately 375° C.
[0022] Another important technical advantage is good adhesion of the barrier material to the underlying surface as well as to the copper layer deposited over the barrier, such that the structured integrity of the interconnect structure is preserved through the device fabrication process flow and during device operation.
[0023] Another important technical advantage is good nucleation surface to promote <111> texture in the copper layer deposited on the surface, resulting in improved electro migration reliability lifetime.
[0024] Another important technical advantage is low electrical resistivity, such as 500.cm, and contact/interface resistance to the underlying metal, such as copper, so that low via plug resistance, such as R 1.5, can be achieved.
[0025] Another important technical advantage is good step coverage of the barrier material in high-aspect-ratio interconnect features so that barrier thickness on sidewall and bottom surfaces is comparable to barrier thickness in the field, allowing extendibility in terms of barrier thickness scaling.
Brief Description of the Drawings
[0026] A more complete understanding of the present invention and advantages thereof may be acquired by referring to the following description, taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:
[0027] FIG. 1A depicts a side cutaway view of a microelectronic device having high-aspect-ratio features;
[0028] FIG. 1B depicts a side cutaway view of a microelectronic device having high-aspect-ratio features with a diffusion barrier material layer;
[0029] FIG. 1C depicts a side cutaway view of a microelectronic device having high-aspect-ratio features with copper deposited on the barrier layer within the features; and
[0030] FIG. 2 depicts a side cutaway view of a barrier layer having a cobalt, ruthenium, or platinum dopant with increasing dopant density at the overlying interconnect interface compared to the underlying substrate interface.
Detailed Description of the Invention
[0031] Preferred embodiments of the present invention are illustrated in the FIGUREs, like numerals being used to refer to like and corresponding parts of the various drawings.
[0032] Chemical-vapor deposition (CVD) of barrier materials provides a uniform film with a high degree of conformality and good step coverage, as is needed to support device dimensions that continue to shrink. However, conventional CVD techniques for deposition of copper films frequently fail to meet manufacturing standards due to poor adhesion of the copper layer to the underlying barrier film such as to TaN. Further, conventional CVD deposition techniques of barrier films result in relatively high electrical resistivity (e.g., 2000.cm) films as the deposition temperature is reduced to below 380° C. for compatibility with some organic low-K dielectrics. Thus, barrier deposition processes are needed to enable copper metallization both in terms of providing good adhesion for the copper film and allowing lower temperatures for deposition for reduced thermal budget processing without increased resistivity.
[0033] Referring now to FIG. 1A, a device 10 formed on a substrate layer 12 having an oxide or dielectric portion 14 and a copper portion 16. Device 10 includes a high-aspect-ratio feature 18 etched in oxide or dielectric layers 20. Oxide or dielectric layers 20 are separated by etch stop layers 22, and have photo resist layers 24 patterned on the upper most oxide layer 20. Device 10 is prepared for the second etch treatment of a dual damascene fabrication technique.
[0034] Device 10 of FIG. 1A is treated to etch top oxide layer 20, resulting in the formation of a via hole formation 18 depicted by FIG. 1B. A barrier layer 26 is then deposited on device 10. Deposition of barrier layer 26 using CVD or MOCVD provides uniform layer thicknesses along the side wall and bottom of feature 18 to isolate oxide layers 20. Device 10 is then in a condition to accept deposition of copper to fill feature 18. FIG. 1C depicts copper 28 deposited within feature 18 following CMP. Barrier layer 26 separates the underlying substrate 12 and oxide layers 20 from the overlying copper layer 28 to prevent diffusion of copper layer 28 into substrate 12 and oxide layers 20. If copper layer 28 were allowed to directly contact oxide within any oxide layer 20, this could result in device performance and reliability degradation as copper diffused through the oxide layer 20. However, if barrier layer 26 is conducting with minimal resistivity, current can be conducted between copper layer 16 of substrate 12 and the deposited copper layer 28 with minimal voltage drop. Once copper layer 28 is deposited, chemical-mechanical polishing (CMP) is used to smooth the upper surface of device 10. Although FIG. 1C depicts a copper layer 28 as deposited on barrier 26, it is important to note that the present invention provides a barrier to separate or encapsulate other conventional metallization material layers, such as aluminum and tungsten.
[0035] Copper metallization presents particular difficulties in terms of maintaining effective separation of copper material from a substrate or other underlying dielectric material. Non-conducting barriers based on oxide or nitride insulators, such as silicon nitride Si3N4, provide passivation and prevent copper diffusion due to their amorphous structures. However, most barrier applications for microelectronic devices require a conducting barrier. Electrically conducting barriers that include silicon, such as TiSiN, TaSiN and WSiN, or that include boron, such as WBN, can succeed at limiting copper diffusion but have relatively high resistivity values (e.g., P 1000.cm). Further, such barriers are generally deposited by physical-vapor deposition (PVD), limiting the step coverage and conformality available for these barriers and reducing their practicality as device dimensions shrink. In addition, the resistivity of CVD barriers increases to higher levels as the deposition temperature decreases below 380° C. for compatibility with certain low-K dielectrics. Also, these barriers generally have poor adhesion, limiting their usefulness, especially when chemical-mechanical polishing (CMP) is needed for device fabrication, such as in single-damascene or dual-damascene copper metallization processes.
[0036] To obtain good adhesion and reduced deposition temperature, and, in some applications, to reduce the barrier resistivity, the present invention uses one or more dopants selected from the group of platinum, palladium, iridium, rhodium, and tin to dope barrier layer 26 and tailor barrier properties for copper metallization. Some dopants can render the barrier amorphous or nano-crystalline by disrupting the crystalline structure of other materials in the barrier, such as refractory metals selected from the group of tungsten, titanium, tantalum, chromium and cobalt. For example, the alloys Co91ZrTa and Co91ZrNb are amorphous even though Co is polycrystalline in its pure form. Other nitridizing, oxidizing, or carbonizing elements selected from the group of nitrogen, oxygen and carbon can also be included in the barrier, either as an intentional controlled addition to obtain desired barrier properties or as impurities resulting from the deposition process, particularly CVD processes.
[0037] Doping the barrier with an appropriate dopant element provides a number of advantages. For instance, a suitable dopant, such as cobalt or ruthenium or platinum, enhances nucleation and adhesion of copper to enable MOCVD deposition of an overlying copper film. A suitable dopant, such as cobalt or ruthenium or platinum, also reduces resistivity of the barrier, such as MOCVD TaN layers, particularly with CVD deposited barriers. Low barrier resistance, such as less than 500.cm provide desirable low via plug resistance (e.g., R 2). Further, by rendering the barrier amorphous or nano-crystalline through disruption of the crystalline structure, the dopant provides passivation and prevents metallic diffusion between metallization layers.
[0038] Cobalt and ruthenium are examples of dopants, the addition of which to a barrier, such as MOCVD TaN, decreases the resistivity at low deposition temperatures. Cobalt and ruthenium have low diffusivity in tantalum, provides a good nucleation surface for CVD copper deposition, and improves adhesion of as-deposited MOCVD copper to the barrier for reliable chemical-mechanical polishing (CMP).
[0039] Cobalt and ruthenium enhance adhesion of copper to a barrier by reducing interfacial contamination formed during initiation of CVD copper. Copper deposition with Cu(I) precursors such as Cupraselect (Cu-hfac-tmvs) supplied by Schumacher, proceeds through adsorption of the precursor and subsequent disproportionation reaction. A parallel reaction pathway is adsorption and ligand (hfac) decomposition, resulting in interfacial contamination at the barrier/copper interface. The rate of ligand decomposition depends upon the nature of the barrier surface accepting the initial copper film. Both copper and cobalt surfaces adsorb the hfac ligand in a “standing up” mode with the hfac skeleton normal to the substrate surface. On other materials, the hfac ligand is adsorbed in a lying down mode that decomposes at 190K, compared with decomposition at 350K for standing up ligand on copper and 300K on cobalt. Uniform nucleation and adhesion occur on both copper and cobalt because the rate for disproportionation exceeds the rate for ligand decomposition. In other words, the precursor has reacted via disproportionation before ligand decomposition and interface contamination can occur. With most materials other than copper and cobalt, the threshold temperature for ligand decomposition is much lower, and the rate of ligand decomposition exceeds the rate of disproportionation leading to interface contamination at the barrier/copper interface. Cobalt containing alloys, such as Co80Pt20, Co82Cr8Pt10, and Co75Cr13Pt12also provide good adhesion for a subsequent copper metal layer, suggesting that cobalt contained in a material matrix can actually be at least as effective as a continuous platinum layer. Thus, doping of conventional barrier materials such as TaN, TiN and WN with cobalt can enhance the barrier properties provided through resistivity reduction and enhancement of MOCVD copper adhesion.
[0040] One conventional method for CVD of a barrier layer is thermal decomposition/thermolysis of a metal-containing precursor in an inert (Ar, He) or reducing (NH3, H2) ambient. Such deposition typically results in some level of carbon incorporation in the barrier material since many of the reaction byproducts have low volatility when metal-organic precursors are used. Carbon incorporation can lead to high barrier resistivity and sometimes unstable time-dependent barrier properties, and is generally reduced by post-deposition treatment, such as plasma treatment or thermal annealing, to remove the most volatile constituents and densify the barrier film.
[0041] One method for reducing carbon incorporation into the barrier is co-deposition of the barrier precursor and a cobalt-containing precursor in an H2 or ammonia ambient. Cobalt or platinum has catalytic qualities to encourage the hydrogenation of barrier precursor ligands to their volatile forms, leading to a cobalt-doped or platinum-doped barrier with low carbon content and deposition temperature reduction (e.g., between 10° and 30° C. for platinum). The lower deposition temperatures associated with a platinum dopant better enable integration of low-k dielectrics and improvement in step coverage. Commercial grade platinum precursors, such as MeCpPtMe3 support easy disassociation of the Pt—C bond in an H2 ambient, increasing the purity of the deposited platinum and reducing the resistivity of the composite barrier, such as TaNPt. For cobalt, the CVD process may include Co(CO)3NO as a deposition precursor.
[0042] Referring now to FIG. 2, a cobalt-containing barrier layer 26 is depicted between an underlying substrate oxide layer 20 and an overlying copper layer 28. Barrier layer 26 has a graded composition through its thickness that contains a greater proportion of cobalt adjacent to copper layer 28 than is contained adjacent to oxide layer 20. For example, barrier layer 26 could consist of a TaCoN barrier that is more cobalt rich adjacent to the copper layer to provide a good nucleation and adhesion surface for copper deposition, and that is cobalt deficient, with reduced Co doping in the bulk of barrier layer 26 to retain optimal barrier properties. Varied concentrations of cobalt through the thickness of barrier layer 26 can be achieved through co-deposition of cobalt with barrier materials, such as TiN and TaN and WN, with the deposition rate of cobalt increasing as barrier 26 is deposited. Co-deposition techniques are discussed in greater detail in U.S. patent application Ser. No. 09/113,852, entitled “Method for Forming a Copper Film on a Substrate”, by Paranjpe et al., which is incorporated herein by reference.
[0043] Although cobalt provides many advantages as a dopant, other dopants and combinations of dopants can be used to optimize barrier qualities. In general, barriers according to the present invention can be represented by the formula: [R1][R2][X1][X2][Y1][Y2][Y3], where R represents a refractory metal selected from the group of tantalum, tungsten, titanium, and chromium; X represents a dopant selected from the group of cobalt, ruthenium, platinum, palladium, iridium, rhodium, and tin; and Y represents an element select from the group of nitrogen, oxygen and carbon. As a minimum, the barrier comprises at least one refractory metal and one dopant (e.g., TaCo). The barrier can also comprise between zero and two refractory metals, and between zero and three of the other elements from the Y group. The table below depicts a number of barrier materials according to the present invention, methods for deposition of the barrier and properties and some properties associated with each barrier material:
| Interconnect Barrier Material | ||
|---|---|---|
| ID | (Deposition Methods) | Properties and Impact |
[0044] Following the deposition, the barrier surface may be treated, such as by thermal annealing or plasma treatment, to selectively passivate some of the surface elements. For example, for a TaCo barrier, a thermal or plasma oxidation following deposition will passivate the Ta. Thus, the barrier surface would behave more as a Co surface than a TaCo surface with respect to subsequent metallization. This advantageously enhances adhesion, particularly for copper overlayers.
[0045] Barrier layer 26 may also be configured using other types of metal for providing good adhesion of copper overlays. For example, cobalt-containing barrier 26 of FIG. 2 may be configured as a cobalt, cobalt alloy, ruthenium, or ruthenium alloy layer.
[0046] Barrier layer 26 may be deposited using conventional methods such as chemical vapor deposition (CVD)or physical vapor deposition (PVD) to a predetermined thickness. In one embodiment, barrier layer 26 may include TaN, TiN, WNx or other materials for creating barrier layers configured to provide conductivity while maintaining a diffusion barrier. Adhesion region 29 of barrier layer 26 is preferably made of cobalt or cobalt based alloys and promotes excellent adhesion and uniform nucleation of copper layer 28 during a deposition process. For example, adhesion region 29 may be comprised of 50 Å of cobalt or cobalt alloys to allow reduced nucleation delay times of less than 30 seconds during deposition of 100 to 250 Å of copper to create copper layer 28.
[0047] In one embodiment, adhesion region 29 may have a graded composition through its thickness thereby providing greater proportion of cobalt adjacent to copper layer 28 than is adjacent to barrier layer 26. For example, adhesion region 29 may be more cobalt rich adjacent to copper layer 28 to provide a good nucleation and adhesion surface for copper deposition. Varied concentrations of cobalt within adhesion region 29 provide a graded composition that can be achieved through co-deposition of adhesion region 29 with barrier layer 26. For example, an adhesion region comprised of cobalt may be co-deposited with a barrier layer comprised of TiN and TaN and WN. A variance in the rate of deposition and concentration of materials used during the deposition process can provide desirable concentration levels of materials between the copper layer and barrier layer 26. Co-deposition techniques are discussed in greater detail in U.S. patent application Ser. No. 09/113,852, entitled “Method for Forming a Copper Film on a Substrate”, by Paranjpe et al., which is incorporated herein by reference.
[0048] In one embodiment of the present invention a method of fabricating an interconnect having a barrier layer with an adhesion region is disclosed. The method includes depositing barrier layer 26 using a physical vapor deposition technique to a predetermined thickness. Physical vapor deposition of barriers include depositing TaSiN, TiSiN, WSiN, etc. Upon depositing barrier layer 26, adhesion region 29 may be deposited using a chemical vapor deposition process or a PVD process. Copper may then be deposited using a CVD copper process. In a preferred embodiment, a metalorganic chemical vapor deposition process (MOCVD) that includes utilizing organometallic liquid precursors is used for the copper deposition.
[0049] The CVD copper deposition process is performed using a MOCVD copper chamber having a warm wall stainless steel chamber regulated at a temperature of preferably 50° C. to 70° C. Reactants are introduced through a temperature controlled multi-zone or single-zone showerhead and the substrate is positioned on a heated chuck with the chuck having a backside He gas flow. The substrate is clamped to ensure good thermal contact and uniform substrate temperature. A turbo molecular pump provides a good base pressure while a dry pump is used to pump process gases during the process. The chamber is pumped down to 10−6Torr prior to deposition using a turbo molecular pump and a roughing pump is used during the deposition process.
[0050] The MOCVD process utilizes organometallic liquid precursors with helium serving as the carrier/diluent gas. A liquid precursor is delivered via a single channel liquid delivery system. In one embodiment, an S-100 precursor is used and includes a shortened nucleation delay. For example, a nucleation delay of less than 30 seconds can be used for the deposition process. A substrate is loaded into a CVD Cu module and exposed to a 10 second burst of precursor diluted in a carrier gas. Alternatively, the wafer may be allowed to soak in a dilute precursor containing ambient prior to, during, or following heating the wafer. The process proceeds by providing a backside gas to the backside of the substrate and heating the substrate for seventy seconds in the dilute precursor containing ambient. The process proceeds by providing a precursor/carrier flow introduced for a 30-120 second deposition period.
[0051] The deposition process conditions include: 0.15 cc/min S-100, 100 sccm carrier He, 200 sccm purge He, 10 sccm backside He, 0.75 Torr chamber pressure, 180° C./212° C. chuck temperature (substrate temperature of ˜175° C.), 0.2″ showerhead to substrate spacing, and ATMI vaporizer temperature of 80° C. In addition, 10 sccm of wet He (generated by flowing 10 sccm of He through a water containing bubbler maintained at room temperature and 30 psig) is added during the 10 second precursor burst step as well as during the main deposition step.
[0052] In an alternate embodiment, a Cupraselect precursor may be used during the deposition process. Cupraselect is deposited using a CVD copper process having deposition conditions that include: 0.4 cc/min Cupraselect, 100 sccm carrier He, 200 sccm purge He, 15 sccm backside He, 0.75 Torr, 205° C./240° C. chuck temperature (wafer temperature of ˜200° C.), 0.2″ showerhead to wafer spacing, and ATMI vaporizer temperature of 64° C. In one embodiment, using CUPRASELECT allows for a wide temperature range of up to 165° C./195° C. for CVD deposited copper.
[0053] In an alternate embodiment, a CVD copper layer is deposited onto a PVD deposited adhesion region comprised of Co or cobalt alloys such as Co90Zr5Ta5and Co82Cr6Pt12. The cobalt based adhesion region 29 may be deposited during a PVD process. A nucleation delay of less than ninety seconds is used for 50 Å PVD Co. In one embodiment, barrier layer 26 and the cobalt based adhesion region 29 may be co-deposited within the same PVD process. The process proceeds by creating a copper layer 28 using a CVD copper process as described above. In this manner a PVD process for depositing a barrier layer having an adhesion region comprised of cobalt may be used in conjunction with a CVD process for depositing copper thereby providing a continuous, adherent interconnect structure.
[0054] The above process results in CVD Cu films with Rsranging from 2/sq to 5/sq for 250-150 Å CVD Cu deposited on 50 Å PVD Co. The 150-250 Å CVD Cu region may be further electroplated providing continuous CVD Cu film on PVD Co adhesion region. The resulting interconnect when exposed to a post-deposition anneal at 400° C. confirms that the resistivity of CVD Cu on PVD Co does not increase upon annealing. In other words, cobalt and copper do not inter-diffuse at elevated temperatures since the two elements are generally immiscible. Hence the low resistivity of copper is retained. In fact, a decrease in resistivity of CVD Cu on PVD Co may be observed.
[0055] In a preferred embodiment, an interconnect may be formed using an all CVD process for fabricating adhesion region 29, barrier layer 26, and a copper layer 28. Adhesion region 29 may be deposited in a CVD barrier module using a cobalt based precursor such as Co(Co)3NO. The CVD barrier module includes a warm-wall stainless steel chamber with wall temperature regulated at 40° C. Reactants are introduced through a temperature controlled multi-zone showerhead. A two-zone resistively heated chuck with backside Ar gas flow and substrate clamping ensures good thermal contact and uniform substrate temperature. A turbo molecular pump is used for achieving good base pressure while a dry pump is used to pump the process gases during the process. The chamber was pumped down to 10−6Torr prior to the deposition using the turbo molecular pump. The cobalt precursor is sublimed in a bubbler (held at 0° C.) and metered by a vapor source MFC. Excess H2is used as the diluent gas. The deposition process conditions for the cobalt based adhesion region process may include: 1 sccm Co(CO)3NO, ˜500 sccm diluent H2, 15 sccm backside Ar, 1-2 Torr and 410° C. wafer temperature.
[0056] In an alternate embodiment, a CVD process may be used to co-deposit barrier layer 26 and adhesion region 29. Adhesion region 29 may have a graded composition through its thickness having a profile with a greater proportion of cobalt adjacent to copper layer 28 than is adjacent to adhesion region 29. For example, adhesion region 29 may be more cobalt rich adjacent to the metal layer to provide a good nucleation and adhesion surface for a metal deposition, with reduced cobalt doping at adhesion region 29 to retain optimal barrier properties. Varied concentrations of cobalt within adhesion region 29 provide a gradient that can be achieved through co-deposition of adhesion region 29 with adhesion region 29 during the CVD process. For example, an adhesion region comprised of cobalt may be co-deposited with a adhesion region comprised of TiN, TaN, or WN. A variance in the rate of deposition and concentration of materials used during the deposition process can provide gradients between the metal layer and the adhesion region.
[0057] In another embodiment, a CVD process may be provided to co-deposit an adhesion region 29 of cobalt and a copper layer 28. Adhesion region 29 and/or copper layer 28 may have a graded composition through its thickness having a profile with a greater proportion of cobalt adjacent to copper layer 28 than is adjacent to adhesion region 29. For example, adhesion region 29 may be more cobalt rich adjacent to the metal layer to provide a good nucleation and adhesion surface for a copper deposition.
[0058] Therefore, the disclosed all CVD process for fabricating of copper interconnect provides good adhesion of a metal layer, such as copper, to an adhesion region, such as cobalt or cobalt-based alloys. Additionally, a CVD based adhesion layer adheres well to underlayers comprised of SiO2and CVD barriers.
[0059] In a preferred embodiment, a thin adhesion region comprising cobalt (<50 Å) may be provided as an adhesion region for a CVD Cu layer. In one embodiment, CVD Co may be deposited in the CVD barrier module or in another embodiment CVD Co may be deposited in a CVD Cu module, thereby providing a thin adhesion region of cobalt deposited in a CVD module between a CVD barrier and CVD Cu layer. The cobalt adhesion layer may also be provided using a separate CVD cluster module.
[0060] Additionally, the process conditions for CVD Co are compatible with those of TaN when Co(CO)3NO is used as the precursor, it is possible to co-deposit CVD Co with the barrier to eliminate the CVD barrier/CVD Co interface. Analogously, since the process conditions for CVD Co are compatible with those of CVD Cu when Co2(CO)8is used as the precursor, it is possible to co-deposit CVD Co with CVD Cu to eliminate the CVD Co/CVD Cu interface. This method is extendible to other elements/alloys (e.g. Pt and Fe based materials) that also share the desired characteristics for glue/nucleation layers. Other precursors for Co can also be used such as CpCo(CO)2.NH3can be used as a reducing gas together with or in place of H2.
[0061] Ruthenium and ruthenium-based alloys may also be used as an adhesion region. A method to simultaneously achieve 150-250 Å continuous, conformal and well adherent CVD Cu to CVD barriers using an ultra-thin (<50 Å) glue/nucleation layer of CVD Ru (or Ru based alloys) is disclosed. The CVD Ru may be deposited in a barrier module or prior to CVD Cu in a CVD Cu module. Alternatively CVD Ru may be co-deposited either with the CVD barrier in the CVD barrier module or the CVD ruthenium may be co-deposited with the CVD Cu in the CVD Cu module. Therefore, the present invention enables an all CVD approach for ruthenium, ruthenium alloy, cobalt, or cobalt alloy adhesion regions for copper based interconnects.
[0062] In one embodiment of the present invention, CVD deposited cobalt or ruthenium may be desirable over PVD processes for promoting adhesion of copper. Impurity levels associated with CVD processes may promote the adhesion of copper. For example, a CUPRASELECT CVD Cu to CVD Co process having an increased level of impurities promotes adhesion of the CVD copper. Impurities such as C, O, and H associated with a CVD Cu process aid in promoting adhesion of copper to an adhesion region comprised of cobalt, cobalt alloys, ruthenium, or ruthenium alloys and may be desirable in predetermined amounts for providing conformal and adherent microelectronic interconnect structures comprised of copper.
[0063] Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
What is claimed is:
1. A method for fabrication of a microelectronic device on a substrate, the method comprising:
depositing a barrier layer on the substrate, the barrier layer operable to limit diffusion of copper to the substrate;
depositing a cobalt layer over the barrier layer; and
depositing a copper layer over the cobalt layer, the copper layer deposited with a chemical vapor deposition precursor.
2. The method of claim 1 wherein depositing a copper layer further comprises depositing the copper layer with a metal-organic precursor.
3. The method of claim 2 wherein depositing the cobalt layer further comprises depositing the cobalt layer with a chemical vapor deposition precursor.
4. The method of claim 3 wherein the cobalt chemical vapor deposition precursor comprises Co(CO)3NO.
5. The method of claim 3 wherein the cobalt chemical vapor deposition precursor comprises Co2(CO)8.
6. The method claim 3 wherein depositing the barrier layer further comprises depositing the barrier layer with a chemical vapor deposition precursor.
7. The method of claim 6 further comprising:
co-depositing the barrier layer and the cobalt layer by flowing the cobalt precursor with the barrier precursor and then ending the barrier precursor flow.
8. The method of claim 7 wherein the barrier layer comprises TaN and the cobalt precursor comprises Co(CO)3NO.
9. The method of claim 8 further comprising:
co-depositing the cobalt layer and the copper layer by flowing the copper precursor with the cobalt precursor and then ending the cobalt precursor flow.
10. The method of claim 9 wherein the cobalt precursor comprises Co2(CO)8.
11. The method of claim 6 further comprising:
co-depositing the cobalt layer and the copper layer by flowing the copper precursor with the cobalt precursor and then ending the cobalt precursor flow.
12. The method of claim 9 wherein the cobalt precursor comprises Co2(CO)8.
13. The method of claim 2 wherein the microelectronic device comprises an integrated circuit interconnect structure.
14. A method for fabricating an electronic device on a semiconductor substrate, the electronic device having a conductive copper structure, the method comprising:
flowing a barrier precursor over the substrate to deposit a barrier material on the substrate, the barrier material reducing diffusion of copper into the substrate;
flowing a cobalt precursor over the substrate to deposit cobalt on the barrier material; and
flowing a copper precursor over the substrate to deposit copper on the cobalt.
15. The method of claim 14 further comprising:
overlapping the flows of the barrier precursor and the cobalt precursor to deposit a graded composition of barrier material and cobalt between the barrier material and the cobalt material.
16. The method of claim 15 further comprising:
overlapping the flows of the cobalt precursor and the copper precursor to deposit a graded composition of cobalt and copper between the cobalt material and the copper material.
17. The method of claim 14 further comprising:
overlapping the flows of the cobalt precursor and the copper precursor to deposit a graded composition of cobalt and copper between the cobalt material and the copper material.
18. The method of claim 17 further comprising:
overlapping the flows of the barrier precursor and the cobalt precursor to deposit a graded composition of barrier material and cobalt between the barrier material and the cobalt material;
wherein the cobalt precursor comprises a first precursor for overlapping with the barrier precursor and a second precursor for overlapping with the copper precursor.
19. The method of claim 18 wherein the barrier material comprises TaN, the first cobalt precursor comprises Co(CO)3NO and the second cobalt precursor comprises Co2(CO)8.
20. The method of claim 19 wherein the copper precursor comprises a metal-organic precursor.
21. The method of claim 14 wherein the electronic device comprises an integrated circuit.
22. The method of claim 21 wherein the structure comprises a copper interconnect.
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