System and method for improving LBIST test coverage

[0002] 1. Field of the Invention

[0003] The present invention relates generally to built-in self-testing of logic (LBIST), and more particularly, to an apparatus and a method for improving observability and maintaining the validity of test coverage for a scan design in an integrated circuit environment.

[0004] 2. Relevant Technology

[0005] Many Integrated Circuit (IC) logic circuit designs commonly include decoder outputs in electrical communication with state elements, such as latches or flip-flops. The state elements of the IC may in turn be in electrical communication with the select lines of a passgate multiplexer. Logic Circuit designs may employ a full scan design that advantageously provides controllability and observability of the internal logic in a circuit. For circuit designs that employ scanning, the state elements are usually scannable.

[0006] Built-in self testing of logic (LBIST) is a signature-based test methodology which depends on deterministic results. At any given time during the test, the test responses must be known and are compressed into a special structure such as a multiple input shift register (MISR) to produce a unique signature. A problem with LBIST is that a full scan may be unsafe for non-random state elements. During a full scan, scannable state elements receive random data from a pseudo random pattern generator (PRPG). However, in some circuit designs, certain state elements (non-random state elements) cannot tolerate random data and will not provide valid values.

[0007] One solution to scanning circuits having one or more non-random state elements is to operate a partial scan for the circuit. In a partial scan, the PRPG provides random data to the state elements except for the non-random state elements. This avoids the above noted problems, but converting a portion of the circuit into a non-scan mode during a LBIST may prove detrimental. This is because some intermediate stages having non-random state elements lack controllability and observability, which results in poor test coverage.

[0008] A further concern during a LBIST is the validity of the bit values supplied to passgate or transmission gate multiplexers. During general circuit operation, a circuit design with a multiplexer operates according to rules that ensure that the select lines of the multiplexer are always orthogonal, i.e., only one of the select lines is on. However, under test conditions, e.g., during a LBIST, the select lines may be driven by scannable state elements that receive random data that no longer abides by the orthogonal rule.

[0009] Another concern during LBIST arises from the fact that scannable state elements in the functional paths may receive random data that results in invalid outputs. For high performance in circuit design, the complex operation of decoding a wide bus during normal circuit operation may be carried over a number of clock cycles. When a full scan design is employed, partially decoded bit values are stored in the scannable state elements. Under system operation, this configuration works satisfactorily since the above scenario can be described as a functional path. However, under test conditions such as a LBIST, the scannable state elements in the functional path receive random data which no longer abide rules. As a result, invalid input values may be introduced to logic devices and in particular, the last stage of the functional path may no longer produce the desired result such as an orthogonal result (1-hot or 1-cold). If the logic devices receiving output from the last stage of the pipeline are combinational, then this poses no problem. However, if the last stage of the pipeline outputs to a 1-hot multiplexer that requires one and only one select line to be on, then the 1-hot multiplexer output will be invalid, which may destroy the validity of the LBIST. For example, if no select lines are on (0-hot), the multiplexer output will be floating which results in a high current state that could be detrimental to integrated circuit reliability. Having multiple select lines on could cause contention that has a similar effect to the 0-hot case.

[0010] It would therefore be an advancement in the art to ensure a 1-hot condition during LBIST for a multi-cycle decoded 1-hot multiplexor. Ensuring a 1-hot condition would avoid problems associated with an unknown value and provide validity of the LBIST. It would be another advancement in the art to improve the observability of intermediate stages in a partial scan environment. It would further be an advancement in the art to achieve the foregoing while maintaining the validity of the LBIST where scannable state elements that cannot tolerate random values are involved.

[0011] The present invention is generally directed to providing a pseudo partial scan design that operates as a full scan design and behaves like a partial scan design under particular test environments. A preferred embodiment of the present invention is embodied as a system that receives valid test responses from scan chains during a self-testing of Logic (LBIST). As referenced herein, a scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a “LBIST Non-random Scan Chain” (LNSC).

[0012] A preferred embodiment of the system includes a psuedo-random pattern generator (PRPG) to generate random data signals having a plurality of bit values. The PRPG feeds the random data signals and bit values into one or more LRSCs having one or more scan registers. After passing the bit values through the LRSC, the LRSC feeds the bit values into the MISR. The system further includes one or more LNSCs having one or more scan registers that cannot tolerate random data. The LNSCs do not receive bit values from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and decoded. Thereafter, the LNSCs feed bit values into the MISR. The system may further include recirculation lines in electrical communication with LNSCs to recirculate original bit values back into the LNSCs. In an embodiment, the system further includes a 1-hot multiplexer having an input line that is in electrical communication with a scan register of a scan chain. The scan register that feeds the input line of the 1-hot multiplexer may be embodied as a series of successive state elements and inverters to ensure the 1-hot condition for the input line. An output line of the 1-hot multiplexer may be in electrical communication with a scan chain, such as a LRSC.

[0013] A preferred embodiment of the system may be described as having a scan path and a functional path. The scan path includes the PRPG, a scan chain (LRSC or LNSC), and the MISR. The functional path includes one or more scan registers, one or more decoders, the 1-hot multiplexer, and output functional logic.

[0014] In a preferred embodiment the system initializes the state elements within the scan registers of the LRSCs and the LNSCs. This performs a scan flush to initialize the state elements to a zero state. Prior to running the LBIST, the system may further temporarily disable clock input to state elements in the LRSC. The system may then perform a certain number of clock cycles to input partially decoded values into the state elements of the functional path. The process may then begin the LBIST process and feed random data to the LRSCs. Bit values are also decoded and feed into the LNSCs and then recirculated back into the LNSCs. Bit values outputted from the scan chains reflect test responses and are feed into the MISR which produces a signature. Bit values are further passed along the functional path into the 1-hot multiplexer.

[0015] The initialization process and structure of the system ensures that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the LNSCs while allowing the LNSCs to feed the MISR.

[0016] These and other features, and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

[0017] In order that the manner in which the above-recited and other advantages and features of the invention are obtained, a more particular description of the invention summarized above will be rendered by reference to the appended drawings. Understanding that these drawings only provide selected embodiments of the invention and are not therefore to be considered limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0018] FIG. 1 is a schematic diagram of one embodiment of a system for built-in self-testing of logic (LBIST) in accordance with the present invention;

[0019] FIG. 2 is a schematic diagram of an alternative embodiment of the system of FIG. 1;

[0020] FIG. 3 is a schematic diagram of one embodiment of a scan register in a LBIST circuit in accordance with the present invention; and

[0021] FIG. 4 is a flow diagram of a process for operation of a scan path with regard to a LBIST circuit in accordance with the present invention.

[0022] A preferred embodiment of the invention is now described with reference to the Figures, where like reference numbers indicate identical or functionally similar elements. The components of the present invention, as generally described and illustrated in the Figures, may be implemented in a wide variety of configurations. Thus, the following more detailed description of the embodiments of the system and method of the present invention, as represented in the Figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of presently preferred embodiments of the invention.

[0023] Referring to FIG. 1, a circuit diagram of a system 100 for improved test coverage during built in self-testing of logic (LBIST) is shown. For adequate test coverage during partial scan environments, the present invention provides a system for improving observability during LBIST. The system 100 includes a conventional pseudo-random pattern generator (PRPG) 102 that generates random data having a plurality of bit values. The PRPG 102 is in electrical communication with certain scan chains 108₁, 108₂to thereby feed the scan chains 108₁, 108₂random data. The scan chains 108₁, 110₁, 110₂, 108₂are generally illustrated in the vertical direction.

[0024] The scan chains 108₁, 110₁, 110₂, 108₂include one or more scan registers 106₁, 106₄; 106₂, 106₅, 106₇; 106₃, 106₆, 106₈; 106₉that may include one or more scannable state elements such as flip-flops or latches. The number of scan registers in each scan chain may vary depending on the design of the system 100. In a given system, certain scan registers are capable of receiving random data and others are not. As referenced herein, a scan chain 108₁, 108₂having only scan registers 106₁,106₄; 106₉that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) 108₁, 108₂. A scan chain 110₁, 110₂having one or more scan registers 106₂, 106₅, 106₇; 106₃, 106₆, 106₈that cannot tolerate and cannot receive random data is referred to as a “LBIST Non-random Scan Chain” (LNSC) 110₁, 110₂. The PRPG 110₂is only in direct electrical communication with the LRSCs 108₁, 108₂and does not provide random data to the LNSCs ,110₁, 110₂.

[0025] The system 100 may further include one or more decoders 112₁, 112₂which may be disposed in electrical communication between scan chains. As shown in FIG. 1, a decoder 112₁, 112₂may be disposed between scan registers (e.g. between 106₄and 106₅and between 106₅and 106₆) in separate scan chains 108₁, 110₁, 110₂. The decoders 112₁, 112₂may be embodied in various ways and, in one embodiment, may be an x-bit decoder such as a 2-bit decoder. The decoders 112₁, 112₂receive and decode bit values which are representative of the random data feed into a LRSC 108₁, 108₂. A very wide decode step may require a number of clock cycles. Thus, in a single clock cycle the decoders 112₁, 112₂partially decode bit values received from a scan register 106₄, 106₅. The system 100 further includes a conventional multiple input shift register (MISR) 114 that is in electrical communication with the LRSCs 108₁, 108₂and the LNSCs 110₁, 110₂. During the LBIST, the LRSCs 108₁, 108₂and the LNSCs 110₁, 110₂feed bit values reflecting test responses directly into the MISR 114. LBIST is a signature-based test methodology that depends on deterministic results. Thus, for a successful LBIST, the test responses must be known at any given time. The test responses are compressed into the MISR 114 which is based on a predefined polynomial to produce a unique signature.

[0026] The system 100 further includes a conventional multiple input shift register (MISR) 114 that is in electrical communication with the LRSCs 108₁, 108₂and the LNSCs 110₁, 110₂. During the LBIST, the LRSCs 108₁, 108₂and the LNSCs 110₁, 110₂feed bit values reflecting test responses directly into the MISR 114. LBIST is a signature-based test methodology that depends on deterministic results. Thus, for a successful LBIST, the test responses must be known at any given time. The test responses are compressed into the MISR 114 which is based on a predefined polynomial to produce a unique signature.

[0027] The system 100 may further include a 1-hot multiplexer 116 having multiple input lines 118. In one embodiment the 1-hot multiplexer 116 may be embodied as a 4-to-1 multiplexer and having an input from a scan register 106₆in a scan chain 110₂. The remaining input lines to the 1-hot mutliplexer 116 may be in electrical communication with functional logic 120. The functional logic 120 may be various forms of random or combinational logic on a microchip and may include logic latches or logic flip-flops. The 1-hot multiplexer further includes an output line 122 which is in electrical communication with output logic 124. The output logic may be embodied as random or combinational logic such as latches or flip-flops. The output logic 124 may be in electrical communication with a scan register 106₉in a scan chain 108₂that feeds test responses into the MISR 114.

[0028] The system 100 in FIG. 1 may be described as having a scan path and a functional path. The scan path is illustrated in the vertical direction and includes the PRPG 102, a scan chain 108₁, 108₂, 110₁, 110₂having one or more scan registers (e.g. 106₁and 106₄; 106₂, 106₅, and 106₇; 106₃, 106₆and 106₈; 106₉) and the MISR 114. The functional path is illustrated in the horizontal direction and, in one embodiment, includes one or more scan registers (e.g. 106₄, 106₅, 106₆) one or more decoders 112₁, 112₂, the 1-hot multiplexer 116, and the output functional logic 120.

[0029] As shown in FIG. 1, the PRPG 102 is in electrical communication with the LRSCs 108₁, 108₂to deliver random data to the one more scan registers 106₁and 106₄, 106₉within that chain. The number of LRSCs 108₁, 108₂in a system 100 may vary based on design choice and is not limited to the example of FIG. 1. A LRSC 108₁, 108₂may be placed in electrical communication through a decoder 112₁with a LNSC 110₁, 110₂to pass bit values. For example, the scan register 106₄may be placed in electrical communication with a decoder 112₁as illustrated. This scan register 106₄may transmit a bit value represented as a. In one embodiment, a scan register 106₄may couple with the decoder 112₁through an x-bit signal line such as a 2-bit signal line. The decoder 112₁performs a decode of bit value a to produce a bit value b. The bit value b is then fed into a scan register 106₅of the LNSC 110₁.

[0030] The LNSCs 110₁, 110₂are not in direct electrical communication with the PRPG 102 and therefore do not receive random data. Because the LNSCs 110₁, 110₂do not receive random data, there is no corruption by the non-random state elements and the bit value b remains valid. The observability of the intermediate non-scan stages is thereby improved. The bit value b may be feed into one or more subsequent scan registers 106₅, 106₇of the LNSC 110₁and is further passed to the MISR 114. The LNSCs 110₁, 110₂provide the MISR 114 with bit values to improve the test coverage of the intermediate bit values.

[0031] A LNSC may further be placed in electrical communication with another scan chain to pass bit values. In the example of FIG. 1, the bit value b is further feed into a second decoder 112₂in the functional chain. The second decoder 112₂performs a decode of the bit value b to produce a bit value n which is feed into a scan register 106₆of a subsequent LNSC 110₂. The bit value n may thereafter feed into subsequent scan registers 106₈of the LNSC 110₂and into the MISR 114.

[0032] At some point in the functional chain, bit values are passed to the 1-hot multiplexer 116. In the example of FIG. 1, the bit value n feeds into an input line 118 of the 1-hot multiplexer 116. Because the LNSCs 110₁, 110₂do not receive random data that cannot be tolerated, the bit value n received by the 1-hot mutliplexer 116 is valid.

[0033] Referring to FIG. 2, an embodiment of the present invention is shown wherein the system 100 further includes recirculation lines 200₁, 200₂. The recirculation lines 200₁, 200₂are in electrical communication with each LNSC 110₁, 110₂to recirculate the original bit values back into the LNSCs 110₁, 110₂. In the system 100 depicted in FIG. 2, the recirculated bit values are b and n. Recirculation ensures that the LNSCs 110₁, 110₂can scan values into the MISR 114 to improve observability. The original bit values in the LNSC 110₁, 110₂are also maintained to restart LBIST. One of skill in the art will appreciate that there are numerous hardware embodiments for recirculating bit values in a LNSC 110₁, 110₂, all of which are within the scope of the present invention.

[0034] The embodiment shown in FIG. 2 further ensures a 1-hot condition after initial flush for an input line 118 of the multiplexer 116 in a multi-cycle decode design. To accomplish this, the scan register 106₆that feeds directly into the input line 118 of the 1-hot multiplexer 116 is embodied as shown in FIG. 3. The scan register 106₆includes a plurality of scannable state elements 300₁, 300₂, 300₃, 300₄such as flip-flops which are disposed coupled in series along the functional path. After a certain number of state elements (e.g. 300₁, 300₂, 300₃) such as three, an inverter 302 is placed in series. The inverter 302 is followed in series by another state element 300₄which is then followed by a second inverter 304. Bit values are inputted from the left and traverse the illustrated chain of state elements and inverters 302, 304 before feeding into the input line 118.

[0035] Referring to FIG. 4, a flow diagram for a preferred process 400 of operating the system 100 in accordance with the present invention is shown. After the start 402 of the process 400, the scan path initializes 404 the state elements of the scan registers by flushing the scan path. During initialization, the state elements in the LRSCs 108₁, 108₂and LNSCs 110₁, 110₂are flushed to a zero state. This ensures that the last scan register 106₆in the functional path is in a 1-hot or 1-cold condition. Upon completion of initialization, the process 400 then disables update of all the LRSCs 406 by holding the clock enable off for state elements in the LRSCs 108₁, 108₂.

[0036] The process then performs 408 a certain number of system clocks to establish partially decoded values in the functional path based on an all zero encoded state. The PRPG 102 feeds 410 random data to the LRSCs 108₁, 108₂, but not to the LNSCs 110₁, 110₂. The process 400 then runs 412 the LBIST sequences until complete. The MISR 114 receives bit values which indicate test responses and produces 414 a unique signature. As shown in step 417, if the test is not completed, the process returns to step 410 to repeat the process until it is completed. The signature may be examined to determine the condition of the system 100, which ends 416 process 400.

[0037] The present invention ensures that during loading of random data from a PRPG 102 a 1-hot condition exists for the 1-hot multiplexer 116 so to prevent contention or a high current state. More particulary, the present invention advantageously provides an orthogonal 1-hot select signal line 118 to the 1-hot multiplexer 116. The present invention further improves observability of intermediate stages by having the LNSCs 110₁, 110₂feed the MISR 114 and not allowing the PRPG 102 to feed the LNSCs 110₁, 110₂.

[0038] The present invention may be embodied in other specific forms without departing from its scope or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.