Sample and hold circuit

[0002] This application claims priority under 35 USC §119(e)(1) of provisional application No. 60/171,762 filed Dec. 22, 1999.

[0003] This invention relates generally to analog and digital electronics, and more particularly to an improved sample and hold circuit.

[0004] The bandwidth and settling time of a sample and hold stage of a switched capacitor circuit is a function of the closed looped gain in an operational amplifier utilized in the stage. To sample and track an analog input, a unity gain is needed across the operational amplifier. This requirement places the operational amplifier at a unity gain operating point. For a single pole system, the bandwidth and settling time of a sample and hold stage are functions of the transconductance of the operational amplifier divided by the total output load capacitance.

[0005] To increase the speed at which the sample and hold stage can sample and track the analog input, conventional sample and hold stages increase the transconductance of the operational amplifier. One means of increasing the transconductance of the operational amplifier is by increasing the internal bias current of the input devices inside the operational amplifier. However, such a technique also undesirably increases the power dissipation of the sample and hold stage and reduces the bias swing of transistors within the input stage of the operational amplifier. Such technique also decreases the output impedance of devices within the operational amplifier with the negative effect of reducing the open loop gain of the operational amplifier. A second alternative means of increasing the transconductance of the operational amplifier involves increasing the aspect ratio of devices, such as transistors, inside the input stage of the operational amplifier. However, this second technique also undesirably increases the input capacitance of the operational amplifier, thereby worsening feedback caused by parasitic capacitances. Thus, both of these alternatives do not achieve improving the bandwidth or response time of sample and hold stages of switched capacitor circuits without either increasing power dissipation or the input capacitance of the operational amplifier.

[0006] As data converters such as analog to digital converters and digital to analog converters are used increasingly in high-speed data transfer applications, in many cases, the bandwidth and settling time of the sample and hold stage in a switched capacitor circuit is the principal bottleneck in time critical applications. Such switched capacitor circuits are also used significantly in filters designed for high-speed applications. Again, the bandwidth and settling time of the sample and hold stage in switched capacitor circuits in such filters becomes a bottleneck within such high-speed applications.

[0007] In accordance with the present invention, an improved sample and hold circuit is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods.

[0008] In one embodiment of the present invention, a sample and hold circuit is disclosed that includes an operational amplifier, the operational amplifier having a first and a second input and an output. The sample and hold circuit also includes a first feedback path of the operational amplifier, the first feedback path including a first capacitor coupled to the first input of the operational amplifier and a first switch coupled to the output of the operational amplifier. The sample and hold circuit further includes a second feedback path including a second capacitor coupled to the first input of the operational amplifier and a second switch coupled to the output of the operational amplifier. The sample and hold circuit additionally includes a third capacitor coupled to the first input of the operational amplifier.

[0009] In a second embodiment, a sample and hold circuit is disclosed that includes an operational amplifier and a plurality of switched capacitors, the switched capacitors introducing a closed loop gain of one-half for the operational amplifier.

[0010] Technical advantages of the present invention include presenting an improved sample and hold circuit addressing disadvantages of previous systems and methods. In particular, various embodiments of the present invention increase the bandwidth of a sample and hold circuit without increasing the input parasitic capacitance of the operational amplifier used in such sample and hold circuit. Additionally, various embodiments of the present invention improve the speed at which analog inputs may be sampled and held without dissipating additional power in the operational amplifier of such sample and hold circuit. A further advantage of various embodiments of the present invention is that a sample and hold circuit is presented that allows an increased bandwidth for such sample and hold circuit without substantial degradation of the opened loop gain of the operational amplifier or the bias swing of devices inside the operational amplifier. Yet another advantage of the present invention is that a sample and hold circuit is presented that may be used in a switched capacitor circuit where the settling time required is less than a few nanoseconds and where minimal parasitic capacitors are required.

[0011] Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.

[0012] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

[0013] FIG. 1 illustrates a sample and hold circuit implemented according to the teachings of the present invention;

[0014] FIG. 2 illustrates a timing diagram indicating the relative switching times of switches used to implement the sample and hold circuit of FIG. 1; and

[0015] FIG. 3 illustrates an alternative embodiment of a sample and hold circuit implemented according to the teachings of the present invention.

[0016] FIG. 1 illustrates one embodiment of a sample and hold circuit 10 that utilizes an operational amplifier 12 and switched capacitors 14, 16, 18, 20, 22, and 24 in order to track analog inputs with a digital output. Sample and hold circuit 10 increases the bandwidth and decreases the response time necessary for such sampling and tracking of the analog input from conventional sample and hold circuits and techniques without undesirable consequences such as, for example, increased power dissipation, reducing the bias swing of transistors within a utilized operational amplifier, and/or increasing the parasitic capacitances of such an operational amplifier.

[0017] In the illustrated embodiment, sample and hold circuit 10 is a differential sample and hold circuit utilizing a differential operational amplifier as operational amplifier 12 in order to sample and track the differential analog inputs defined by analog signals V_inP, applied at nodes 27 and 28, and V_inM, applied at nodes 40 and 42, at a digital output defined by signals V_outP at node 50 and V_outM at node 36.

[0018] In the illustrated embodiment, sample and hold circuit 10 includes six capacitors 14, 16, 18, 20, 22, and 24, as well as eight switches 25athrough 25hand five switches 26athrough 26e.All capacitors 14, 16, 18, 20, 22 and 24 have a substantially equivalent capacitance. In configuration, switch 25ais coupled between node 28 and capacitor 16 and switch 26bat node 32. Switch 25bis coupled between node 27 and capacitor 14 and switch 26eat node 30. Capacitor 14 is also coupled to capacitor 16, capacitor 18, switch 25c,and the positive input terminal of operational amplifier 12 at node 34. Capacitor 18 is further coupled to switches 25dand 26aat node 38. Switch 25cis also coupled to the negative output terminal of operational amplifier 12, switch 26a,and switch 26bat node 36. Switch 25dis further coupled to a common mode level voltage at node 39.

[0019] Similarly, switch 25eis coupled between node 42 and capacitor 20 and switch 26eat node 46. Switch 25fis coupled between node 40 and capacitor 22 and switch 26dat node 44. Capacitor 20 is also coupled to capacitor 22, capacitor 24, switch 25g,and the negative input terminal of operational amplifier 12 at node 48. Capacitor 24 is further coupled to switch 25hand switch 26cat node 52. Switch 25gis also coupled to switch 26c,switch 26d,and the positive output terminal of operational amplifier 12 at node 50. Switch 25his further coupled to a common mode level voltage at node 53.

[0020] The operation of sample and hold circuit 10 is illustrated in connection with the timing diagram of FIG. 2. The timing diagram of FIG. 2 illustrates a timing diagram representing one embodiment of the switching times for switch groups 25 and 26. In particular, the timing signal labeled PHI 1 corresponds to the opening and closing of all switches 25 at substantially equivalent times. Similarly, the timing signal labeled PHI 2 corresponds to the opening and closing of switches 26 at substantially equivalent times. In particular, each rising edge of PHI 1 represents the time (illustrated as “Time 1”) at which all switches 25 are closed. The falling edge of PHI 1 illustrates the time (illustrated as “Time 2”) at which all switches 25 are open. Similarly, the rising edge of PHI 2 illustrates the time (illustrated as “Time 3”) at which all switches 26 are closed and the falling edge of PHI 2 represents the switching time (illustrated as “Time 4”) at which all switches 26 are opened.

[0021] In operation of sample and hold circuit 10, at Time 1 as indicated in FIG. 2, switches 25 are closed causing analog voltage inputs V_inP to be sampled across switches 25aand 25bat nodes 30 and 32. Similarly, analog voltage signal V_inM is sampled across closed switches 25eand 25fat nodes 44 and 46. Additionally, a common mode level voltage supplied at nodes 39 and 53 are sampled across closed switches 25dand 25h, respectively, at nodes 38 and 52. Nodes 34 and 36, and nodes 48 and 50, are each shorted together by the closure of switches 25cand 25grespectively. Thus, nodes 34, 36, 48, and 50 all settle to the dc operating point of operational amplifier 12.

[0022] At Time 2 in operation of sample and hold circuit 10, switches 25 are closed as described with reference to FIG. 2, thereby holding analog voltage signal V_inP at nodes 30 and 32, and holding analog voltage signal V_inM at nodes 44 and 46.

[0023] At Time 3 in operation of sample and hold circuit 10, switches 26 are closed as described with reference to FIG. 2. Upon enclosure of switches 26, a transfer function of voltage signal V_outM at node 36 as compared to the voltage signal V_inP being held at nodes 30 and 32 is one-half. Therefore, voltage signal V_outM is equal to voltage signal V_inPdivided by 2. As two inputs V_inPare provided at nodes 30 and 32, output signal V_outMis equal to V_inP/2 plus V_inP/2, or V_inP. In particular, the voltage transfer function of the voltage at node 36 over the voltage at node 30 is defined by the equivalent impedance of the two feedback paths that include capacitors 16 and 18 respectively, divided by the input impedance that is defined by capacitor 14. As capacitors 14, 16, and 18 all have an equivalent capacitance (hereafter “C”) which is inversely proportional to impedance, the transfer function of the voltage at node 36 over the voltage at node 30 is equal to one-half C divided by C, which is equal to one-half. Thus, V_outM is equal to V_in/2, or the transfer function of the voltage at bode 36 over the voltage at node 30 is equal to ½.

[0024] Similarly, the transfer function of the voltage at node 36 over the voltage at node 32 is defined by the ratio of the feedback impedance introduced by capacitors 16 and 18 over the impedance introduced by the input impedance, in this case, capacitor 16. Thus, following logic similar to that described above, it can easily be shown that the transfer function of the voltage at node 36 over the voltage at node 32 is also equal to one-half. Thus, by summing the two inputs provided at nodes 27 and 28, the complete transfer function of: $\frac{V_{\mathrm{out}}M}{V_{\mathrm{in}}P}=\frac{1}{2}+\frac{1}{2}=1$

[0025] thereby generating the magnitude of V_outM necessary to sample and hold the magnitude of input V_inP while limiting the closed loop gain of operational amplifier 12 to one-half.

[0026] Thus, by employing a combination of switched capacitors, sample and hold circuit 10 can achieve an output V_outM equal to the magnitude of its sampled input V_inP using a closed loop gain across operational amplifier 12 of only one-half. It can easily be seen that, using capacitors 20, 22, and 24, the positive output V_outP may also directly reflect the magnitude of the input voltage V_inM using a closed loop gain of operational amplifier 12 of only one-half. Thus, a differential output of operational amplifier 12, as reflected across node 36 and node 50, may be achieved that is a direct sampling of the differential input applied across nodes 27 and 28 to nodes 40 and 42. Thus, between Time 3 and Time 4 as illustrated in FIG. 2, the differential output across nodes 36 and 50 is equivalent to the differential input across, for example, nodes 28 and 42 at Time 2.

[0027] At Time 4, switches 26 are again opened, in preparation for the next cycle of sampling and holding an analog signal that is begun at the closing of switches 25 as described at Time 1 in reference to FIG. 2.

[0028] Although operational amplifier 12 is illustrated in FIG. 1 as a differential operational amplifier with both differential inputs and differential outputs, the configuration of switched capacitors utilized in FIG. 1 may be easily adapted for use in an embodiment of operational amplifier 12 with differential inputs and a single output. In such an embodiment, capacitors 14, 16 and 18 and switches 25athrough 25d, 26a, and 26b, and the nodes coupling them, are unnecessary. In particular, node 46, instead of being coupled to node 30 by switch 26e, would instead be coupled to a common mode level voltage by switch 26e. The positive differential input of operational amplifier 12 would be coupled directly to a common mode level voltage in such an embodiment. The negative differential output of operational amplifier 12 at node 36 would instead be a single positive output normally used for a non-differential operational amplifier 12. In any event, this alternative embodiment would achieve the same sampling of the magnitude of the analog voltage signal V_inP at the output V_outM as shown at node 36 using a closed loop gain of one-half for operational amplifier 12. The selection of the illustrated differential operational amplifier 12 or of the described alternative embodiment using a non-differential operational amplifier 12 may depend upon the particular application for which sample and hold circuit 10 is utilized, and may take into account the significance of outside factors such as noise introduced across operational amplifier 12 when a differential configuration is not utilized.

[0029] In an additional embodiment of sample and hold circuit 10 illustrated in FIG. 3, the feedback paths utilized between each of nodes 34 and 36, that includes switch 25c, and nodes 48 and 50, that includes switch 25g, may be eliminated by utilizing switches 25cand 25gto couple nodes 34 and 48 to a common mode level voltage. Thus, coupling nodes 34 and 48 to the common mode level voltage serves to bring the inputs to operational amplifier 12 at nodes 34 and 48 to a common mode level voltage previously brought about by the presence of feedback paths connecting node 34 to node 36 and node 48 to node 50.

[0030] The described operation of sample hold circuit 10 allows the magnitude of an analog voltage input to be sampled and held at the output of operational amplifier 12 utilizing a close loop gain of only one-half. As the bandwidth and response time of sample and hold circuit 10 are functions of the closed loop gain of operational amplifier 12, by reducing the required gain from one to one-half, the bandwidth of sample and hold circuit 10 is doubled. Similarly, the response time required for sample and hold circuit 10 to sample and hold the magnitude of an analog signal may be effectively halved. Thus, the implementation of sample and hold circuit 10, in any of the described embodiments of this invention, may eliminate bottlenecks previously presented in many high speed applications by prior implementations of sample and hold circuits.

[0031] Although the present invention has been described using several embodiments, various changes and modifications may be suggested to one skilled in the art after a review of this description. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.