US 6,629,425 B2Grant
MEMS heat pumps for integrated circuit heat dissipation
Issue Date:2003-10-07
•10 Claims
•12 Drawing Sheets
Abstract
A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling channels are embedded within an integrated circuit die, such as in interlevel dielectric layers between metal levels. The channels are formed by engineering deposition of a layer to line trenches and form continuous voids along the trenches. Exemplary heat pumps comprise cavities, formed in communication with the channels, covered by piezoelectric actuators. Preferably, the actuators are wired to act in sequence as a peristaltic pump, circulating the fluid within the channels. The channels are positioned to carry heat from active devices within the integrated circuit, and a heat sink carries heat from the die.
Metadata
Assignee
- Micron Technology, Inc.
Inventor
- Venkateshwaran Vaiyapuri
Application Information
Application Number:US 09/912,631
Filing Date:2001-07-23
Priority Date:2000-07-24
Art Unit:7
Classifications
IPC:
F25D 2312H05K 720
Field of Search:
62259262118361688361690361689165185165 80416510433438422438632
Patent Drawings (12 sheets)
Description
REFERENCE TO RELATED APPLICATION
[0002] This application claims the priority benefit under 35 U.S.C. §119 to Singapore patent application no. 200004125-1, filed Jul. 24, 2000.
FIELD OF THE INVENTION
[0003] The present invention relates generally to the cooling of integrated circuits, and more particularly to a MEMS heat pump and cooling channels for cooling integrated circuits.
BACKGROUND OF THE INVENTION
[0004] Today's personal computers (PCs) and workstations are experiencing a rapid growth of accelerated clocking and computational speeds. PC clock speeds have progressed from the Intel Corporation 486™ microprocessor speeds of 60 and 90 MHz, to the present Pentium III™ clock speeds in excess of 600 MHz. Moore's Law generally predicts a doubling of computing power and circuit complexity every year and a half or so.
[0005] The downside corollary to Moore's Law, however, is that with doubling the number of devices in an integrated circuit (IC) consequently raises the amount of heat generated requiring dissipation. As an integrated circuit drives current between transistors it consumes power, producing waste heat that eventually transfers outward through the chip from the surface of the die. Generally, a PC chip designed for commercial use can withstand up to 150° C. Exceeding that limit, however, will cause the chip to make errors in its calculations, or perhaps fail completely.
[0006] Current solutions in heat dissipation for chips include heat spreaders, heat sinks and fans. Heat spreaders, which generally are made of a tungsten-copper alloy and are placed directly over a chip, have the effect of increasing the chip's surface area, allowing more heat to be vented upward. Similarly, heat sinks spread the heat upward through fins or folds, which are vertical ridges or columns that allow heat to be conducted in three dimensions—length, width, and height, as opposed to the two-dimensional length and width of heat spreaders.
[0007] Fans within a computer housing can further aid heat dissipation from the chip or heat sink surface by convection. The amount of heat a fan dissipates away from a chip depends on the volume of air the fan moves, the ambient temperature, and the difference between the chip temperature and the ambient temperature.
[0008] The miniaturizing of integrated circuits have generally allowed for a reduction of operating voltages, resulting in lower heat production. However, chip shrinkage also means that heat-generating devices are packed closer together. Thus, the “power density” or the amount of heat concentrated at particular spots across the chip may begin to climb. As a consequence, heat is generated faster than it can be dissipated as higher clock speeds are demanded.
[0009] For example, PCs with a 486™ microprocessor drew generally 12 to 15 watts, primarily concentrated in the processor. A power supply with an embedded fan was typically sufficient to circulate air and cool the inside of the PC chassis, while a passive heat sink could cool the processor. On the other hand, Pentium™ processors from Intel Corporation consumed about 25 watts, thus requiring more cooling means than the passive heat sink for the processor alone. Similarly, the Pentium II™ processor consumes about 40 watts, while future processors like the 64-bit Merced™ may consume up to 65 watts. Other transistor-laden components must also contend with increasing heat generation: add-on cards; chipsets; graphics chips; and high-performance dynamic random access memory (DRAM).
[0010] There is, consequently, a need for improved heat dissipation from integrated circuits.
SUMMARY OF THE INVENTION
[0011] These and other needs are satisfied by several aspects of the present invention.
[0012] In accordance with one aspect of the invention a cooling system is provided for an integrated circuit. The system comprises a pump that circulates fluid within the integrated circuit. Desirably, the fluid carries heat from regions of heat generation to regions outside the integrated circuit.
[0013] In particular, Miniaturized Electro-Mechanical Structure (MEMS) technology is applied to create a miniature electromechanical pump within the chip. The illustrated pump comprises a piezoelectric actuator formed over a cavity in a structural layer. In other arrangements, a MEMS structure formed externally can be placed within the cavity, wired for operation, and sealed within the cavity. The cavity is in fluid communication with fluid-filled channels embedded within the integrated circuit.
[0014] The channels are formed, in the preferred embodiments, by etching trenches in a desired pattern, followed by lining the trenches by deposition. The deposition is engineered to create a continuous air gap along the trenches, and the cavity is opened to communicate with this air gap. Desirably, the air gap forms a closed loop including the cavity. After formation of the pump, these channels are then filled with fluid, such as argon, helium or other thermally conductive fluid, and the channels are sealed, such as by lamination of the piezoelectric actuator over the cavity.
[0015] In operation, the pump circulates fluid within the channels and preferably carries heat away from heat generating integrated devices, such as fast switching transistors in a logic circuit of a dynamic random access memory (DRAM) chip. In the illustrated embodiment, the channels communicate the heat outwardly from these buried devices, and a heat sink, such as a conventional copper plate, communicates heat away from the die. Moreover, a series of pumps can be arranged in sequence along the channels, and operated in sequence to serve collectively as a peristaltic pump.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] These and further aspects of the invention will be readily apparent to those skilled in the art from the following description and the attached drawings, which are meant to illustrate and not to limit the invention, and wherein:
[0017] FIG. 1A is a schematic plan view of a partially fabricated integrated circuit, illustrating segmented zones comprising cooling channels and heat pumps.
[0018] FIG. 1B is a schematic horizontal cross-section of a segmented zone of FIG. 1A, schematically illustrating the interconnection between cooling channels and a heat pump.
[0019] FIG. 2 is a schematic vertical cross-section of a partially fabricated integrated circuit, illustrating a trench overlying a semiconductor substrate.
[0020] FIG. 3 is a schematic cross-section of the trench of FIG. 2, illustrating a “pinching” effect of a deposited sealant layer.
[0021] FIG. 4 is an isometric view of a section of a partially fabricated cooling channel.
[0022] FIG. 5 is a schematic cross-section of a partially fabricated integrated circuit, illustrating the formation of a cavity opening within an insulating layer in communication with cooling channels.
[0023] FIG. 6 is a schematic cross-section of a partially fabricated integrated circuit, illustrating a piezoelectric pump actuator laminated over the cavity of FIG. 5.
[0024] FIG. 7 is a schematic cross-section of a partially fabricated integrated circuit, illustrating a fluid filling the cooling channels and cavity of the structure of FIG. 6.
[0025] FIG. 8A is a schematic cross-section of a partially fabricated integrated circuit, illustrating a pump actuator during an active low input signal.
[0026] FIG. 8B is a schematic cross-section of a partially fabricated integrated circuit, illustrating a pump actuator during an active high input signal.
[0027] FIG. 9A is a schematic cross-section of a partially fabricated integrated circuit, illustrating the position of a discrete packet of fluid during a first step of operating an exemplary heat pump array.
[0028] FIG. 9B illustrates a timing diagram corresponding to the first sequential step of FIG. 9A.
[0029] FIG. 10A is a schematic cross-section of a partially fabricated integrated circuit, illustrating the position of the packet of fluid of FIG. 9A during a second step.
[0030] FIG. 10B illustrates a timing diagram corresponding to the second step of FIG. 10A.
[0031] FIG. 11A is a schematic cross-section of a partially fabricated integrated circuit, illustrating the position of the packet of fluid of FIG. 10A during a third step.
[0032] FIG. 11B illustrates a timing diagram corresponding to the third step of FIG. 11A.
[0033] FIG. 12 is a schematic of a partially fabricated integrated circuit, illustrating a thermally conductive plate or heat sink bonded to the die of FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0034] As noted in the “Background” section above, the trend in integrated circuit fabrication is to further miniaturize devices, condensing larger numbers of transistors in smaller regions. As devices become smaller and more powerful, heat generated by device switching and current driving of more densely packed transistors continues to rise. Various solutions have been implemented in response to the cooling needs of heat-generating devices.
[0035] Solutions such as heat spreaders, heat sinks and fans have all aided in cooling such heat-generating devices. Such solutions were generally effective in cooling earlier generation chips. However, as integrated circuits become more and more dense, present cooling measures by external means will soon be ineffective. Furthermore, existing trends dictate that other transistor-laden devices, aside from microprocessors, will similarly require cooling means. Devices such as chipsets, graphics chips, and high-performance DRAM are similarly generating enough heat to warrant their own cooling means in order to avoid computation errors and other general device failures.
[0036] It is an object of the present invention to provide cooling means for heat-generating integrated circuits. In the preferred embodiment, an embedded cooling feature for integrated circuits comprises a Miniaturized Electro-Mechanical Structure (MEMS) heat pump in communication with interconnected cooling channels.
[0037] MEMS is a relatively new field which exploits existing microelectronics fabrication technology to create complex machines with micron feature sizes. These machines can have many functions, including sensing, communication and actuation.
[0038] The mechanical actuation of a MEMS heat pump of the illustrated embodiment effectively circulates a fluid, preferably a gas, through cooling channels, promoting heat energy transfer by forced convection. The cooling channels function as conduits for the circulating fluid that serves as a heat-transferring medium. Generally, heat is absorbed by the fluid near heat-generating devices, carried along with the fluid in the channels, and released to heat sinks leading out of the chip.
[0039] FIG. 1A is a schematic plan view of the preferred embodiment, illustrating an integrated circuit chip or die 100 with segmented zones 110 across the chip. FIG. 1B is an enlarged view of an exemplary zone 110 comprising a MEMS heat pump 150 interconnected with a network of cooling channels 50. The zones 110 can be selected to maximize cooling efficiency, depending on the configuration of the integrated circuit 100. Accordingly, the network of interconnected cooling channels 50 may vary in design layout to best benefit the cooling needs of the particular integrated circuit die 100.
[0040] A heat sink is preferably provided to direct the heat energy away from the die 100. In the preferred embodiment, a heat sink or heat conductive plate 130 (see FIG. 12) is bonded to a backside of the die 100. Accordingly, the cooling channels 50 and heat pumps 150 expel thermal energy from within the integrated circuit die 100, while the heat sink 130 carries heat away from the die 100.
[0041] It is another object of the present invention to create cooling channels for an integrated circuit by controlling a thin film thickness across a surface topography. The cooling channels preferably contain a fluid that is thermally conductive and has a high specific heat capacity, thus promoting efficient energy transfer to and from the fluid by conduction and transfer along the channels by convection.
[0042] The network of cooling channels is by engineering a deposition process to produce continuous voids while lining trenches. Generally, it is desirable for thin films to obtain good step coverage or conformal coverage, wherein equal film thickness exists over all surface topography regardless of its slope (i.e., vertical and horizontal surfaces). However, it is preferable in the illustrated embodiment to engineer a non-conformal thin film. A non-conformal thin film can be realized by physical vapor deposition (PVD) or chemical vapor deposition (CVD), as is well known in the art.
Fabrication of Cooling Channels
[0043] FIGS. 2 through 5 illustrate the fabrication of cooling channels 50 in the preferred embodiment.
[0044] FIG. 2 is a schematic cross-section, illustrating an opening, preferably an elongated trench 30 within a partially fabricated integrated circuit. The trench 30 is formed within a structural layer 65, such as a typical interlevel dielectric (ILD) material, that is formed over electronic devices such as integrated transistors. The structural layer comprises borophosphosilicate glass (BPSG) in the illustrated embodiment, and overlies a semiconductor substrate 200 in which the electronic devices are (partially) formed. Though not shown, will be understood that there will generally be intervening layers between the structural layer 65 and the substrate. The trench 30 serves as a foundation to form conduits from regions of heat generation throughout the integrated circuit 100 to heat exhaust points. Accordingly, the trench 30 preferably traverses proximate integrated heat-generating electronic devices, such as output driver transistors in logic circuits, particularly in a dynamic random access memory (DRAM) chip.
[0045] Within the layer 65, the trench 30 is defined by a top opening 38, bottom corners 36, top corners 32 and a surrounding planar surface 34. The trenches 30 of the preferred embodiment preferably range from about 0.05 μm to 20 μm deep and about 0.1 μm to 10 μm wide, more preferably about 0.2 μm to 5 μm deep and about 0.5 μm to 2 μm wide, and most preferably about 0.5 μm to 2 μm deep and about 0.8 μm to 1.2 μm wide.
[0046] At the same time, a larger cavity 70 (FIG. 5) is formed in communication with the trenches 30. Advantageously, the cavity 70 has a significantly smaller aspect ratio.
[0047] Referring to FIG. 3, a sealant layer 15 is deposited in the trench 30 by chemical vapor deposition (CVD) to form the cooling channels of the preferred embodiment. For the sealant layer 15, silicon carbide (SiC) is the preferred material for deposition due to its thermal stability, low stress, crack resistance and hermetic characteristics.
[0048] The wafer with trenches 30 of the preferred embodiment is introduced into a CVD chamber with a chamber pressure range preferably between about 5 Torr and 10 Torr, more preferably between about 6 Torr and 9 Torr. The temperature range within the process chamber is preferably between about 300° C. and 450° C., more preferably between about 325° C. and 425° C., most preferably between about 350° C. and 400° C.
[0049] A silicon source gas such as silane (SiH4) is flowed in the preferred process chamber at a rate of between about 50 sccm and 300, more preferably between about 80 sccm and 200 sccm. Additionally, a carbon precursor, such as methane (CH4), is generally used for the CVD growth of SiC. In the preferred embodiment, CH4is used as the carbon precursor, and is flowed at a rate of between about 50 sccm and 300, more preferably between about 80 sccm and 200 sccm.
[0050] Deposition conditions can be controlled to generally deposit the sealant layer 15 at the top corners 32 at a faster rate than at the bottom corners 36 (see FIG. 3). For the preferred embodiment, the process described above deposits the sealant layer 15 for a duration of 50 seconds, while the pressure is ramped to about 20 Torr. As a result, the sealant layer 15, or silicon carbide (SiC) layer grows more quickly and pinches off at the opening 38 before the trench 30 is completely filled.
[0051] FIG. 4 is an exemplary view of a cooling channel 50 of the preferred embodiment. The deposited sealant layer 15 seals the opening 38 before trench 30 is filled, consequently forming a sealed air gap 20. The sealed air gap 20 follows the length of the trench 30, forming a tube or channel 50 having a width or diameter on the order of 5,000 Å.
[0052] After fabrication of an initial level of cooling channels 50, subsequent layers, such as BPSG, are deposited over the initial layer as the integrated circuit is fabricated, typically in the course of metallization or “back-end” processing. Depending upon the circuit design, the process of etching trenches 30 and depositing sealant layers 15 can be repeated as the layers of the integrated circuit are built up until a desired network of cooling channels is created.
[0053] In a typical DRAM fabrication, where a plurality of dies are simultaneously formed on a single large substrate (e.g., 200 mm or 300 mm silicon wafer), at least the steps described up to this point are preferably conducted prior to cutting the substrate into a plurality of dies. Optionally, die cutting can be performed prior to completion of heat pumps, as described below.
Fabrication of MEMS Heat Pumps
[0054] It is a further object of the preferred embodiment to provide a circulation means for a fluid that will fill the cooling channels 50. A pump, fan or other circulator is desired to circulate a fluid through the cooling channels 50, enhancing cooling of the integrated circuit.
[0055] A heat pump with micron feature sizes is most desirable for it to be effectively incorporated within an integrated circuit. In the preferred embodiment, a MEMS circulator or pump communicates with the network of cooling channels 50. Micro Electro-Mechanical Structures (MEMS) are built by a relatively new technology that exploits an existing microelectronics infrastructure to create mechanical structures on such a micro-scale.
[0056] With reference to FIG. 5, an opening or cavity 70 is formed in communication with the cooling channels 50. While shown in communication with only one level of channels, it will be understood that the cavity can extend vertically through multiple levels of the cooling channel network. The cavity 70 is preferably formed within the chip's exclusion zones by conventional photolithography and dry etch processes. Preferably, the cavity 70 has a depth between about 0.05 μm and 20 μm, more preferably between about 0.2 μm and 5 μm, and most preferably between about 0.5 μm and 2 μm. The cavity 70 has a bottom area ranging between about 100 μm2and 10,000 μm2, more preferably between about 500 μm2and 5,000 μm2, and most preferably between about 1,000 μm2and 3,000 μm2.
[0057] As noted above, the cavity 70 is preferably formed simultaneously with the trenches 30. Accordingly, the sealant layer 15 coats the cavity 70 walls. However, the much wider cavity 70 has a low aspect ratio. Accordingly, the cavity 70 remains open while the sealant 15 pinches off and encloses the channels 50.
[0058] The circulator or MEMS heat pump of the preferred embodiment is formed at the cavity 70 described above. The MEMS heat pump comprises a flexible membrane, preferably a piezoelectric membrane that, when actuated, effectively pumps a fluid through the cavities 70 and interconnected cooling channels 50. In other arrangements, the heat pump can resemble a fan, vibrator or other agitator that is externally micromachined and placed within the cavity to cause circulation of fluid during operation.
[0059] Methods for the formation of flexible membranes for pump actuation are known by those skilled in the micro-machining art. For example, a method for the formation of a silicon-based micropump is described in the paper, “A Novel Micromachined Pump Based On Thick-Film Piezoelectric Actuation,” by Michael Koch et al., Sensors and ActuatorsA70 (1998), pp. 98-103, (hereinafter “Koch et al.”), the disclosure of which is incorporated herein by reference. The actuation principle of the exemplary pump relies on the flexure of a screen-printed piezoelectric lead zirconium titanate (PZT) layer on a large-scale silicon membrane.
[0060] FIG. 6 illustrates such a flexible membrane or piezoelectric actuator 147 for a MEMS heat pump within an integrated circuit in accordance with the preferred embodiment. Preferably, the piezoelectric actuator 147 is first formed independently and then laminated over the structure of FIG. 5.
[0061] Referring to FIG. 6, the actuator 140 comprises a first layer 141 that is flexible enough to bend within the cavity 70. The first layer 141 preferably comprises a silicon membrane, as described in Koch et al., incorporated by reference above. A thin insulating layer 142, preferably comprising a form of silicon oxide, is optionally formed above the first layer 141. The oxide layer 142 isolates the first layer 141 from the next conductive layer that will comprise the bottom electrode of the pump actuator.
[0062] A first conductive layer 143, is deposited above the oxide layer 142. The first conductive layer or bottom electrode 143 comprises any suitable conductive material that can serve as a piezoelectric actuator's electrode in a thickness that remains flexible. Typical electrode metals include aluminum and copper. A piezoelectric layer 144, is formed over the first conductive layer 143. The piezoelectric layer 144 of the illustrated embodiment comprises lead zirconium titanate (PZT). A second conductive layer 145 is formed over the piezoelectric layer 144. The second conductive layer 145 can be any suitable conductor, typically metal, as discussed above with respect to the first conductive layer 143. An exemplary top electrode 145 comprises a 0.5 milli-inch to 5 milli-inch copper foil laminated or epoxied over the PZT 144.
[0063] This stack of layers (141, 142, 143, 144 and 145) is patterned (e.g., by photolithography) and etched to isolate a plurality of piezoelectric actuators 147. The individual actuators 147 are made slightly larger than the cavity 70 to allow for placement, such as by pick and place machines, and sealing over the cavity 70. Such lamination can be conducted prior to or after cutting the substrate (e.g., silicon wafer) into a plurality of dies. Together with the cavities 70, the actuators 147 define a plurality of heat pumps 150.
[0064] In the course of assembly and sealing of the channels 50, a heat transfer medium, preferably comprising a thermally conductive fluid having a high specific heat capacity, is introduced into the cooling channels 50. Openings to the cooling channels are formed and the workpiece on which the integrated circuit is formed is subjected to the fluid (preferably a gas) while the openings are sealed. Preferably, an inert fluid 25, more preferably a thermally conductive noble gas (e.g., Ar, He, Kr, or Xe) is utilized to fill the cooling channels 50, avoiding unwanted reactions with the process environment and semiconductor layers. Methods for filling cavities or micro-pumps with fluids has been described in “A Piezoelectric Micropump based on Micromachining of Silicon,” by H. T. G Van Lintel et al., Sensors and Actuators,15 (1988), pp. 153-167, the disclosure of which is incorporated herein by reference.
[0065] In the preferred embodiment, the inert fluid 25 is introduced through an opening, preferably through the cavity 70. The MEMS heat pump 150 of FIG. 7 is placed within a process chamber at atmospheric pressure and filled with the desired inert fluid 25. As a result, the cavity 70 and interconnect cooling channels 50 are filled with the desired inert fluid 25. Laminating the actuator 147 over the cavity 70 subsequently seals the cavity 70. The skilled artisan will appreciate
[0066] A resultant plurality of MEMS heat pumps 150 are preferably arranged and wired in an array to enable pumping the fluid 25 peristaltically (i.e., the fluid 25 is forced onward by the sequential, wavelike contractions of the arrayed heat pumps 150), as will be appreciated from a discussion of the operation, set forth below. The skilled artisan will readily appreciate that each actuator 147 is preferably also wired for operation in the course of lamination. In particular, the electrode layers 143, 145 are preferably electrically connected to a voltage source and to circuitry that times operation of pumps in an array, as described below with respect to FIGS. 9-11.
[0067] A passivation layer 149 is desirably deposited over the die 100 after formation of the actuators 147. The passivation layer 149, preferably comprising an insulating barrier such as silicon nitride or silicon oxynitride, is desirably deposited by CVD in a manner that protects the formed piezoelectric actuators 147 from damage. The passivation layer 149 also electrically isolates the piezoelectric actuators 147 from one another and from adjacent electronics. The passivation layer can be formed as part of the laminate, but is more preferably deposited over the entire die after lamination.
Exemplary Operation
[0068] FIGS. 8A and 8B illustrate two different positions during pump operation by the application of an input voltage. In the preferred embodiment, the voltage applied to the piezoelectric actuator 147 preferably ranges between about 2 VDCand 24 VDC, more preferably between about 5 VDCand 12 VDC.
[0069] FIG. 8A illustrates the position of an exemplary flexible membrane or piezoelectric actuator 147 during a relaxed (e.g., ˜0 VDC) or active low state (e.g., ≦2 VDC), as will be appreciated by the skilled artisan. The piezoelectric actuator 147 can be planar or bends downward as shown, compressing the volume within cavity 70. It should be generally understood that the position of the piezoelectric actuator 147 within the cavity 70 volume is strictly schematic and does not represent an actual compression ratio. Furthermore, the cavity is much larger in the horizontal dimension (as compared to the vertical dimension) than indicated in the figures.
[0070] On the other hand, FIG. 8B illustrates the position of the piezoelectric actuator 147 during an active high state (e.g., applied voltage of about ˜12 VDC). The piezoelectric actuator 147 is electrically forced to actuate and bend in an upward direction. Actuation of the piezoelectric actuator 147, in turn, increases the volume within the cavity 70 creating a low pressure zone that pulls fluid into the cavity 70. When returned to the active low state, the piezoelectric actuator 147 compresses the volume enough to push a fluid out of the cavity 70 and seal the passage of material backward through the system when the next cavity activates (see FIGS. 9A to 11B). The repetitive actuation of the piezoelectric actuator 147 results in the pumping of a fluid through the cavity 70 and interconnected cooling channels 50.
[0071] With reference to FIGS. 9A through 11B, an exemplary sequence of pump actuations is illustrated for propelling the fluid 25 onward through sequential cavities 70a, 70b, 70cand interconnected cooling channels 50. The process is illustrated by reference to an arbitrarily defined fluid packet 25aof the continuous fluid filling the interconnected cooling channels 50.
[0072] In the illustrated embodiment, FIGS. 9A and 9B show an array of MEMS heat pumps 150a, 150b, 150ccorrespondingly assembled with a sequential array of cavities 70a, 70b, 70cand a preferred timing diagram, respectively. A first moment 301 indicates when the first MEMS heat pump 150ais active low, the second heat pump 150bis active high and the third heat pump 150cis recently transitioned active high. At this first moment 301, the fluid packet 25ais being pulled towards the second cavity 70bshortly after it is compressed out of the first cavity 70a.
[0073] Subsequently, FIGS. 10A and 10B illustrate a second moment 302 when the first heat pump 150ais active low, the second heat pump 150bis recently transitioned active low and the third heat pump 150cis active high. During this second moment 302, the fluid packet 25ais compressed out of the second cavity 70band pulled into the third cavity 70c.
[0074] FIGS. 11A and 11B illustrate a third moment 303 when the third heat pump 150cis recently transitioned active high, the second heat pump 150bis active low and the third heat pump 150cis also active low. The third moment 303 indicates when the fluid packet 25ais compressed out of the third cavity 70cand into the interconnected cooling channel 50. Also, upstream fluid is subsequently drawn into the first cavity 70aas a result of the upward actuation of the first heat pump 150ato continue the repetitive pumping cycle. With the continuous, sequential actuation of the peristaltic MEMS heat pumps 150, the cooling fluid 25 effectively circulates through the cavities 70 and interconnected cooling channels 50, which, in turn, cools the integrated circuit 100 by forced convection. Most preferably, heat is carried from regions of high heat generation, such as logic circuits of a DRAM chip.
[0075] With reference to FIG. 12, another aspect of the present embodiment is to provide a thermally conductive material such that it can conductively carry heat from the cooling fluid within the cooling channels to points outside of the die or chip 100. Generally, a thermally conductive material or a heat sink provides a thermal path, thus directing thermal energy away from its hot region to atmosphere.
[0076] The heat sink 130 is preferably made of a high thermal conductivity material, such as copper, and preferably covers a large fraction of the overall integrated circuit 100 area, preferably greater than about 50 percent, more preferably greater than about 80 percent of the overall integrated circuit 100 area. Also, the thickness of the heat sink 130 is preferably between about 1 μm and 20 μm, more preferably between about 5 μm and 10 μm. In the preferred embodiment, the heat sink 130 is aligned with and laminated to a surface of the integrated circuit die 100. The heat sink 130 is bonded to the surface of the die 100 by an epoxy 135, which is also thermally conductive and provides thermal communication between the die 100 and the heat sink 130.
[0077] The cooling channels 50 and the MEMS heat pump(s) 150 thus preferably circulate a heat transfer medium, promoting a more efficient cooling of an integrated circuit by forced convection. Advantageously, the preferred embodiment incorporates miniature circulation devices within integrated circuits. The combined effect of a cooling fluid pumping through networked cooling channels within the die 100 and a heat conductive plate that directs heat away from the die 100 effectively cools the integrated circuit die 100 during operation.
[0078] Aside from heat pump actuators, other microelectromechanical structure (MEMS) devices can be incorporated to circulate a fluid for cooling of an integrated circuit. A MEMS fan, for example, can similarly force a fluid to flow by the mechanical movement of parts. Other MEMS devices that involve mechanical movement of parts to pump, agitate, otherwise cause a fluid to move or circulate through channels can be employed in the integrated heat pump.
[0079] Although the foregoing invention has been described in terms of certain preferred embodiments, other embodiments will become apparent to those of ordinary skill in the art in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the recitation of preferred embodiments, but is intended to be defined solely by reference to the appended claims.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
We claim:
1. An integrated circuit with embedded cooling channels, comprising:
a structural layer overlying integrated transistors in a semiconductor substrate, the structural layer having trenches formed therein;
a deposited layer coating surfaces of the trenches and sealing upper openings of the trenches, the deposited layer surrounding a continuous air gap extending longitudinally along the trenches;
at least one cavity in communication with the air gap, the cavity housing a fluid pump comprising a piezoelectric actuator partially defining and sealing the cavity; and a fluid disposed within the air gap.
2. The integrated circuit of claim 1, wherein the deposited layer comprises a barrier material.
3. The integrated circuit of claim 2, wherein the deposited layer comprises silicon carbide (SiC).
4. The integrated circuit of claim 1, wherein a lateral width of the air gap is less than about 5,000 Å.
5. The integrated circuit of claim 1, wherein the fluid is inert.
6. The integrated circuit of claim 5, wherein the fluid comprises a thermally conductive gas.
7. The integrated circuit of claim 2, wherein the structural layer comprises an interlevel dielectric between metallization levels of the integrated circuit.
8. The integrated circuit of claim 7, wherein the interlevel dielectric comprises borophosphosilicate glass.
9. The integrated circuit of claim 1, wherein a width of the trenches is range between about 0.5 μm and 2 μm.
10. The integrated circuit of claim 9, wherein the width of the trenches is between about 0.8 μm and 1.2 μm.
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