Circuit, method and/or architecture for improving the performance of a serial communication link

[0002] The present invention may relate to co-pending application Ser. No. 09/347,830, filed Jul. 2, 1999, Ser. No. 09/347,046, filed Jul. 2, 1999 and Ser. No. 09/347,045, filed Jul. 2, 1999, which are each hereby incorporated by reference in their entirety.

[0003] The present invention relates to communication devices generally and, more particularly, to a circuit, method and/or architecture for improving the performance of a serial communication link.

[0004] Referring to FIG. 1, a block diagram illustrating a communications circuit 10 is shown. The circuit 10 comprises a number of ports 14a-14n.Each of the ports 14a-14ncomprises receive block 16, a transmit block 18 and a multiplexer 20.

[0005] The ports 14a-14nare connected to each other via serial links 21a-21nand 22a-22n.The ports 14a-14neach comprise serial inputs 24a-24n,26a-26nand 28a-28n,and serial outputs 25a-25n,27a-27nand 29a-29n,respectively. The serial connection from each port 14a-14nto another port 14a-14nis in both directions (i.e., both receive and transmit communication). The data arrives in the transmit block 18a-18nfrom a parallel interface 15a-15n,respectively, for each port 14a-14n.The data is then transmitted through a selectable multiplexer 20a-20nto the serial outputs 25a-25n,27a-27nand/or 29a-29n.The serial outputs 25a-25n,27a-27nand/or 29a-29ntransmit the data to one of the serial communication links 22a-22n.

[0006] For the receive side, the data is received from one of the serial communication links 21a-21nor 22a-22nat the serial input 24a-24n,26a-26nand/or 28a-28nand passed through the selectable multiplexer 20a-20nto the receive (RX) block 16. The receive block 16 then passes the data to one of the parallel interfaces 15a-15n.

[0007] The selectable multiplexers 20a-20ncan be configured by management registers or by interface pins. When the connection from a particular port 14a-14nfor either transmit or receive needs to be changed, the configuration interface or the configuration registers pass this new information to the particular selectable multiplexers 20a-20b.For the receive side, the receiver 16 has to wait for a period of time to acquire a lock.

[0008] The performance of the circuit 10 is significantly reduced since the amount of time to acquire a lock to a new port is of the order of the time it takes to send a block of data. Such a condition occurs in data communication switches.

[0009] The present invention concerns a circuit comprising a plurality of communication devices each configured to receive and transmit one or more data packets in response to one or more control signals and a control circuit configured to generate the one or more control signals in response to the one or more data packets.

[0010] The objects, features and advantages of the present invention include providing a communication device that may (i) eliminate a lock time between successive transfers, (ii) improve the overall performance of the device, and/or (iii) conserve power.

[0011] These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

[0012] FIG. 1 is a block diagram of a conventional communication device;

[0013] FIG. 2 is a block diagram of a preferred embodiment of the present invention; and

[0014] FIG. 3 is a more detailed block diagram of one of the ports of FIG. 2.

[0015] Referring to FIG. 2, a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 generally comprises a number of ports 102a-102nand a circuit 104. In one implementation, circuit 104 may be a scheduler circuit. The ports 102a-102nmay have one or more input streams at inputs 110a-110nand one or more output streams at outputs 112a-112n,respectively. The inputs 110a-110nand the outputs 112a-112nmay be considered a parallel interface.

[0016] Each of input streams 110a-110nmay be connected to one of the ports 102a-102nthrough one or more classifier circuits 114a-114n.The classifier circuits 114a-114nmay look at information embedded within one or more data packets (e.g., multicast information, destination information, priority information, etc.) to generate one or more signals (e.g., classifier control signals CLASSCTRa-n) at one or more outputs 116a-116n.The classifier control signals CLASSCTRa-n may determine the appropriate outgoing port 102a-102nas well as the priority of the traffic in the appropriate port 102a-102n.The packet classifiers 114a-114nmay determine the priority of the data packet as well as the number of destination ports 102a-102nfrom the information embedded in the data packets.

[0017] The scheduler 104 is generally configured to present a plurality of port control signals (e.g., PORTCTRa-n) in response to a number of control signals (e.g., CLASSCTRa-n). The port control signals PORTCTRa-n may comprise a first and second list. The first and second list may indicate (i) which port to transfer and/or receive the packet of data to and/or from, and (ii) the order to transfer the data packets within each port.

[0018] The ports 102a-102ngenerally communicate the data packets to each other through a plurality of serial links 120a-120nand/or 121a-121n.The present invention may have a number of serial links (e.g., P), where P is an integer. The number of serial links P depends on the number of ports 102a-102n.The ports 102a-102nmay be configured to both transfer and receive the data packets. The data packets may be presented in an order determined in response to one of the plurality of control signals PORTCTRa-n presented at the outputs 122a-122n.The ports 102a-102bmay present data packets to the outputs 112a-112n.

[0019] Each of ports 102a-102nmay comprise a (i) plurality of serial inputs 126a-126n,128a-128nand 130a-130n,and (ii) a plurality of serial outputs 127a-127n,129a-129nand 131a-131n,respectively. One or more of the serial inputs 126a-126nof the port 102amay be connected to the serial links 120a-120n.One or more of the serial links 120a-120nmay also be connected to one or more of the serial outputs 129a-129nof the port 102band one or more of the serial outputs 131a-131nof the port 102n.One or more of the serial links 121a-121nmay be connected to the serial outputs 127a-127nof the port 102a.The serial links 120a-120nand 121a-121nmay allow the packets of data to be transferred and/or received by one or more of the ports 102a-102n.The transferred data packets generally become outgoing data. The ports 102a-102nmay receive and transfer the outgoing data packets over the outputs 112a-112n.

[0020] Referring to FIG. 3, a detailed block diagram of an exemplary port 102ais shown. Each of the ports 102a-102ngenerally comprise a selectable multiplexer 140, a transmit block (or circuit) 142 and a receive block (or circuit) 144. The receive circuit 144 generally comprises a circuit 146 that may include a multiplexer circuit, a select circuit, serial to parallel converter, etc., a first receive circuit (e.g., RXPC) 148 and a second receive circuit (e.g., RXPC) 150. In one example, the first receive circuits 148a-148nand the second receive circuits 150a-150nmay be receive PLL circuits. The selectable multiplexer 140 may be configured by the scheduler 104, through management registers or through interface pins. When the connection from a particular port 102a-102nfor either transmit or receive needs to be changed, the configuration interface or the configuration registers may pass this new information to the particular port 102a-102n.

[0021] The classifier circuits 114a-114nhave been described in the context of separate circuits. However, the particular classifier circuits 114a-114nmay be embedded into the transmit blocks 142a-142n.In such an example, the transmit circuits 142a-142nand the classifier circuits 114a-114nmay be implemented as a single integrated circuit. More specifically, the classifier circuit 114aand the transmit circuit 142amay be implemented as a single integrated circuit within the port 102a.However, independently implemented transmit circuits 142a-142nand classifier circuits 114a-114nmay be implemented to meet the design criteria of a particular implementation.

[0022] The selectable multiplexer 140amay receive data packets from the serial inputs 126a-126n.The ports 102b-102nare generally connected to the port 102athrough the serial links 120a-120nand 12la-121n.One or more of the serial links 120a-120nare generally connected to the serial inputs 126a-126nof the port 102a.The selectable multiplexer 140amay transmit data through the serial outputs 127a-127n.The selectable multiplexer 140amay receive data through the serial inputs 126a-126n.The selectable multiplexer 140amay transmit or receive data packets in response to the port control signal PORTCTRa received at an input 152 from the scheduler 104. The selectable multiplexer generally presents the data packets to the receive circuit 144.

[0023] The data packet within the first receive PLL circuit 148a-148nmay be multiplexed to the ports 102a-102nthrough the serial connections 121a-121n.The selectable multiplexers 140a-140nare generally controlled by port control signals PORTCTRa-n generated by the scheduler 104. The scheduler 104 may synchronize the operation of all the ports 102a-102n,in response to the classifier control signals CLASSCTRa-n. A slot time may be defined as the time it takes to transfer a fixed block of data from one of the ports 102a-102nto another one of the ports 102a-102n.

[0024] The scheduler 104 may configure the selectable multiplexers 140a-140nin the ports 102a-102nfor a first slot time. The circuit 100 may use the scheduler 104 to look ahead by one slot time and set the selectable multiplexers 140a-140nfor a second slot time. The port 102a-102nmay receive the data packet in the first slot time and transmit the data packet during the second slot time to one or more of the ports 102a-102n.One of the receive PLL circuits 148a-148nor 150a-150nmay be connected to one of the receive circuits 146a-146nof the ports 102a-102nto perform the receive data function. However, a second one of the receive PLL circuits 148a-148nand/or 150a-150nmay start listening to the particular one of the ports 102a-102nfor the transmission that will occur in the next slot time. This look ahead may allow the lock time to overlap with the reception of data and may eliminate the receive lock time for back-to-back transfers.

[0025] In one example, if the lock time is in the order of the packet transmit time, two receive PLL circuits 148a-148nand 150a-150nmay be sufficient to reduce lock time. However, if the lock time is in the order of 10 times the transmit time, then more receive PLL circuits M, where M is an integer, may be needed. For example, 10 receive PLL circuits may be implemented. The particular number of receive circuits 148a-148nand 150a-150nmay be implemented accordingly to meet the design criteria of a particular implementation.

[0026] For the transmit side, the selectable multiplexers 140a-140nmay enable transmission on one or more serial outputs 127a-127n,128a-128nand/or 131a-131n.One of the serial links 120a-120nand 121a-121nmay carry the data packet for the current slot time and another of the serial links 120a-120nand 121a-121nmay send the data packet in the next slot time. The present invention may significantly improve the performance of the ports 102a-102nby eliminating (or reducing) the lock time.

[0027] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.