Variable gain amplifier stage

[0002] This invention relates, in general, to a variable gain amplifier stage and more particularly to a variable gain amplifier stage that has a constant bandwidth.

[0003] In general, the product of the gain of an amplifier stage and the bandwidth of the gain stage is fixed. Thus, if the gain stage has a variable gain, the bandwidth will vary inversely proportionately to the gain, so that, if the gain is increased, the bandwidth decreases and if the gain is decreased, the bandwidth increases. However, this increase in bandwidth is usually the result of a resonant peak in the frequency response of the amplifier stage.

[0004] Therefore, it is desirable to provide an amplifier stage that maintains a constant bandwidth over a wide range of gain settings, so that high signal quality can be maintained over a wide dynamic range.

[0005] Accordingly, in a first aspect, the present invention provides a variable gain amplifier stage comprising first and second input terminals for receiving a differential input signal, first and second input transistors, the first input transistor having a base electrode coupled to the first input terminal, a first current electrode coupled to a first supply rail and a second current electrode coupled to a first voltage controlled current source, and the second input transistor having a base electrode coupled to the second input terminal, a first current electrode coupled to the first supply rail and a second current electrode coupled to a second voltage controlled current source, a differential pair of transistors having respective base electrodes coupled to the second current electrodes of the first and second transistors, respectively, first current electrodes coupled to the first supply rail via load components and second current electrodes coupled together and to a third voltage controlled current source, wherein the gains of the first and second voltage controlled current sources are matched, and first and second output terminals coupled respectively to the respective first current electrodes of the differential pair of transistors.

[0006] An embodiment of the present invention will now be described, by way of example, with reference to FIG. 1 of the accompanying drawing, which is a schematic circuit diagram of an embodiment of a variable gain amplifier stage according to one embodiment of the present invention including bipolar transistors; and

[0007] FIG. 2 is a schematic circuit diagram of a second embodiment employing field effect transistors.

[0008] Thus, as shown in the drawing, a variable gain amplifier stage 1 includes a fixed bandwidth gain stage 2, an optional pre-emphasis gain stage 3 and an optional output buffer stage 4. The pre-emphasis gain stage 3 includes a pair of differential input terminals 5 and 6 coupled to respective base electrodes of a differential pair of bipolar transistors 7 and 8. Respective collector electrodes of the differential pair of transistors 7 and 8 are coupled, via respective resistors 9 and 10, to a power supply rail 11 operating at V_cc. Respective emitter electrodes of the differential pair of transistors 7 and 8 are coupled, via respective RC filters 12 and 13, to a single current source 14, which is coupled to a relative ground power supply rail 15 operating at V_ee. Each of the RC filters 12 and 13 comprises a resistor 56, 57 and a capacitor 18, 19 coupled in parallel between the respective emitter electrode of the respective transistor 7, 8 and the current source 14. The values of the resistors and the capacitors in the RC filters 12 and 13 are chosen so as to provide pre-emphasis filtering of an input signal to provide a peak in frequency response at high frequencies.

[0009] A differential output is taken from the respective collector electrodes of the differential pair of transistors 7 and 8 and provided as a differential input to respective base electrodes of a pair of emitter follower bipolar transistors 16 and 17 forming input transistors of the fixed bandwidth gain stage 2. Respective collector electrodes of the input transistors 16 and 17 are coupled to the power supply rail 11 and respective emitter electrodes of the input transistors 16 and 17 are coupled, via respective voltage controlled current sourcesss 18 and 19, to the relative ground power supply rail 15. Each of the voltage controlled current sources 18 and 19 is coupled to a control voltage terminal 20 providing a controllable voltage V_controlto control the gain of the voltage controlled current sources 18 and 19. The gains of the two voltage controlled current sources 18 and 19 are matched.

[0010] Respective DC current sinks 21 and 22 are coupled in parallel with respective ones of the two voltage controlled current sources 18 and 19. Each of the DC current sinks 21 and 22 includes a transistor 23, 24 coupled in series with a resistor 25, 26 such that the collector electrode of the transistor is coupled to the emitter electrode of the respective one of input transistors 16 and 17, the emitter electrode of the transistor is coupled to a first electrode of the respective resistor 25, 26, and the base electrode of the transistor is coupled to a fixed voltage terminal 27 providing a fixed voltage V_fixedto control the DC level of the DC current sinks 21 and 22, with the second electrode of the resistor being coupled to the relative ground power supply rail 15. The DC current sinks are used to adjust the current through the input transistors 16 and 17 to maximise the switching speed of the transistors since the switching speed is dependent on the current through a transistor.

[0011] Respective emitter electrodes of the input transistors 16 and 17 are also coupled, to provide an amplified differential signal to, respective base electrodes of a differential pair of transistors 28 and 29. Respective collector electrodes of the differential pair of transistors 28 and 29 are coupled to the power supply rail 11 via respective resistors 30 and 31 and respective emitter electrodes of the differential pair of transistors 28 and 29 are coupled together and, via a voltage controlled current source 32, to the relative ground power supply rail 15. The voltage controlled current source 32 is coupled to the control voltage terminal 20 so that the controllable voltage V_controlcontrols the gain of the voltage controlled current source 32. However, in this case, the gain of the voltage controlled current source 32 is predetermined so that the ratio of the gains of the voltage controlled current sources 18 and 32 maintains a flat frequency response of the stage 2.

[0012] Thus, it will be seen that since the voltage controlled current sources 18, 19 and 32 are controlled by the same voltage source V_control, a decrease in the differential pair tail current, will increase the bandwidth and decrease the gain of the stage, but a decrease in the current through the emitter follower transistors will decrease the bandwidth of the stage. Therefore, by carefully controlling the ratio of the gains between the voltage controlled current sources 18 and 19, on the one hand, and voltage controlled current source 32, on the other, a constant bandwidth can be maintained.

[0013] The output buffer stage 4 includes a pair of emitter follower transistors 36 and 37. A differential output is taken from the respective collector electrodes of the differential pair of transistors 28 and 29 and provided as a differential input to respective base electrodes of the pair of emitter follower transistors 36 and 37. Respective collector electrodes of the emitter follower transistors 36 and 37 are coupled to the power supply rail 11 and respective emitter electrodes of the emitter follower transistors 36 and 37 are coupled, via respective current sources 38 and 39, to the relative ground power supply rail 15. A differential output is taken from the respective emitter electrodes of the emitter follower transistors 36 and 37 and coupled to a pair of differential output terminals 40 and 41 to provide the differential output of the variable gain amplifier stage.

[0014] It will be appreciated that the above description has been given by way of example only and that a person skilled in the cart can make varios modifications and improvements without departing from the scope of the present inivention. For example, although the various transistors, particularly the transistors forming the DC current sinks, have been shown as bipolar transistors, it will be appreciated that they could alternatively be formed as Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) without departing from the scope of the present invention. For example, biopolar transistors 7, 8, 16, 17, 21, 22, 28, 29, 36 and 37 of FIG. 1 are respectively replaced in FIG. 2 by field effect transistors 70, 80, 160, 170, 210, 220, 280, 290, 360 and 370.