Etching method

[0002] 1. Field of the Invention

[0003] The present invention relates to an etching method used in a method of manufacturing a semiconductor device, and more particularly, a method of dry etching an SiC film and a method of manufacturing a multilayer wiring structure using an SiC film.

[0004] The present application is based on Japanese Patent Application No. 295905/2000, filed on Sep. 28, 2000, the contents of which is incorporated herein by reference.

[0005] 2. Description of the Related Art

[0006] As semiconductor device elements become smaller, it is essential to form smaller multilayer wiring for the semiconductor device. In addition, as the semiconductor device is operated at a lower voltage, a higher speed, or the like, it is necessary to form an interlayer insulating film having a lower dielectric constant.

[0007] More specifically, in a semiconductor device of a logic system, increased resistance due to smaller wiring and increased parasitic capacitance between wirings results in a reduction of the semiconductor device operation speed. Thus, it is essential to form a small multilayer using a low dielectric constant film as an interlayer insulating film (e.g., a silisesquioxane such as hydrogen silsesquioxane, hereinafter referred to as HSQ) as an interlayer insulating film with a low dielectric constant.

[0008] The small wiring width and short wiring pitch result in an increase in the aspect ratio of the wiring and an increase in the aspect ratio of a space between wirings. As a result, techniques for forming a strip of minute wiring longitudinally and embedding an interlayer insulating film in a space between minute wirings become more difficult. Thus, the related art semiconductor device manufacturing process is complicated, and the number of subprocesses in the related art manufacturing process increases.

[0009] In the related art system, a groove wiring technique (i.e., a damascene technique) forms a wiring groove in an interlayer insulating film and embeds a wiring material such as copper (i.e., Cu) in the wiring groove by using chemical mechanical polishing (hereinafter referred to as CMP). However, when a wiring groove or a via hole is formed by a reactive ion etching (hereinafter referred to as RIE) process, it is necessary to form an etching stopper layer.

[0010] The etching stopper layer is an insulating film with an etching speed different from that of an interlayer insulating film where the wiring groove or the via hole is formed. Various related art techniques using an insulating film with a low dielectric constant as the inter layer insulating film and using a silicon nitride film (SiN film) or a silicon oxide nitride film (SiON film) as the etching stopper layer have been proposed. For example, but not by way of limitation, Japanese Patent Application Laid-open No. Heisei 10-116904 and Japanese Patent Application Laid-open No. Heisei 10-229122 disclose related art manufacturing techniques.

[0011] FIGS. 1A to 1C illustrate cross sectional views of a related art manufacturing process of a dual damascene structure. As shown in FIG. 1A, a copper lower layer wiring 101 is formed over a semiconductor substrate (not shown) via an insulating film. Then, a SiN film 102 is formed to cover the copper lower layer wiring 101.

[0012] Next, an interlayer insulating film 103 is deposited on the SiN film 102, and the surface of the interlayer insulating film 103 is leveled by CMP. The interlayer insulating film 103 is a silicon oxide film formed in plasma by using a chemical vapor deposition (hereinafter referred to as CVD) method.

[0013] Next, using a related art photolithography technique and a related art dry etching technique, a via hole 104 that reaches the surface of the SiN film 102 is formed in the interlayer insulating film 103. Further, a wiring groove 105 is formed in the interlayer insulating film 103. After the via hole 104 and the wiring groove 105 are formed, a resist mask used as an etching mask is removed by using a related art ashing method that ashes the resist mask as an organic film with an oxygen plasma. In the related art ashing process, as shown in FIG. 1A, the copper lower layer wiring 101 is protected by the SiC film 102. Therefore, the copper lower layer wiring 101, which is otherwise easily oxidized, is not exposed to the oxygen plasma, and is protected from the oxidation.

[0014] Next as shown in FIG. 1B, using the interlayer insulating film 103 as an etching mask, the SiN film 102 is dry-etched by RIE to form a via hole 104athat reaches the surface of the lower layer wiring 101. The dry etching of the SiN film 102 is performed by introducing a gaseous mixture of CH₂F₂, O₂, and Ar into a space between parallel plate electrodes. The gaseous mixture is then plasma-excited with a high frequency energy of 13.56 MHz, which is applied between the parallel plate electrodes. In the dry etching step, a ratio of an etching rate of the SiN film 102 to that of the interlayer insulating film 103 (i.e., a selection ratio) is about 3 to 5, and the film thickness of the SiN film 102 is about 50 nm.

[0015] As illustrated in FIG. 1C, after a thin tantalum nitride (TaN) film and a copper film are laminated, the lamination film is processed by CMP, so that a barrier layer 106 and a groove wiring 107 are formed in a predetermined region of the interlayer insulating film 103. The barrier layer 106 and the groove wiring 107 are electrically connected to the copper lower layer wiring 101. By the above related art processes, the related art dual damascene wiring structure can be obtained.

[0016] However, the related art as described above has various problems and disadvantages. For example, but not by way of limitation, since the dielectric constant of the etching stopper layer increases, the parasitic capacitance between the copper lower layer wiring 101 and the upper layer wiring 107 in the multilayer wiring structure increases. In addition, a parasitic capacitance between wirings of the same layer increases due to a fringe effect generated between wirings of the same layer through the SiN film 102.

[0017] Further, in the above described example, a relative dielectric constant of the SiN film is 7 to 8. If the interlayer insulating film is formed using an HSQ film with a relative dielectric constant of about 3, the parasitic capacitance at least doubles. Thus, the operation speed of the semiconductor device (more specifically, a logic system of a semiconductor device) is reduced. Alternatively, since a groove wiring cannot be formed using a low dielectric constant film as an interlayer insulating film, there is a limitation on a low dielectric constant of the interlayer insulating film.

[0018] It is an object of the present invention to provide a simple etching method in which a low dielectric constant film can be effectively used as an interlayer insulating film and to reduce parasitic capacitance between groove wirings, by easily performing dry etching of an SiC film.

[0019] It is another object of the present invention to shorten a manufacturing process and reduce a manufacturing cost of a semiconductor device.

[0020] To overcome the aforementioned related art problems and to achieve at least the aforementioned objects, a method of etching a silicon carbide film is provided, comprising forming a silicon carbide film on a semiconductor substrate, and etching said silicon carbide film with an etching gas that comprises a halogen compound and a nitrogen containing gas.

[0021] Additionally, a method of manufacturing a semiconductor device is provided, comprising (a) forming a wiring on a semiconductor substrate, (b) forming a silicon carbide film on said wiring, (c) forming an interlayer insulating film on said silicon carbide film, (d) etching said interlayer insulating film to form a via hole by a first etching gas, and (e) etching said silicon carbide film that is exposed in said via hole, by a second etching gas comprising a halogen compound and a nitrogen containing gas.

[0022] Further, a method of manufacturing a semiconductor device is provided, comprising (a) forming a wiring on a semiconductor substrate, (b) forming a first silicon carbide film on said wiring, (c) forming a first interlayer insulating film on said first silicon carbide film, (d) forming a second silicon carbide film on said first interlayer insulating film, (e) forming a second interlayer insulating film on said second silicon carbide film, (f) etching said second interlayer insulating film an d said second silicon carbide film, and then etching said first interlayer insulating film to form a via hole by a first etching gas, (g) etching said second interlayer insulating film to form a wiring groove by using said first silicon carbide and said second silicon carbide as an etching stopper, and (h) etching said first silicon carbide film exposed in said via hole by a second etching gas comprising a halogen compound and a nitrogen containing gas.

[0023] Therefore, according to one embodiment of the etching method of the present invention, in a dry etching of an SiC film used in manufacturing a semiconductor device, a gas containing nitrogen is added to an etching gas containing a halogen compound. Such a halogen compound is a fluorine compound. The fluorine compound is fluorocarbon, nitrogen trifluoride (NF₃), or sulfur hexafluoride (SF₆). The fluoro-carbon is CF₄, CHF₃, CH₂F₂, CH₃F, or C₄F₈. Here, an oxygen gas may be mixed with the etching gas containing the fluoro-carbon.

[0024] Alternatively, according to the etching method of the present invention, in a dry etching of a lamination film of an SiC film and an interlayer insulating film which is made of, a silicon oxide film used for a semiconductor device, a silsesquioxane insulating film, or a silica film including at least one bonding of an Si—H bonding, an Si—CH₃bonding and an Si—F bonding, a gas containing nitrogen is added to an etching gas containing a halogen compound, which is used in dry etching of the interlayer insulating film in the dry etching of the SiC film.

[0025] Then, the gas containing nitrogen is a nitrogen gas, an ammonia gas, or a nitrous oxide gas. An end point detection in the dry etching of the SiC film is performed by measuring an light emitting intensity in a wavelength of 387 nm from a reaction product CN.

[0026] According to the etching method of the SiC film of the present invention, the added nitrogen is plasma-excited and then chemically bonded to carbon (C) of the SiC film as a material to be etched, so that a reaction product CN with a high volatility is formed. Thus, the dry etching of the SiC film, which is difficult until now is very easy.

[0027] Alternatively, a method of manufacturing a semiconductor device, according to the represent invention is a method of manufacturing a multilayer wiring structure, including the steps of: forming an SiC film for covering on a lower layer wiring; forming an interlayer insulating film for covering the SiC film, and forming a via hole which reaches a surface of the SiC film and a wiring groove connecting with the via hole by dry-etching a predetermined region of the interlayer insulating film; removing the SiC film exposed in a region of the via hole by etching using the interlayer insulating film as an etching mask such that the via hole penetrates the SiC film to the surface of the lower layer wiring; and filling the penetrating via hole and the wiring groove with a conductive material to form a groove wiring connecting with the lower layer wiring, and removal of the SiC film by etching is performed by adding the gas containing nitrogen to the etching gas containing the halogen compound.

[0028] Alternatively, a method of manufacturing a semiconductor device, according to the present invention, is in manufacturing a layer wiring structure, a method of manufacturing a multilayer wiring structure, including the steps of: forming a first SiC film for covering on a lower layer wiring; forming a first interlayer insulating film, a second SiC film, and a second interlayer insulating film in this order on the first SiC film; dry etching the second interlayer insulating film, the second SiC film, and the first interlayer insulating film in succession to form a via hole which reaches a surface of the first SiC film; dry etching a predetermined region of the second interlayer insulating film using the second SiC film as an etching stopper layer to form a wiring groove connecting with the via hole; after the formation of the wiring groove, removing the first SiC film exposed in a region of the via hole using the second interlayer insulating film as an etching mask such that the via hole penetrates the first SiC film to the surface of the lower layer wiring; and filling the penetrating via hole and the wiring groove with a conductive material to form a groove wiring connecting with the lower layer wiring, and removal of the SiC film is performed by adding the gas containing nitrogen to the etching gas containing the halogen compound. Here, the second interlayer insulating film may be made from two layers to be laminated of different kinds of insulating films.

[0029] Then, the interlayer insulating film, the first interlayer insulating film, or the second interlayer insulating film is made of a silicon oxide film, a silsesquioxane insulating film, or a silica film including at least one bonding of an Si—H bonding, an Si—CH₃bonding and an Si—F bonding. Also, the silsesquioxane insulating film is hydrogen silsesquioxane, methyl silsesquioxane, methylated hydrogen silsesquioxane, or fluorinated silsesquioxane. Further, the lower layer wiring or the groove wiring is made of copper (i.e., Cu).

[0030] As described above, according to the present invention, the dry etching of the SiC film is easily performed, and the SiC film can be easily applied as a stopper layer in manufacturing of a multiplier wiring structure such as a dual damascene structure. Thus, a parasitic capacitance between a lower layer wiring and an upper layer wiring in the multilayer wiring structure is reduced, and a parasitic capacitance between wiring layers of the same layer due to a fringe effect generated between wirings of the same layer is largely reduced. Further, a low dielectric constant film can be effectively used as an interlayer insulating film, and a parasitic capacitance between groove wirings can be reduced.

[0031] Also, a lamination film of the interlayer insulating film and the SiC film, constituting a semiconductor device, can be processed by etching using a simple method. In addition, a manufacturing process is shortened and a manufacturing cost of a semiconductor device is reduced.

[0032] The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] FIGS. 1A to 1C illustrate cross sectional views of a manufacturing process of a related art wiring structure;

[0034] FIGS. 2A to 2C illustrate cross sectional views of a manufacturing process of a wiring structure according to a first preferred embodiment of the present invention;

[0035] FIG. 3 is a graph representing a nitrogen addition effect in etching of an SiC film according to the first preferred embodiment of the present invention; and

[0036] FIGS. 4A to 4G illustrate cross sectional views of a manufacturing process of a wiring structure according to a second preferred embodiment of the present invention.

[0037] When a related art groove wiring using copper as a conductive material is formed, since copper is easily oxidized, it is necessary to form an insulating film without oxygen as the above etching stopper layer. Also, to reduce parasitic capacitance between wirings, an insulating film with a low dielectric constant is desired. The present invention uses an effective etching gas in dry etching of a SiC film by an RIE, which is not known in the related art.

[0038] To overcome at least the aforementioned problems and disadvantages, a trial experiment was performed, considering that the interlayer insulating film and the SiC film can be etched using similar etching gases. Accordingly, the first and second preferred embodiments of the present invention were developed.

[0039] FIGS. 2A to 2C illustrate cross sectional views of manufacturing process orders of a dual damascene wiring structure according to the first preferred embodiment of the present invention. As shown in FIG. 2A, a lower layer wiring 1 is formed using copper (i.e., Cu) over a semiconductor substrate through an insulating film. Then, an SiC layer 2 having a film thickness of about 50 nm is formed to cover the lower layer wiring 1. The SiC layer 2 is formed by a plasma CVD method using trimethylsilane (SiH(CH₃)₃) as a reaction gas. The SiC layer 2 has an insulation characteristic, and its relative dielectric constant is approximately 4.6.

[0040] Next, an interlayer insulating film 3 is formed using a silicon oxide film on the SiC layer 2. Then, using a well-known photolithography and dry etching techniques, a via hole 4 that reaches an upper surface of the SiC layer 2 is formed in the interlayer insulating film 3, and further, a wiring groove 5 is formed in the interlayer insulating film 3. Thereafter, a resist mask that is used as an etching mask is removed by an ashing method, as described above in the related art. In the ashing process of this resist mask, as shown in FIG. 2A, the lower layer copper (i.e., Cu) wiring 1 is protected by the SiC layer 2 against oxidation.

[0041] Next, as shown in FIG. 2B, the SiC layer 2 is dry-etched using the interlayer insulating film 3 as an etching mask, to form a via hole 4athat reaches the surface of the lower layer wiring 1. Here, dry etching of the SiC layer 2 is performed as follows. A mixture gas of, for example, but not by way of limitation, CH₂F₂, O₂, and Ar, to which a nitrogen gas (N₂) is introduced into a space between parallel plate electrodes. The nitrogen mixed gas is then plasma-excited with a high frequency energy of about 13.56 MHz, which is applied between the electrodes. In the above dry etching process, a ratio of an etching rate of the SiC layer 2 to that of the interlayer insulating film 3 (i.e., a selection ratio) is about 5 or larger. Etching of the SiC layer 2 is described in greater detail below based on FIG. 3.

[0042] In the etching process of the first preferred embodiment of the present invention, the related art problems of the etching step are overcome because an etching amount in the surface portion of the interlayer insulating film 3 is small. In addition, even if the SiC layer 2 is etched to expose the surface of the lower layer wiring 1, the surface of the lower layer wiring 1 is not oxidized.

[0043] In the above described dry etching of the SiC layer 2, an end point detection of etching may be performed by measuring a change in a light emitting intensity with a wavelength of 387 nm from CN as a reaction product in plasma. Here, the reaction product CN is a compound of SiC as an object to be etched, and the added nitrogen. Alternatively, in the case of the above described etching gas, the end point detection of etching may be performed by measuring a change in an light emitting intensity with a wavelength of 451 nm or 483 nm from CO as a reaction product.

[0044] Next, as illustrated in FIG. 2C, the related art process art is performed, so that after a thin tantalum nitride film and a copper (i.e., Cu) film are laminated, the lamination film is processed by CMP to form a barrier layer 6 and a groove wiring 7 in a predetermined region of the interlayer insulating film 3. By the above-described processes, a dual damascene wiring structure is formed.

[0045] Next, dry etching of the above SiC layer by RIE is described. FIG. 3 is a graph representing changes in etching rates with respect to a silicon oxide (SiO₂) film and an SiC film where nitrogen gas is added to the above mixture gas of CH₂F₂, O₂, and Ar. In FIG. 3, a CH₂F₂gas flow rate is about 20 sccm, an O₂gas flow rate is about 5 sccm, and an Ar gas flow rate is about 200 sccm. The x-axis of FIG. 3 represents an N₂gas flow rate, and the y-axis of FIG. 3 represents an etching rate with respect to the SiC film and the SiO₂film.

[0046] As shown in FIG. 3, when the nitrogen gas is not added to the mixture gas of CH₂F₂, O₂, and Ar, etching of the SiC film does not progress substantially, and the etching rate of the SiO₂film is greater than the etching rate of the SiC film.

[0047] As nitrogen gas is added, the etching rate of the SiC film increases substantially, while the etching rate of the SiO₂film remains substantially unchanged. Thus, a ratio of the etching rate of the SiC film to the etching ratio of the SiO₂film (i.e., the selection ratio) increases. A similar effect occurs when, instead of the SiO₂film an Si—O based insulating film with a low relative dielectric constant (e.g., the silsesquioxane insulating film), or the silica film including at least one bonding of, an Si—H bonding, an Si—CH₃bonding and an Si—F bonding, is used.

[0048] In an RIE for the SiC film, if a fluorocarbon gas such as CF₄, CHF₃, C₄F₈, or CH₃F is used instead of the CH₂F₂gas, the substantially same effect as the addition of nitrogen gas occurs.

[0049] In addition, even if nitrogen gas is added to a gas of a fluorine compound such as NF₃or SF₆, the above described etching rate effect occurs. In the case of a fluorine compound gas, a mixture of an O₂gas is not required because a gas mixture of this oxygen gas increases the amount of fluorine radical in the above plasma excitation, and a substantial amount of the fluorine radical can be formed by using the gas of the fluorine compound, such as NF₃or SF₆. Also, in the case of the fluorine compound gas, since an excess amount of organic polymer is not generated in etching, the mixture of the O₂gas is not required.

[0050] If a nitrous oxide (N₂O) gas or an ammonia (NH₃) gas is added instead of nitrogen gas, the above-described effect occurs, as the dry etching of the SiC film is performed very easily by adding the nitrogen contained gas.

[0051] In a dry etching process using ICP (inductive coupled plasma), a plasma excitation method is performed with a microwave, and a plasma excitation method with two frequencies, which are well known, except for the above plasma excitation method with a high frequency, is used. As a result, the effect by the above addition of the nitrogen contained gas occurs even in those cases.

[0052] In the present invention, the etching gas for the interlayer insulating film is almost identical to the etching gas for the SiC film. Therefore, it is an advantage of the present invention that a multilayer wiring structure such as a groove wiring can be simply manufactured, so that a manufacturing process of a semiconductor device is shortened and its manufacturing cost is reduced.

[0053] FIGS. 4A to 4G illustrate cross sectional views of a manufacturing process of a dual damascene wiring structure according to the second preferred embodiment of the present invention. Silsesquioxane with a low relative dielectric constant (e.g., an HSQ film) is used as an interlayer insulating film.

[0054] As shown in FIG. 4A, a lower layer wiring 8 is formed using a copper (i.e., Cu) film. Subsequently, a first SiC layer 9 having a film thickness of about 50 nm, a first HSQ film 10 having a film thickness of about 500 nm, a second SiC layer 11 having a film thickness of about 50 nm, and a second HSQ film 12 having a film thickness of about 500 nm, are sequentially laminated on the lower layer wiring 8. A coating solution as the HSQ film is applied onto the entire surface, baked at a temperature of about 150° C., and further subjected to a thermal treatment with a temperature of about 400° C., in a diffusion furnace, to form the HSQ films 10, 12. Then, a CMP stopper layer 13 is formed using a silicon oxide film having a film thickness of about 15 nm on the second HSQ film 12.

[0055] Next, as shown in FIG. 4B, a first resist mask 14 is formed by a well known photolithography technique. Using the first resist mask 14 as an etching mask, the CMP stopper layer 13, the second HSQ film 12, the second SiC layer 11, and the first HSQ film 10 are dry-etched in succession to form a via hole 15 that reaches an upper surface of the first SiC layer 9. In the dry etching with respect to the CMP stopper layer 13, the first and second HSQ films 10, 12, a mixture gas of CH₂F₂, O₂and Ar is used as an etching gas. Then, in the dry etching of the second SiC layer 11, as described in the first embodiment, a predetermined amount of nitrogen gas is added to the above mixture gas.

[0056] Then as shown in FIG. 4C, the first resist etching mask 14 is removed by the above-described ashing method. In the ashing process, the SiC layer 9 protects the lower layer wiring 8 made of copper (i.e., Cu).

[0057] Next, as shown in FIG. 4D, using a second resist mask 16 having a wiring groove pattern as an etching mask, the CMP stopper layer 13 and the second HSQ film 12 are dry-etched to form a wiring groove 17. Here, the dry etching with respect to the CMP stopper layer 13 and the second HSQ film 5 is performed by plasma-exciting a mixture gas of C₄F₈, O₂, and Ar. When such an etching gas is used, since an etching rate of the second SiC layer 11 is reduced, the second SiC layer 11 functions as an etching stopper layer. Thus, the first HSQ film 10 is protected by the second SiC layer 11 against the dry etching.

[0058] Next, the second resist mask 16 used as the etching mask is removed by ashing method, such that the lower layer copper wiring 8 is protected by the SiC layer 9 against oxidation.

[0059] Next, as shown in FIG. 4E, using the CMP stopper layer 13 as an etching mask, the second SiC layer 11 and the first SiC layer 9 in the wiring groove 17 are dry-etched to form a via hole 15awhich reaches the surface of the lower layer wiring 8. In this process, the wiring groove 17 is changed into a wiring groove 17a.

[0060] In the dry etching at the second SiC layer 11 and the first SiC layer 9, a nitrogen gas or a nitrous oxide gas is added to a mixture gas of NF₃and Ar as a reaction gas, to perform a plasma excitation. In the above dry etching, a ratio of an etching rate of the SiC layer to that of the CMP stopper layer (i.e., a selection ratio) is about 10. Thus, after the above etching, the CMP stopper layer 13 has a sufficient film thickness of about 10 nm.

[0061] In the above dry etching of the SiC layer, an end point detection of etching is performed by measuring a change in an light emitting intensity with a wavelength of 387 nm from a CN as a reaction product in plasma. Here, the reaction product CN is a compound of the SiC layer as an object to be etched, and the added nitrogen.

[0062] Subsequently, as shown in FIG. 4F, a barrier layer 18 is formed to electrically connect with the lower layer wiring 8 in inner walls of the via hole 15a,the wiring groove 17aand the surface of the CMP stopper layer 13. Then, a copper film 19 having a film thickness of about 1000 nm is formed by a plating method or the like.

[0063] The copper film 19 and the barrier layer 18 are then processed by CMP, where the CMP stopper layer 13 is a CMP stopper film that protects the second HSQ film 12 against the effects of the CMP process.

[0064] By the above processes, as shown in FIG. 4G, groove wirings 20, 20aare formed over the lower layer wiring 8 through the first SiC layer 9 and the first HSQ film 10, which are an interlayer insulating film. Here, the groove wirings 20, 20asandwich the barrier layer 18 in the wiring groove 17anext to the second HSQ film 12. Then, the groove wiring 20 is connected with the lower layer wiring 8 through the via hole 15ain the first SiC layer 9 and the first HSQ film 10. Thus, a dual damascene wiring structure is obtained.

[0065] In this second embodiment, a Si—O based low dielectric constant film such as methyl silsesquioxane (called MSQ film) is used as silsesquioxane, except for an HSQ film, can be effectively used as an interlayer insulating film in a multilayer wiring structure. In addition, a parasitic capacitance between wirings in a damascene wiring structure is easily reduced. In particular, a parasitic capacitance between the lower layer wiring 8 and the groove wiring 20a,and a parasitic capacitance generated due to a fringe effect between the groove wirings 20 and 20ais largely reduced.

[0066] Even if the above silsesquioxane is methylated hydrogen silsesquioxane, or fluorinated silsesquioxane, except for an HSQ film and an MSQ film, the present invention can be applied as the above. Further, even if where, except for silsesquioxane, a silica film including at least one bonding of an Si—H bonding, an Si—CH₃bonding and an Si—F bonding, is used as an interlayer insulating film, the present invention can be applied as the above. Alternatively, if an organic insulating film is used as an interlayer insulating film, the present invention can be applied as the above.

[0067] If an SiC film is dry-etched using a compound containing fluorine as an etching gas, the SiC film is effectively etched by an addition of a gas containing nitrogen. The present invention is not limited to the case of a compound gas containing fluorine. Even if a compound of halogen such as chlorine is used as an etching gas, the SiC film can be effectively etched by an addition of the gas containing nitrogen.

[0068] In the preferred embodiments of the present invention, a dual damascene wiring structure is used. However, the present invention is not limited thereto, and can be applied to the case where a commonly used wiring structure or a damascene wiring structure is formed, as the above. Further, the present invention is not limited to the case where a wiring structure is formed, and can be applied to the case where an SiC film used for manufacturing a semiconductor device is processed, as described above.

[0069] The present invention is not limited to the above embodiment, but various improvements and modifications may be naturally made in the scope not departing from the gist of the present invention.

[0070] As described above, according to the present invention, in the dry etching of the SiC film used for manufacturing a semiconductor device, a gas containing nitrogen is added to an etching gas containing a halogen compound. Then, the dry etching method of the SiC film is applied to the case where a multilayer wiring structure such as groove wirings is manufactured.

[0071] According to the present invention, the above dry etching of the SiC film is performed very easily, and the SiC film is effectively applied as a stopper layer to the case where a multilayer wiring structure such as a dual damascene structure is manufactured.

[0072] Therefore, it is an advantage of the present invention that a parasitic capacitance between a lower layer wiring and an upper layer wiring in the multilayer wiring structure is reduced, and a parasitic capacitance between wiring layers of the same layer due to a fringe effect generated between wirings of the same layer is reduced. In addition, a low dielectric constant film can be effectively used as an interlayer insulating film, and a parasitic capacitance between groove wirings can be reduced by using a simple method. Further, a manufacturing process may be shortened and a manufacturing cost of a semiconductor device may be reduced.

[0073] As additional advantages according to the present invention, a high integration, a high speed operation, and a multi-function in a semiconductor device are further improved as a semiconductor element becomes smaller.

[0074] The present invention is not limited to the above embodiments, and it is contemplated that numerous modifications may be made without departing from the spirit and scope of the invention. The etching method, as described above with reference to the figures, is a merely an exemplary embodiment of the invention, and the scope of the invention is not limited to these particular embodiments. Accordingly, other structural configurations may be used, without departing from the spirit and scope of the invention as defined in the following claims.