Blocked net buffer insertion

[0002] This invention relates to the field of integrated circuit design. More particularly, this invention relates to a method and system for timing optimization during integrated circuit design.

[0003] Integrated circuits consist of a large number of electronic components having individual logic devices or groups of logic devices, which are formed on a substrate, typically a silicon wafer. The components, or cells, are typically grouped to reduce the size and increase the speed of the integrated circuit. Each cell has one or more pins that are connected by wires to one or more pins of other cells of the integrated circuit. The pins are structures that function as the input or output of a cell, and the wires are structures that function as the interconnections between cells. A net is a set of pins connected by a set of wires.

[0004] Placement of the components in optimum positions provides efficient layout of the components in the integrated circuit, and tends to reduce integrated circuit costs, signal delays, size, and the like. Because integrated circuits typically contain hundreds of thousands if not millions of components, the task of optimizing the placement of components on in integrated circuit is typically not practical without the aid of computerized layout tools.

[0005] Designers address timing issues associated with the propagation of signals from one cell to another. For the integrated circuit design to function properly, the numerous signals that are transmitted between cells of the net are typically synchronized. Thus, designers make allowance for the delays inherent in the components of the integrated circuit and the routing between the components. Thus, faster routes must be synchronized with slower routes for the integrated circuit to function properly.

[0006] In addition to ensuring that electrical and timing aspects of the integrated circuit design are attended to, the physical layout of an integrated circuit can also present rigorous problems for the designer to overcome. For example, design constraints having a high priority may place some components in certain areas of the integrated circuits, which components may later become effectual blockages to other components having design constraints with a low priority. Thus, the low priority components need to be rerouted around the high priority blockages. Such rerouting must also take in to consideration the timing issues discussed below.

[0007] There is a need, therefore, for a method of routing a net around blockages, especially large blockages, whereby the net is effectively rerouted and timing considerations are accounted for.

[0008] The above and other needs are met by a method of determining a desired connection path between a pair of points of a net separated by one or more blockages which will avoid path delays and ramp time violations without placing buffers within any of the blockages.

[0009] In a preferred embodiment, the method includes the steps of identifying a constructed path between the pair of points of the net, identifying the distance between the pair of points corresponding to the constructed path and comparing the distance to an optimal distance value, calculating a middle point of the constructed path when the distance between the pair of points corresponding to the constructed path is greater than the optimal distance value, and determining if the middle point is covered by a blockage.

[0010] If the middle point is not covered by a blockage, the union of each path between the middle point and each of the points of the pair of points is identified as the desired connection path,

[0011] If the middle point is covered by a blockage, visible angles of the blockage are determined. Next, first and second paths extending between the points of the pair of points and passing through at least one of the determined visible angles of the blockage are determined. Penalties for the first and second paths are then determined and compared. The one of the first and second paths having the least penalties is then selected as the desired connection path.

[0012] In another aspect, a computer program having logic elements for accomplishing the foregoing steps is provided.

[0013] Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:

[0014] FIG. 1 is a representational diagram of an integrated circuit,

[0015] FIG. 2 is a representational diagram of a net made up of interconnected cells of an integrated circuit,

[0016] FIG. 3 is a representational diagram of a net having a blockage,

[0017] FIG. 4 shows a buffer insertion scheme for the net of FIG. 3 determined in accordance with a preferred embodiment of the invention,

[0018] FIG. 5 is a flow chart of preferred steps in a method for determining a buffer insertion scheme for nets having blockages,

[0019] FIG. 6 is a representational diagram of a first constructed path for a simplified buffer insertion scheme,

[0020] FIG. 7 is a representational diagram illustrating visible angles in connection with a net blockage, and

[0021] FIG. 8 is a representational diagram illustrating selection of an optimal path between two points separated by a blockage, according to a complex buffer insertion procedure.

[0022] Referring now to FIG. 1 there is shown an integrated circuit 10 provided on a substrate 12, such as a silicon wafer, having a plurality of components made by layering various materials on the substrate 12. The arrangement of the components on the substrate 12 is described in terms of a geometric description referred to as a layout, characterized by a plurality of planar geometric shapes separated from one another and arranged on the substrate 12. Masks or patterns corresponding to the layout are used to render the desired shapes in the desired locations on the substrate 12 in a series of photolithographic steps.

[0023] For example, the circuit 10 includes a plurality of functional circuit blocks formed thereon, such as central processing unit 14, read-only memory (ROM) 16, clock/timing unit 18, random access memories (RAM) 20, and input/output interface (I/O) 22. The circuit 10 also includes numerous (e.g., from about 10,000 to several million) cells 24. The cells 24 and the other components of the circuit 10 are interconnected or routed according to a desired logical design of the circuit corresponding to a desired application. This routing or interconnection is accomplished by electrically conductive lines or traces located such as in vertical channels 26 and horizontal channels 27 between the cells 24.

[0024] Each cell 24 corresponds to a logic element, such as a gate, or to a combination of logic elements interconnected to perform a specific function. The cells 24 are typically grouped to produce a device such as an application specific integrated circuit. Each cell 24 has one or more pins that are connected by wires to one or more pins of other cells of the circuit. A net is the set of pins connected by the wire. An example of a net 30 is shown in FIG. 2. In FIG. 2, p₀is the first output pin of the net 30 and p₁is the last input pin of the net. The pin p₀is referred to as the driver of the net 30 and the pin p₁is the driven pins. Typically, there are a plurality of driven pins, each being designated p₁, p₂, p₃, . . . , p_n, with n representing the number of driven pins.

[0025] As a part of arranging the components of the circuit 10, buffers are added to preferably minimize path delays or to minimize the ramptime violation of the driver of the net. A buffer is a structure that propagates the same signal that it receives, without logical modification. Placement of the buffers is complicated when a net contains one or more blockages. A blockage is a region of the net where cells, including buffers, cannot be placed, and over which wires of the net cannot be routed. Thus, a net scheme is preferably determined to reduce path delays and ramp time violations without placing buffers within the blockage.

[0026] FIG. 3 is a representational diagram of the net 30 crossing a blockage 34. The wire between the driven pin p₁and the driving pin p₀represents a path having too great a length such that the net 30 has a ramptime violation. The invention relates to a method for determining an appropriate buffer insertion scheme for nets such as net 30 having blockages, especially large blockages, to reduce net delays and avoid ramp time violations. FIG. 4 represents a finished complex buffer insertion scheme according to a preferred embodiment of the invention, wherein buffers 40, 42, and 44 are inserted into the net 30 to define a new path in accordance with an iterative optimization method. The path 46 is selected to reduce both path delays and ramptime violations without passing through the blockage 34.

[0027] For reasons as given more completely below, a simplified buffer insertion procedure cannot always be used, because it tends to produce the net as depicted in FIG. 6, which has ramptime violations. Thus, according to the procedure described herein, the simplified buffer insertion procedure is used in those situations where it produces acceptable results, and a more detailed buffer insertion procedure is used in those situations where the more simplified buffer insertion procedure does not produce acceptable results.

[0028] The input into the overall procedure is a net. For example, if p₀is the driver of the net, p₁, . . . , p_nare then driven pins of the net. The maximal pin of the net, or in other words the driven pin at the maximal distance from the driver is p_m, where m is at least one and no greater than n. The maximal distance of this pin p_mis denoted by d_m. If d_mis less than or equal to D₀, then the simplified buffer insertion procedure may be appropriately used to determine the modifications to be applied to the input net. D₀is an optimal distance between two buffers of the same type of chain and is preferably calculated as follows:

[0029] D₀=(MaxCapacity(p_out)−PinCapacity(p_in))/(UnitCapacity)

[0030] Where:

[0031] p_outis the output pin of the buffer,

[0032] p_inis the input pin of the buffer,

[0033] MaxCapacity is the maximal allowed capacity of the net driven by the pin p_out,

[0034] PinCapacity is the capacity of the driven pin p_in, and

[0035] UnitCapacity is a coefficient selected such that UnitCapacity×WireLength(p) equals the capacity of the wire, where WireLength(p) is equal to the length of the wire connecting the driven pin p _in, with the driver.

[0036] An example of a simplified buffer insertion procedure is given with more detail hereafter.

[0037] However, if d_mis greater than D₀, then the more detailed or complex procedure to construct an optimal path is applied to the input net, which detailed procedure is also described with more detail below.

[0038] The main complexity of the simplified buffer insertion procedure is to choose a subset of driven pins, which are designated to the new buffer, which become the new driving pin for the selected subset of driven pins. There are many ways in which a subset of driven pins can be chosen. For example, all subsets of the initial set of driven pins can be examined one by one and the best subset can be selected. This method gives the best simplified solution, but has a complexity that is exponential with the number of driven pins.

[0039] As a more preferred alternative, the driven pins are sorted by some feature. For example, during a resynthesis procedure there is preferably performed a ramptime optimization and a timing optimization. During the ramptime optimization stage, the following value is preferably calculated for each driven pin p:

[0040] Cap(p)=PinCapacity(p)+UnitCapacity×WireLength(p)

[0041] The driven pins are preferably sorted in decreasing order of the calculated values. During the timing optimization stage, MaximalTime(p) is calculated for each driven pin p, and the driven pins are sorted in increasing order of the calculated values. For example, if the set {p₁, . . . , p)}is the sorted set of driven pins, the subsets S_i={p₁, . . . , p_i}are examined step by step, and the best subset is selected. This method provides acceptable results and has linear complexity, rather than the exponential complexity of the method first listed above.

[0042] However, as mentioned above, such simplified procedures tend to produce the flawed results as depicted in FIG. 6 where the wires of the net have lengths that create ramptime violations.

[0043] Turning now to FIG. 5, there is shown a flow chart of preferred steps in a complex method for determining the path for buffer insertions. In an initial step 50, input information is selected corresponding to the path to be constructed by inserting a buffer. The output to eventually be realized by the complex procedure is depicted in FIG. 8. Each of the depicted pins is considered to be a point on the integrated circuit having an abscissa location (x) and an ordinate location (y). In a preferred embodiment, the first point of the initial constructed, path is p₁, at location (x₁,y₁) and the last point is p₂at location (x₂,y₂). An optimal path P is defined as OptimalPath, where P=OptimalPath (p₁,p₂,r). The r parameter is preferably an integer included to avoid an infinite loop in the iterative method of FIG. 5. Thus, for a given value of r, P is the optimal path connecting the points p₁and p₂.

[0044] In step 52, r is compared to a parameter MaxDepth, which corresponds to the maximum number of iterations through the procedure, and preferably has a value of from about ten to about fifteen. If r is at least equal to MaxDepth, then at step 54 the procedure returns the currently determined optimal path of P={(p₁,p₂)}.

[0045] If it step 52 the input parameter r is less than MaxDepth, then at step 56 the distance d=|x₁−x₂|+|y₁−y₂|between points p₁and p₂is calculated. At 58, the value for d calculated in step 52 is compared to the distance D₀. If d is less than or equal to D₀, then the procedure returns to step 54 to present the current path as the optimal path. If d is greater than D₀, the procedure continues to step 60.

[0046] In step 60, a middle point p is calculated, where p=((x₁+x₂)2,(y₁+y₂)2). In the next step 62, the method checks whether the middle point p is covered by a blockage. The circuit is preferably divided into square logical sections using horizontal and vertical lines. Each of the sections is preferably referred to as a tile s. A characteristic B(s) is assigned to each tile s, where B(s) is equal to zero if the tile is not covered by any blockages, and B(s)=n if the tile s is covered by n blockages. A blockage is considered to be large if both sides of the blockage are greater than D₀.

[0047] If the midpoint p is not covered by a blockage, then the procedure proceeds to step 64. In step 64, (and with reference back to step 50) the program recursively calls itself twice, first for the input parameters (p₁,p,r), and secondly for the input parameters (p,p₂,r), where P₁=OptimalPath(p₁,p,r) and P₂=OptimalPath(p,p₂,r). At step 66, the path P is returned as the union of paths P₁and P₂, e.g., P=P₁∪P₂.

[0048] If at step 62 the point p is covered by some blockage n, then at step 68 visible angles p′ and p″ of the blockage n are determined for the point p₁. For example, with reference to FIG. 7, the angles A and C are “visible” for point D. Thus, if a point is located in the side of a blockage, the ends of the side are referred to as “visible.” As a further example of this, it is seen that the angles A and D are visible for the point E. Therefore, it is understood that if a point is located outside a blockage and only two angles are visible from the point, then the angles are considered as visible from the point. As an example of this, it is understood that the angles B and C are visible from the point F. However, if a point is located outside of a blockage and more than two angles are visible from the point, then the two outer angles are considered as visible, but the interior angles are not considered as visible. Thus, in FIG. 7, the angles B and D are understood to be visible from the point G.

[0049] In step 70, the procedure recursively calls itself four times to obtain four paths:

[0050] P′₁=OptimalPath(p₁,p′,r+1)

[0051] P′₂=OptimalPath(p′,p₂,r+1)

[0052] P″₁=OptimalPath(p₁,p″,r+1)

[0053] P″₂=OptimalPath(p″,p₂,r+1)

[0054] Where p′ and p″ are the two visible angles from point p₁. A first path P₁is defined as the union of the first and second paths, e.g., P₁=P′₁∪P′₂and a second path P₂is defined as the union of the third and fourth paths, e.g., P₂=P″₁∪P″₂.

[0055] In step 72, penalties are calculated for the paths P₁and P₂obtained in step 70. The penalty of a path P is defined as a pair k(P), Violation(P), where k(P) is the number of edges of the path and Violation(P) is the violation of the path. An edge is a pair of pints (p₁,p₂). The violation of a path is the sum of the violations of the edges of the path. For example, for a path between points p₁and p₂, where p₁=(x₁,y₁) and p₂=(x₂,y₂), the violation of the edge (p₁,p₂) equals max{0,PinCapacity(p_i)+(|x₁−x₂|)+|y₁−y₂|) X UnitCapacity−MaxCapacity(p₀)}, where p_iis the input pin and p_ois the output pin of the edge. In this example it is assumed that the wire between p₁and p₂is routed orthogonally rather than directly. If the wire between p₁and p₂is routed directly, then the length of the wire is determined using the quadratic equation with the point coordinates as the input.

[0056] In step 74, the penalties obtained in step 72 for the paths P₁and P₂are compared and the least penalty path is selected. That is, if Violation(P₁)<Violation(P₂) or Violation(P₁)=Violation(P₂) and K(P₁)≦K(P₂), then P₁is selected as the least penalty path. Otherwise, P₂is selected.

[0057] For further example with reference to FIG. 8, there is depicted a pair of points p₁and p₂separated by a pair of blockages, Blockage 1 and Blockage 2. Applying the procedure of FIG. 5, it is seen that the middle point p is covered by Blockage 1. The points a and f are visible angles of Blockage 1 for point p₁. The path P′₁connecting the point p₁and a is equal to {(p₁,a)}. The optimal path P″₂connecting the points a and p₂is equal to {(a,b), (b,c), . . . , (e,p₂)}. The path P″₁connecting the points p₁and f is equal to {(P₁, f)}. The optimal path P″₂connecting the points f and p₂is equal to {(f,g),(g,h), . . . , (m,p₂)}. The path P₁={(p₁,a),(a,b),(b,c),(e,p₂)}is better than the path P₂={(p₁,f),(fg),(g,h), . . . , (m,p₂)}in this example, because it is determined to be shorter and requires fewer buffer insertions. At each point between two pins, if a ramptime violation is determined, the procedure is called to determine another point at which to insert a buffer. In many instances, a simple buffer insertion procedure is sufficient, but in other instances the complex procedure is required.

[0058] The detailed buffer insertion process is preferably input with the point p₀, p_m, and r=0. The path generally referred to as P={(p₀,p′₁),(p′₁,p′₂), . . . , (p′_k,p_m)}is the result of the procedure. To determine the actual position at which the added buffer is to be inserted, the point (x′_j,y′_j) is determined, where (x′_j,y′_j) is the point closest to the point p′_jwhere j=1, . . . , k, such that buffer C_optcan be placed at (x′_j,y′_j). The point (x′_j,y′_m)can be determined with the help of a density driven procedure to assign cell coordinates, such as that described in copending U.S. patent application Ser. No. 09/841,824 filed Apr. 25, 2001, the entirety of which disclosure in incorporated herein by reference.

[0059] A total of k buffers C_optare inserted and coordinates (x′_jy′_j) are assigned to the j^thbuffer for each j=1, . . . , k. The pin p₀is connected with the input pin of the first buffer, the output pin of the j^thbuffer is connected with input pin of the (j+1)^thbuffer for each j=1, . . . , k−1, and the output pin of the k^thbuffer is connected with the pin p_m. The obtained buffer tree is returned as a result of the procedure.

[0060] In this manner, a method is presented for determining a net scheme for points separated by one or more blockages which preferably reduces path delays and ramp time violations without placing buffers within any of the blockages. The method includes determining if there is a ramptime violation, locating a midpoint between the two pins if there is a ramptime violation, determining whether the midpoint lies within a blockage, if the midpoint lies within a blockage then looking for a visible angles of the blockage, determining the best visible angle, and then looking at the edge between the new point and the original driven pin. If the new edge also has a ramptime violation, then the method is recursively called. When all of the new points around the blockages have been located, a buffer location routine is called to determine the nearest acceptable buffer location to the new points. The method is preferably incorporated as part of a timing driven resynthesis procedure wherein the circuit is tested for proper temporal relationships of the applied and produced electrical signals of the circuit and then modified in an attempt to optimize the temporal relationships.

[0061] Preferably, once the timing resynthesis is completed and all timing issued with the integrated circuit design have been resolved, the integrated circuit design is used to create mask layers and process flows whereby the integrated circuit design is physically embodied in an integrated circuit.

[0062] In other embodiments, the method of the invention is embodied in a computer program on a physical media, which computer program has logic elements for instructing a computing device to accomplish the method as described above. The invention may also be embodied in a computing device having inputs, outputs, memory, and a processor, which function in cooperation to accomplish the method described above.

[0063] The foregoing embodiments of this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.